1 #include <linux/device.h>
4 #include <linux/percpu.h>
5 #include <linux/init.h>
6 #include <linux/sched.h>
7 #include <linux/export.h>
8 #include <linux/nodemask.h>
9 #include <linux/cpumask.h>
10 #include <linux/notifier.h>
12 #include <asm/current.h>
13 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/hvcall.h>
17 #include <asm/machdep.h>
20 #include <asm/firmware.h>
22 #include "cacheinfo.h"
27 #include <asm/lppaca.h>
30 static DEFINE_PER_CPU(struct cpu
, cpu_devices
);
33 * SMT snooze delay stuff, 64-bit only for now
38 /* Time in microseconds we delay before sleeping in the idle loop */
39 static DEFINE_PER_CPU(long, smt_snooze_delay
) = { 100 };
41 static ssize_t
store_smt_snooze_delay(struct device
*dev
,
42 struct device_attribute
*attr
,
46 struct cpu
*cpu
= container_of(dev
, struct cpu
, dev
);
50 ret
= sscanf(buf
, "%ld", &snooze
);
54 per_cpu(smt_snooze_delay
, cpu
->dev
.id
) = snooze
;
58 static ssize_t
show_smt_snooze_delay(struct device
*dev
,
59 struct device_attribute
*attr
,
62 struct cpu
*cpu
= container_of(dev
, struct cpu
, dev
);
64 return sprintf(buf
, "%ld\n", per_cpu(smt_snooze_delay
, cpu
->dev
.id
));
67 static DEVICE_ATTR(smt_snooze_delay
, 0644, show_smt_snooze_delay
,
68 store_smt_snooze_delay
);
70 static int __init
setup_smt_snooze_delay(char *str
)
75 if (!cpu_has_feature(CPU_FTR_SMT
))
78 snooze
= simple_strtol(str
, NULL
, 10);
79 for_each_possible_cpu(cpu
)
80 per_cpu(smt_snooze_delay
, cpu
) = snooze
;
84 __setup("smt-snooze-delay=", setup_smt_snooze_delay
);
86 #endif /* CONFIG_PPC64 */
88 #ifdef CONFIG_PPC_FSL_BOOK3E
92 static u64 altivec_idle_wt
;
94 static unsigned int get_idle_ticks_bit(u64 ns
)
99 cycle
= div_u64(ns
+ 500, 1000) * tb_ticks_per_usec
;
101 cycle
= div_u64(ns
* tb_ticks_per_usec
, 1000);
109 static void do_show_pwrmgtcr0(void *val
)
113 *value
= mfspr(SPRN_PWRMGTCR0
);
116 static ssize_t
show_pw20_state(struct device
*dev
,
117 struct device_attribute
*attr
, char *buf
)
120 unsigned int cpu
= dev
->id
;
122 smp_call_function_single(cpu
, do_show_pwrmgtcr0
, &value
, 1);
124 value
&= PWRMGTCR0_PW20_WAIT
;
126 return sprintf(buf
, "%u\n", value
? 1 : 0);
129 static void do_store_pw20_state(void *val
)
134 pw20_state
= mfspr(SPRN_PWRMGTCR0
);
137 pw20_state
|= PWRMGTCR0_PW20_WAIT
;
139 pw20_state
&= ~PWRMGTCR0_PW20_WAIT
;
141 mtspr(SPRN_PWRMGTCR0
, pw20_state
);
144 static ssize_t
store_pw20_state(struct device
*dev
,
145 struct device_attribute
*attr
,
146 const char *buf
, size_t count
)
149 unsigned int cpu
= dev
->id
;
151 if (kstrtou32(buf
, 0, &value
))
157 smp_call_function_single(cpu
, do_store_pw20_state
, &value
, 1);
162 static ssize_t
show_pw20_wait_time(struct device
*dev
,
163 struct device_attribute
*attr
, char *buf
)
169 unsigned int cpu
= dev
->id
;
172 smp_call_function_single(cpu
, do_show_pwrmgtcr0
, &value
, 1);
173 value
= (value
& PWRMGTCR0_PW20_ENT
) >>
174 PWRMGTCR0_PW20_ENT_SHIFT
;
176 tb_cycle
= (tb_cycle
<< (MAX_BIT
- value
+ 1));
177 /* convert ms to ns */
178 if (tb_ticks_per_usec
> 1000) {
179 time
= div_u64(tb_cycle
, tb_ticks_per_usec
/ 1000);
183 time
= div_u64_rem(tb_cycle
, tb_ticks_per_usec
,
185 time
= time
* 1000 + rem_us
* 1000 / tb_ticks_per_usec
;
191 return sprintf(buf
, "%llu\n", time
> 0 ? time
: 0);
194 static void set_pw20_wait_entry_bit(void *val
)
199 pw20_idle
= mfspr(SPRN_PWRMGTCR0
);
201 /* Set Automatic PW20 Core Idle Count */
203 pw20_idle
&= ~PWRMGTCR0_PW20_ENT
;
206 pw20_idle
|= ((MAX_BIT
- *value
) << PWRMGTCR0_PW20_ENT_SHIFT
);
208 mtspr(SPRN_PWRMGTCR0
, pw20_idle
);
211 static ssize_t
store_pw20_wait_time(struct device
*dev
,
212 struct device_attribute
*attr
,
213 const char *buf
, size_t count
)
218 unsigned int cpu
= dev
->id
;
220 if (kstrtou64(buf
, 0, &value
))
226 entry_bit
= get_idle_ticks_bit(value
);
227 if (entry_bit
> MAX_BIT
)
232 smp_call_function_single(cpu
, set_pw20_wait_entry_bit
,
238 static ssize_t
show_altivec_idle(struct device
*dev
,
239 struct device_attribute
*attr
, char *buf
)
242 unsigned int cpu
= dev
->id
;
244 smp_call_function_single(cpu
, do_show_pwrmgtcr0
, &value
, 1);
246 value
&= PWRMGTCR0_AV_IDLE_PD_EN
;
248 return sprintf(buf
, "%u\n", value
? 1 : 0);
251 static void do_store_altivec_idle(void *val
)
256 altivec_idle
= mfspr(SPRN_PWRMGTCR0
);
259 altivec_idle
|= PWRMGTCR0_AV_IDLE_PD_EN
;
261 altivec_idle
&= ~PWRMGTCR0_AV_IDLE_PD_EN
;
263 mtspr(SPRN_PWRMGTCR0
, altivec_idle
);
266 static ssize_t
store_altivec_idle(struct device
*dev
,
267 struct device_attribute
*attr
,
268 const char *buf
, size_t count
)
271 unsigned int cpu
= dev
->id
;
273 if (kstrtou32(buf
, 0, &value
))
279 smp_call_function_single(cpu
, do_store_altivec_idle
, &value
, 1);
284 static ssize_t
show_altivec_idle_wait_time(struct device
*dev
,
285 struct device_attribute
*attr
, char *buf
)
291 unsigned int cpu
= dev
->id
;
293 if (!altivec_idle_wt
) {
294 smp_call_function_single(cpu
, do_show_pwrmgtcr0
, &value
, 1);
295 value
= (value
& PWRMGTCR0_AV_IDLE_CNT
) >>
296 PWRMGTCR0_AV_IDLE_CNT_SHIFT
;
298 tb_cycle
= (tb_cycle
<< (MAX_BIT
- value
+ 1));
299 /* convert ms to ns */
300 if (tb_ticks_per_usec
> 1000) {
301 time
= div_u64(tb_cycle
, tb_ticks_per_usec
/ 1000);
305 time
= div_u64_rem(tb_cycle
, tb_ticks_per_usec
,
307 time
= time
* 1000 + rem_us
* 1000 / tb_ticks_per_usec
;
310 time
= altivec_idle_wt
;
313 return sprintf(buf
, "%llu\n", time
> 0 ? time
: 0);
316 static void set_altivec_idle_wait_entry_bit(void *val
)
321 altivec_idle
= mfspr(SPRN_PWRMGTCR0
);
323 /* Set Automatic AltiVec Idle Count */
325 altivec_idle
&= ~PWRMGTCR0_AV_IDLE_CNT
;
328 altivec_idle
|= ((MAX_BIT
- *value
) << PWRMGTCR0_AV_IDLE_CNT_SHIFT
);
330 mtspr(SPRN_PWRMGTCR0
, altivec_idle
);
333 static ssize_t
store_altivec_idle_wait_time(struct device
*dev
,
334 struct device_attribute
*attr
,
335 const char *buf
, size_t count
)
340 unsigned int cpu
= dev
->id
;
342 if (kstrtou64(buf
, 0, &value
))
348 entry_bit
= get_idle_ticks_bit(value
);
349 if (entry_bit
> MAX_BIT
)
352 altivec_idle_wt
= value
;
354 smp_call_function_single(cpu
, set_altivec_idle_wait_entry_bit
,
361 * Enable/Disable interface:
362 * 0, disable. 1, enable.
364 static DEVICE_ATTR(pw20_state
, 0600, show_pw20_state
, store_pw20_state
);
365 static DEVICE_ATTR(altivec_idle
, 0600, show_altivec_idle
, store_altivec_idle
);
368 * Set wait time interface:(Nanosecond)
369 * Example: Base on TBfreq is 41MHZ.
373 * 196~390(ns): TB[60]
374 * 391~780(ns): TB[59]
375 * 781~1560(ns): TB[58]
378 static DEVICE_ATTR(pw20_wait_time
, 0600,
380 store_pw20_wait_time
);
381 static DEVICE_ATTR(altivec_idle_wait_time
, 0600,
382 show_altivec_idle_wait_time
,
383 store_altivec_idle_wait_time
);
387 * Enabling PMCs will slow partition context switch times so we only do
388 * it the first time we write to the PMCs.
391 static DEFINE_PER_CPU(char, pmcs_enabled
);
393 void ppc_enable_pmcs(void)
395 ppc_set_pmu_inuse(1);
397 /* Only need to enable them once */
398 if (__this_cpu_read(pmcs_enabled
))
401 __this_cpu_write(pmcs_enabled
, 1);
403 if (ppc_md
.enable_pmcs
)
404 ppc_md
.enable_pmcs();
406 EXPORT_SYMBOL(ppc_enable_pmcs
);
408 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
409 static void read_##NAME(void *val) \
411 *(unsigned long *)val = mfspr(ADDRESS); \
413 static void write_##NAME(void *val) \
416 mtspr(ADDRESS, *(unsigned long *)val); \
419 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
420 static ssize_t show_##NAME(struct device *dev, \
421 struct device_attribute *attr, \
424 struct cpu *cpu = container_of(dev, struct cpu, dev); \
426 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
427 return sprintf(buf, "%lx\n", val); \
429 static ssize_t __used \
430 store_##NAME(struct device *dev, struct device_attribute *attr, \
431 const char *buf, size_t count) \
433 struct cpu *cpu = container_of(dev, struct cpu, dev); \
435 int ret = sscanf(buf, "%lx", &val); \
438 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
442 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
443 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
444 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
445 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
446 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
447 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
449 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
450 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
452 /* Let's define all possible registers, we'll only hook up the ones
453 * that are implemented on the current processor
456 #if defined(CONFIG_PPC64)
457 #define HAS_PPC_PMC_CLASSIC 1
458 #define HAS_PPC_PMC_IBM 1
459 #define HAS_PPC_PMC_PA6T 1
460 #elif defined(CONFIG_6xx)
461 #define HAS_PPC_PMC_CLASSIC 1
462 #define HAS_PPC_PMC_IBM 1
463 #define HAS_PPC_PMC_G4 1
467 #ifdef HAS_PPC_PMC_CLASSIC
468 SYSFS_PMCSETUP(mmcr0
, SPRN_MMCR0
);
469 SYSFS_PMCSETUP(mmcr1
, SPRN_MMCR1
);
470 SYSFS_PMCSETUP(pmc1
, SPRN_PMC1
);
471 SYSFS_PMCSETUP(pmc2
, SPRN_PMC2
);
472 SYSFS_PMCSETUP(pmc3
, SPRN_PMC3
);
473 SYSFS_PMCSETUP(pmc4
, SPRN_PMC4
);
474 SYSFS_PMCSETUP(pmc5
, SPRN_PMC5
);
475 SYSFS_PMCSETUP(pmc6
, SPRN_PMC6
);
477 #ifdef HAS_PPC_PMC_G4
478 SYSFS_PMCSETUP(mmcr2
, SPRN_MMCR2
);
482 SYSFS_PMCSETUP(pmc7
, SPRN_PMC7
);
483 SYSFS_PMCSETUP(pmc8
, SPRN_PMC8
);
485 SYSFS_PMCSETUP(mmcra
, SPRN_MMCRA
);
486 SYSFS_SPRSETUP(purr
, SPRN_PURR
);
487 SYSFS_SPRSETUP(spurr
, SPRN_SPURR
);
488 SYSFS_SPRSETUP(pir
, SPRN_PIR
);
489 SYSFS_SPRSETUP(tscr
, SPRN_TSCR
);
492 Lets only enable read for phyp resources and
493 enable write when needed with a separate function.
494 Lets be conservative and default to pseries.
496 static DEVICE_ATTR(mmcra
, 0600, show_mmcra
, store_mmcra
);
497 static DEVICE_ATTR(spurr
, 0400, show_spurr
, NULL
);
498 static DEVICE_ATTR(purr
, 0400, show_purr
, store_purr
);
499 static DEVICE_ATTR(pir
, 0400, show_pir
, NULL
);
500 static DEVICE_ATTR(tscr
, 0600, show_tscr
, store_tscr
);
503 * This is the system wide DSCR register default value. Any
504 * change to this default value through the sysfs interface
505 * will update all per cpu DSCR default values across the
506 * system stored in their respective PACA structures.
508 static unsigned long dscr_default
;
511 * read_dscr() - Fetch the cpu specific DSCR default
512 * @val: Returned cpu specific DSCR default value
514 * This function returns the per cpu DSCR default value
515 * for any cpu which is contained in it's PACA structure.
517 static void read_dscr(void *val
)
519 *(unsigned long *)val
= get_paca()->dscr_default
;
524 * write_dscr() - Update the cpu specific DSCR default
525 * @val: New cpu specific DSCR default value to update
527 * This function updates the per cpu DSCR default value
528 * for any cpu which is contained in it's PACA structure.
530 static void write_dscr(void *val
)
532 get_paca()->dscr_default
= *(unsigned long *)val
;
533 if (!current
->thread
.dscr_inherit
) {
534 current
->thread
.dscr
= *(unsigned long *)val
;
535 mtspr(SPRN_DSCR
, *(unsigned long *)val
);
539 SYSFS_SPRSETUP_SHOW_STORE(dscr
);
540 static DEVICE_ATTR(dscr
, 0600, show_dscr
, store_dscr
);
542 static void add_write_permission_dev_attr(struct device_attribute
*attr
)
544 attr
->attr
.mode
|= 0200;
548 * show_dscr_default() - Fetch the system wide DSCR default
549 * @dev: Device structure
550 * @attr: Device attribute structure
551 * @buf: Interface buffer
553 * This function returns the system wide DSCR default value.
555 static ssize_t
show_dscr_default(struct device
*dev
,
556 struct device_attribute
*attr
, char *buf
)
558 return sprintf(buf
, "%lx\n", dscr_default
);
562 * store_dscr_default() - Update the system wide DSCR default
563 * @dev: Device structure
564 * @attr: Device attribute structure
565 * @buf: Interface buffer
566 * @count: Size of the update
568 * This function updates the system wide DSCR default value.
570 static ssize_t __used
store_dscr_default(struct device
*dev
,
571 struct device_attribute
*attr
, const char *buf
,
577 ret
= sscanf(buf
, "%lx", &val
);
582 on_each_cpu(write_dscr
, &val
, 1);
587 static DEVICE_ATTR(dscr_default
, 0600,
588 show_dscr_default
, store_dscr_default
);
590 static void sysfs_create_dscr_default(void)
592 if (cpu_has_feature(CPU_FTR_DSCR
)) {
596 dscr_default
= spr_default_dscr
;
597 for_each_possible_cpu(cpu
)
598 paca_ptrs
[cpu
]->dscr_default
= dscr_default
;
600 err
= device_create_file(cpu_subsys
.dev_root
, &dev_attr_dscr_default
);
604 #endif /* CONFIG_PPC64 */
606 #ifdef HAS_PPC_PMC_PA6T
607 SYSFS_PMCSETUP(pa6t_pmc0
, SPRN_PA6T_PMC0
);
608 SYSFS_PMCSETUP(pa6t_pmc1
, SPRN_PA6T_PMC1
);
609 SYSFS_PMCSETUP(pa6t_pmc2
, SPRN_PA6T_PMC2
);
610 SYSFS_PMCSETUP(pa6t_pmc3
, SPRN_PA6T_PMC3
);
611 SYSFS_PMCSETUP(pa6t_pmc4
, SPRN_PA6T_PMC4
);
612 SYSFS_PMCSETUP(pa6t_pmc5
, SPRN_PA6T_PMC5
);
613 #ifdef CONFIG_DEBUG_KERNEL
614 SYSFS_SPRSETUP(hid0
, SPRN_HID0
);
615 SYSFS_SPRSETUP(hid1
, SPRN_HID1
);
616 SYSFS_SPRSETUP(hid4
, SPRN_HID4
);
617 SYSFS_SPRSETUP(hid5
, SPRN_HID5
);
618 SYSFS_SPRSETUP(ima0
, SPRN_PA6T_IMA0
);
619 SYSFS_SPRSETUP(ima1
, SPRN_PA6T_IMA1
);
620 SYSFS_SPRSETUP(ima2
, SPRN_PA6T_IMA2
);
621 SYSFS_SPRSETUP(ima3
, SPRN_PA6T_IMA3
);
622 SYSFS_SPRSETUP(ima4
, SPRN_PA6T_IMA4
);
623 SYSFS_SPRSETUP(ima5
, SPRN_PA6T_IMA5
);
624 SYSFS_SPRSETUP(ima6
, SPRN_PA6T_IMA6
);
625 SYSFS_SPRSETUP(ima7
, SPRN_PA6T_IMA7
);
626 SYSFS_SPRSETUP(ima8
, SPRN_PA6T_IMA8
);
627 SYSFS_SPRSETUP(ima9
, SPRN_PA6T_IMA9
);
628 SYSFS_SPRSETUP(imaat
, SPRN_PA6T_IMAAT
);
629 SYSFS_SPRSETUP(btcr
, SPRN_PA6T_BTCR
);
630 SYSFS_SPRSETUP(pccr
, SPRN_PA6T_PCCR
);
631 SYSFS_SPRSETUP(rpccr
, SPRN_PA6T_RPCCR
);
632 SYSFS_SPRSETUP(der
, SPRN_PA6T_DER
);
633 SYSFS_SPRSETUP(mer
, SPRN_PA6T_MER
);
634 SYSFS_SPRSETUP(ber
, SPRN_PA6T_BER
);
635 SYSFS_SPRSETUP(ier
, SPRN_PA6T_IER
);
636 SYSFS_SPRSETUP(sier
, SPRN_PA6T_SIER
);
637 SYSFS_SPRSETUP(siar
, SPRN_PA6T_SIAR
);
638 SYSFS_SPRSETUP(tsr0
, SPRN_PA6T_TSR0
);
639 SYSFS_SPRSETUP(tsr1
, SPRN_PA6T_TSR1
);
640 SYSFS_SPRSETUP(tsr2
, SPRN_PA6T_TSR2
);
641 SYSFS_SPRSETUP(tsr3
, SPRN_PA6T_TSR3
);
642 #endif /* CONFIG_DEBUG_KERNEL */
643 #endif /* HAS_PPC_PMC_PA6T */
645 #ifdef HAS_PPC_PMC_IBM
646 static struct device_attribute ibm_common_attrs
[] = {
647 __ATTR(mmcr0
, 0600, show_mmcr0
, store_mmcr0
),
648 __ATTR(mmcr1
, 0600, show_mmcr1
, store_mmcr1
),
650 #endif /* HAS_PPC_PMC_G4 */
652 #ifdef HAS_PPC_PMC_G4
653 static struct device_attribute g4_common_attrs
[] = {
654 __ATTR(mmcr0
, 0600, show_mmcr0
, store_mmcr0
),
655 __ATTR(mmcr1
, 0600, show_mmcr1
, store_mmcr1
),
656 __ATTR(mmcr2
, 0600, show_mmcr2
, store_mmcr2
),
658 #endif /* HAS_PPC_PMC_G4 */
660 static struct device_attribute classic_pmc_attrs
[] = {
661 __ATTR(pmc1
, 0600, show_pmc1
, store_pmc1
),
662 __ATTR(pmc2
, 0600, show_pmc2
, store_pmc2
),
663 __ATTR(pmc3
, 0600, show_pmc3
, store_pmc3
),
664 __ATTR(pmc4
, 0600, show_pmc4
, store_pmc4
),
665 __ATTR(pmc5
, 0600, show_pmc5
, store_pmc5
),
666 __ATTR(pmc6
, 0600, show_pmc6
, store_pmc6
),
668 __ATTR(pmc7
, 0600, show_pmc7
, store_pmc7
),
669 __ATTR(pmc8
, 0600, show_pmc8
, store_pmc8
),
673 #ifdef HAS_PPC_PMC_PA6T
674 static struct device_attribute pa6t_attrs
[] = {
675 __ATTR(mmcr0
, 0600, show_mmcr0
, store_mmcr0
),
676 __ATTR(mmcr1
, 0600, show_mmcr1
, store_mmcr1
),
677 __ATTR(pmc0
, 0600, show_pa6t_pmc0
, store_pa6t_pmc0
),
678 __ATTR(pmc1
, 0600, show_pa6t_pmc1
, store_pa6t_pmc1
),
679 __ATTR(pmc2
, 0600, show_pa6t_pmc2
, store_pa6t_pmc2
),
680 __ATTR(pmc3
, 0600, show_pa6t_pmc3
, store_pa6t_pmc3
),
681 __ATTR(pmc4
, 0600, show_pa6t_pmc4
, store_pa6t_pmc4
),
682 __ATTR(pmc5
, 0600, show_pa6t_pmc5
, store_pa6t_pmc5
),
683 #ifdef CONFIG_DEBUG_KERNEL
684 __ATTR(hid0
, 0600, show_hid0
, store_hid0
),
685 __ATTR(hid1
, 0600, show_hid1
, store_hid1
),
686 __ATTR(hid4
, 0600, show_hid4
, store_hid4
),
687 __ATTR(hid5
, 0600, show_hid5
, store_hid5
),
688 __ATTR(ima0
, 0600, show_ima0
, store_ima0
),
689 __ATTR(ima1
, 0600, show_ima1
, store_ima1
),
690 __ATTR(ima2
, 0600, show_ima2
, store_ima2
),
691 __ATTR(ima3
, 0600, show_ima3
, store_ima3
),
692 __ATTR(ima4
, 0600, show_ima4
, store_ima4
),
693 __ATTR(ima5
, 0600, show_ima5
, store_ima5
),
694 __ATTR(ima6
, 0600, show_ima6
, store_ima6
),
695 __ATTR(ima7
, 0600, show_ima7
, store_ima7
),
696 __ATTR(ima8
, 0600, show_ima8
, store_ima8
),
697 __ATTR(ima9
, 0600, show_ima9
, store_ima9
),
698 __ATTR(imaat
, 0600, show_imaat
, store_imaat
),
699 __ATTR(btcr
, 0600, show_btcr
, store_btcr
),
700 __ATTR(pccr
, 0600, show_pccr
, store_pccr
),
701 __ATTR(rpccr
, 0600, show_rpccr
, store_rpccr
),
702 __ATTR(der
, 0600, show_der
, store_der
),
703 __ATTR(mer
, 0600, show_mer
, store_mer
),
704 __ATTR(ber
, 0600, show_ber
, store_ber
),
705 __ATTR(ier
, 0600, show_ier
, store_ier
),
706 __ATTR(sier
, 0600, show_sier
, store_sier
),
707 __ATTR(siar
, 0600, show_siar
, store_siar
),
708 __ATTR(tsr0
, 0600, show_tsr0
, store_tsr0
),
709 __ATTR(tsr1
, 0600, show_tsr1
, store_tsr1
),
710 __ATTR(tsr2
, 0600, show_tsr2
, store_tsr2
),
711 __ATTR(tsr3
, 0600, show_tsr3
, store_tsr3
),
712 #endif /* CONFIG_DEBUG_KERNEL */
714 #endif /* HAS_PPC_PMC_PA6T */
715 #endif /* HAS_PPC_PMC_CLASSIC */
717 static int register_cpu_online(unsigned int cpu
)
719 struct cpu
*c
= &per_cpu(cpu_devices
, cpu
);
720 struct device
*s
= &c
->dev
;
721 struct device_attribute
*attrs
, *pmc_attrs
;
724 /* For cpus present at boot a reference was already grabbed in register_cpu() */
726 s
->of_node
= of_get_cpu_node(cpu
, NULL
);
729 if (cpu_has_feature(CPU_FTR_SMT
))
730 device_create_file(s
, &dev_attr_smt_snooze_delay
);
734 switch (cur_cpu_spec
->pmc_type
) {
735 #ifdef HAS_PPC_PMC_IBM
737 attrs
= ibm_common_attrs
;
738 nattrs
= sizeof(ibm_common_attrs
) / sizeof(struct device_attribute
);
739 pmc_attrs
= classic_pmc_attrs
;
741 #endif /* HAS_PPC_PMC_IBM */
742 #ifdef HAS_PPC_PMC_G4
744 attrs
= g4_common_attrs
;
745 nattrs
= sizeof(g4_common_attrs
) / sizeof(struct device_attribute
);
746 pmc_attrs
= classic_pmc_attrs
;
748 #endif /* HAS_PPC_PMC_G4 */
749 #ifdef HAS_PPC_PMC_PA6T
751 /* PA Semi starts counting at PMC0 */
753 nattrs
= sizeof(pa6t_attrs
) / sizeof(struct device_attribute
);
756 #endif /* HAS_PPC_PMC_PA6T */
763 for (i
= 0; i
< nattrs
; i
++)
764 device_create_file(s
, &attrs
[i
]);
767 for (i
= 0; i
< cur_cpu_spec
->num_pmcs
; i
++)
768 device_create_file(s
, &pmc_attrs
[i
]);
771 if (cpu_has_feature(CPU_FTR_MMCRA
))
772 device_create_file(s
, &dev_attr_mmcra
);
774 if (cpu_has_feature(CPU_FTR_PURR
)) {
775 if (!firmware_has_feature(FW_FEATURE_LPAR
))
776 add_write_permission_dev_attr(&dev_attr_purr
);
777 device_create_file(s
, &dev_attr_purr
);
780 if (cpu_has_feature(CPU_FTR_SPURR
))
781 device_create_file(s
, &dev_attr_spurr
);
783 if (cpu_has_feature(CPU_FTR_DSCR
))
784 device_create_file(s
, &dev_attr_dscr
);
786 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2
))
787 device_create_file(s
, &dev_attr_pir
);
789 if (cpu_has_feature(CPU_FTR_ARCH_206
) &&
790 !firmware_has_feature(FW_FEATURE_LPAR
))
791 device_create_file(s
, &dev_attr_tscr
);
792 #endif /* CONFIG_PPC64 */
794 #ifdef CONFIG_PPC_FSL_BOOK3E
795 if (PVR_VER(cur_cpu_spec
->pvr_value
) == PVR_VER_E6500
) {
796 device_create_file(s
, &dev_attr_pw20_state
);
797 device_create_file(s
, &dev_attr_pw20_wait_time
);
799 device_create_file(s
, &dev_attr_altivec_idle
);
800 device_create_file(s
, &dev_attr_altivec_idle_wait_time
);
803 cacheinfo_cpu_online(cpu
);
807 #ifdef CONFIG_HOTPLUG_CPU
808 static int unregister_cpu_online(unsigned int cpu
)
810 struct cpu
*c
= &per_cpu(cpu_devices
, cpu
);
811 struct device
*s
= &c
->dev
;
812 struct device_attribute
*attrs
, *pmc_attrs
;
815 BUG_ON(!c
->hotpluggable
);
818 if (cpu_has_feature(CPU_FTR_SMT
))
819 device_remove_file(s
, &dev_attr_smt_snooze_delay
);
823 switch (cur_cpu_spec
->pmc_type
) {
824 #ifdef HAS_PPC_PMC_IBM
826 attrs
= ibm_common_attrs
;
827 nattrs
= sizeof(ibm_common_attrs
) / sizeof(struct device_attribute
);
828 pmc_attrs
= classic_pmc_attrs
;
830 #endif /* HAS_PPC_PMC_IBM */
831 #ifdef HAS_PPC_PMC_G4
833 attrs
= g4_common_attrs
;
834 nattrs
= sizeof(g4_common_attrs
) / sizeof(struct device_attribute
);
835 pmc_attrs
= classic_pmc_attrs
;
837 #endif /* HAS_PPC_PMC_G4 */
838 #ifdef HAS_PPC_PMC_PA6T
840 /* PA Semi starts counting at PMC0 */
842 nattrs
= sizeof(pa6t_attrs
) / sizeof(struct device_attribute
);
845 #endif /* HAS_PPC_PMC_PA6T */
852 for (i
= 0; i
< nattrs
; i
++)
853 device_remove_file(s
, &attrs
[i
]);
856 for (i
= 0; i
< cur_cpu_spec
->num_pmcs
; i
++)
857 device_remove_file(s
, &pmc_attrs
[i
]);
860 if (cpu_has_feature(CPU_FTR_MMCRA
))
861 device_remove_file(s
, &dev_attr_mmcra
);
863 if (cpu_has_feature(CPU_FTR_PURR
))
864 device_remove_file(s
, &dev_attr_purr
);
866 if (cpu_has_feature(CPU_FTR_SPURR
))
867 device_remove_file(s
, &dev_attr_spurr
);
869 if (cpu_has_feature(CPU_FTR_DSCR
))
870 device_remove_file(s
, &dev_attr_dscr
);
872 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2
))
873 device_remove_file(s
, &dev_attr_pir
);
875 if (cpu_has_feature(CPU_FTR_ARCH_206
) &&
876 !firmware_has_feature(FW_FEATURE_LPAR
))
877 device_remove_file(s
, &dev_attr_tscr
);
878 #endif /* CONFIG_PPC64 */
880 #ifdef CONFIG_PPC_FSL_BOOK3E
881 if (PVR_VER(cur_cpu_spec
->pvr_value
) == PVR_VER_E6500
) {
882 device_remove_file(s
, &dev_attr_pw20_state
);
883 device_remove_file(s
, &dev_attr_pw20_wait_time
);
885 device_remove_file(s
, &dev_attr_altivec_idle
);
886 device_remove_file(s
, &dev_attr_altivec_idle_wait_time
);
889 cacheinfo_cpu_offline(cpu
);
890 of_node_put(s
->of_node
);
894 #else /* !CONFIG_HOTPLUG_CPU */
895 #define unregister_cpu_online NULL
898 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
899 ssize_t
arch_cpu_probe(const char *buf
, size_t count
)
901 if (ppc_md
.cpu_probe
)
902 return ppc_md
.cpu_probe(buf
, count
);
907 ssize_t
arch_cpu_release(const char *buf
, size_t count
)
909 if (ppc_md
.cpu_release
)
910 return ppc_md
.cpu_release(buf
, count
);
914 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
916 static DEFINE_MUTEX(cpu_mutex
);
918 int cpu_add_dev_attr(struct device_attribute
*attr
)
922 mutex_lock(&cpu_mutex
);
924 for_each_possible_cpu(cpu
) {
925 device_create_file(get_cpu_device(cpu
), attr
);
928 mutex_unlock(&cpu_mutex
);
931 EXPORT_SYMBOL_GPL(cpu_add_dev_attr
);
933 int cpu_add_dev_attr_group(struct attribute_group
*attrs
)
939 mutex_lock(&cpu_mutex
);
941 for_each_possible_cpu(cpu
) {
942 dev
= get_cpu_device(cpu
);
943 ret
= sysfs_create_group(&dev
->kobj
, attrs
);
947 mutex_unlock(&cpu_mutex
);
950 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group
);
953 void cpu_remove_dev_attr(struct device_attribute
*attr
)
957 mutex_lock(&cpu_mutex
);
959 for_each_possible_cpu(cpu
) {
960 device_remove_file(get_cpu_device(cpu
), attr
);
963 mutex_unlock(&cpu_mutex
);
965 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr
);
967 void cpu_remove_dev_attr_group(struct attribute_group
*attrs
)
972 mutex_lock(&cpu_mutex
);
974 for_each_possible_cpu(cpu
) {
975 dev
= get_cpu_device(cpu
);
976 sysfs_remove_group(&dev
->kobj
, attrs
);
979 mutex_unlock(&cpu_mutex
);
981 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group
);
987 static void register_nodes(void)
991 for (i
= 0; i
< MAX_NUMNODES
; i
++)
992 register_one_node(i
);
995 int sysfs_add_device_to_node(struct device
*dev
, int nid
)
997 struct node
*node
= node_devices
[nid
];
998 return sysfs_create_link(&node
->dev
.kobj
, &dev
->kobj
,
999 kobject_name(&dev
->kobj
));
1001 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node
);
1003 void sysfs_remove_device_from_node(struct device
*dev
, int nid
)
1005 struct node
*node
= node_devices
[nid
];
1006 sysfs_remove_link(&node
->dev
.kobj
, kobject_name(&dev
->kobj
));
1008 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node
);
1011 static void register_nodes(void)
1018 /* Only valid if CPU is present. */
1019 static ssize_t
show_physical_id(struct device
*dev
,
1020 struct device_attribute
*attr
, char *buf
)
1022 struct cpu
*cpu
= container_of(dev
, struct cpu
, dev
);
1024 return sprintf(buf
, "%d\n", get_hard_smp_processor_id(cpu
->dev
.id
));
1026 static DEVICE_ATTR(physical_id
, 0444, show_physical_id
, NULL
);
1028 static int __init
topology_init(void)
1034 for_each_possible_cpu(cpu
) {
1035 struct cpu
*c
= &per_cpu(cpu_devices
, cpu
);
1038 * For now, we just see if the system supports making
1039 * the RTAS calls for CPU hotplug. But, there may be a
1040 * more comprehensive way to do this for an individual
1041 * CPU. For instance, the boot cpu might never be valid
1045 c
->hotpluggable
= 1;
1047 if (cpu_online(cpu
) || c
->hotpluggable
) {
1048 register_cpu(c
, cpu
);
1050 device_create_file(&c
->dev
, &dev_attr_physical_id
);
1053 r
= cpuhp_setup_state(CPUHP_AP_ONLINE_DYN
, "powerpc/topology:online",
1054 register_cpu_online
, unregister_cpu_online
);
1057 sysfs_create_dscr_default();
1058 #endif /* CONFIG_PPC64 */
1062 subsys_initcall(topology_init
);