2 * Transactional memory support routines to reclaim and recheckpoint
3 * transactional process state.
5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
8 #include <asm/asm-offsets.h>
9 #include <asm/ppc_asm.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/ptrace.h>
16 /* See fpu.S, this is borrowed from there */
17 #define __SAVE_32FPRS_VSRS(n,c,base) \
20 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
21 SAVE_32FPRS(n,base); \
23 2: SAVE_32VSRS(n,c,base); \
25 #define __REST_32FPRS_VSRS(n,c,base) \
28 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
29 REST_32FPRS(n,base); \
31 2: REST_32VSRS(n,c,base); \
34 #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
35 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
37 #define SAVE_32FPRS_VSRS(n,c,base) \
38 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
39 #define REST_32FPRS_VSRS(n,c,base) \
40 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42 /* Stack frame offsets for local variables. */
43 #define TM_FRAME_L0 TM_FRAME_SIZE-16
44 #define TM_FRAME_L1 TM_FRAME_SIZE-8
47 /* In order to access the TM SPRs, TM must be enabled. So, do so: */
60 std r0, THREAD_TM_TFHAR(r3)
62 std r0, THREAD_TM_TEXASR(r3)
64 std r0, THREAD_TM_TFIAR(r3)
67 _GLOBAL(tm_restore_sprs)
68 ld r0, THREAD_TM_TFHAR(r3)
70 ld r0, THREAD_TM_TEXASR(r3)
72 ld r0, THREAD_TM_TFIAR(r3)
76 /* Passed an 8-bit failure cause as first argument. */
81 /* void tm_reclaim(struct thread_struct *thread,
82 * unsigned long orig_msr,
85 * - Performs a full reclaim. This destroys outstanding
86 * transactions and updates thread->regs.tm_ckpt_* with the
87 * original checkpointed state. Note that thread->regs is
89 * - FP regs are written back to thread->transact_fpr before
90 * reclaiming. These are the transactional (current) versions.
92 * Purpose is to both abort transactions of, and preserve the state of,
93 * a transactions at a context switch. We preserve/restore both sets of process
94 * state to restore them when the thread's scheduled again. We continue in
95 * userland as though nothing happened, but when the transaction is resumed
96 * they will abort back to the checkpointed state we save out here.
98 * Call with IRQs off, stacks get all out of sync for some periods in here!
106 stdu r1, -TM_FRAME_SIZE(r1)
108 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
110 std r3, STK_PARAM(R3)(r1)
111 std r4, STK_PARAM(R4)(r1)
114 /* We need to setup MSR for VSX register save instructions. */
119 ori r16, r16, MSR_EE /* IRQs hard off */
121 oris r15, r15, MSR_VEC@h
124 oris r15,r15, MSR_VSX@h
125 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
128 std r14, TM_FRAME_L0(r1)
130 /* Do sanity check on MSR to make sure we are suspended */
131 li r7, (MSR_TS_S)@higher
135 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
137 /* Stash the stack pointer away for use after reclaim */
140 /* Clear MSR RI since we are about to change r1, EE is already off. */
146 * At this point we can't take an SLB miss since we have MSR_RI
147 * off. Load only to/from the stack/paca which are in SLB bolted regions
148 * until we turn MSR RI back on.
150 * The moment we treclaim, ALL of our GPRs will switch
151 * to user register state. (FPRs, CCR etc. also!)
152 * Use an sprg and a tm_scratch in the PACA to shuffle.
154 TRECLAIM(R5) /* Cause in r5 */
156 /* ******************** GPRs ******************** */
157 /* Stash the checkpointed r13 away in the scratch SPR and get the real
163 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
166 std r1, PACATMSCRATCH(r13)
169 /* Store the PPR in r11 and reset to decent value */
170 std r11, GPR11(r1) /* Temporary stash */
172 /* Reset MSR RI so we can take SLB faults again */
179 /* Now get some more GPRS free */
180 std r7, GPR7(r1) /* Temporary stash */
181 std r12, GPR12(r1) /* '' '' '' */
182 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
184 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
186 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
188 /* Make r7 look like an exception frame so that we
189 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
191 subi r7, r7, STACK_FRAME_OVERHEAD
193 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
194 SAVE_GPR(0, r7) /* user r0 */
195 SAVE_GPR(2, r7) /* user r2 */
196 SAVE_4GPRS(3, r7) /* user r3-r6 */
197 SAVE_GPR(8, r7) /* user r8 */
198 SAVE_GPR(9, r7) /* user r9 */
199 SAVE_GPR(10, r7) /* user r10 */
200 ld r3, PACATMSCRATCH(r13) /* user r1 */
201 ld r4, GPR7(r1) /* user r7 */
202 ld r5, GPR11(r1) /* user r11 */
203 ld r6, GPR12(r1) /* user r12 */
204 GET_SCRATCH0(8) /* user r13 */
211 SAVE_NVGPRS(r7) /* user r14-r31 */
213 /* ******************** NIP ******************** */
215 std r3, _NIP(r7) /* Returns to failhandler */
216 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
217 * but is used in signal return to 'wind back' to the abort handler.
220 /* ******************** CR,LR,CCR,MSR ********** */
232 /* ******************** TAR, DSCR ********** */
236 std r3, THREAD_TM_TAR(r12)
237 std r4, THREAD_TM_DSCR(r12)
239 /* MSR and flags: We don't change CRs, and we don't need to alter
244 /* ******************** FPR/VR/VSRs ************
245 * After reclaiming, capture the checkpointed FPRs/VRs /if used/.
247 * (If VSX used, FP and VMX are implied. Or, we don't need to look
248 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
250 * We're passed the thread's MSR as the second parameter
252 * We enabled VEC/FP/VSX in the msr above, so we can execute these
255 ld r4, STK_PARAM(R4)(r1) /* Second parameter, MSR * */
257 andis. r0, r4, MSR_VEC@h
260 addi r7, r3, THREAD_CKVRSTATE
261 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
266 mfspr r0, SPRN_VRSAVE
267 std r0, THREAD_CKVRSAVE(r3)
272 addi r7, r3, THREAD_CKFPSTATE
273 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
276 stfd fr0,FPSTATE_FPSCR(r7)
280 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
281 * been updated by the treclaim, to explain to userland the failure
284 mfspr r0, SPRN_TEXASR
287 std r0, THREAD_TM_TEXASR(r12)
288 std r3, THREAD_TM_TFHAR(r12)
289 std r4, THREAD_TM_TFIAR(r12)
291 /* AMR is checkpointed too, but is unsupported by Linux. */
293 /* Restore original MSR/IRQ state & clear TM mode */
294 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
297 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
302 addi r1, r1, TM_FRAME_SIZE
309 /* Load CPU's default DSCR */
310 ld r0, PACA_DSCR_DEFAULT(r13)
316 /* void tm_recheckpoint(struct thread_struct *thread,
317 * unsigned long orig_msr)
318 * - Restore the checkpointed register state saved by tm_reclaim
319 * when we switch_to a process.
321 * Call with IRQs off, stacks get all out of sync for
322 * some periods in here!
324 _GLOBAL(__tm_recheckpoint)
330 stdu r1, -TM_FRAME_SIZE(r1)
332 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
333 * This is used for backing up the NVGPRs:
337 /* Load complete register state from ts_ckpt* registers */
339 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
341 /* Make r7 look like an exception frame so that we
342 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
344 subi r7, r7, STACK_FRAME_OVERHEAD
347 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
349 /* Enable FP/vec in MSR if necessary! */
353 beq restore_gprs /* if neither, skip both */
357 oris r5, r5, MSR_VSX@h
358 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
360 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
363 #ifdef CONFIG_ALTIVEC
365 * FP and VEC registers: These are recheckpointed from
366 * thread.ckfp_state and thread.ckvr_state respectively. The
367 * thread.fp_state[] version holds the 'live' (transactional)
368 * and will be loaded subsequently by any FPUnavailable trap.
370 andis. r0, r4, MSR_VEC@h
373 addi r8, r3, THREAD_CKVRSTATE
377 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
379 ld r5, THREAD_CKVRSAVE(r3)
380 mtspr SPRN_VRSAVE, r5
386 addi r8, r3, THREAD_CKFPSTATE
387 lfd fr0, FPSTATE_FPSCR(r8)
389 REST_32FPRS_VSRS(0, R4, R8)
392 mtmsr r6 /* FP/Vec off again! */
396 /* ******************** CR,LR,CCR,MSR ********** */
405 /* ******************** TAR ******************** */
406 ld r4, THREAD_TM_TAR(r3)
409 /* Load up the PPR and DSCR in GPRs only at this stage */
410 ld r5, THREAD_TM_DSCR(r3)
411 ld r6, THREAD_TM_PPR(r3)
413 REST_GPR(0, r7) /* GPR0 */
414 REST_2GPRS(2, r7) /* GPR2-3 */
415 REST_GPR(4, r7) /* GPR4 */
416 REST_4GPRS(8, r7) /* GPR8-11 */
417 REST_2GPRS(12, r7) /* GPR12-13 */
419 REST_NVGPRS(r7) /* GPR14-31 */
421 /* Load up PPR and DSCR here so we don't run with user values for long
426 /* Do final sanity check on TEXASR to make sure FS is set. Do this
427 * here before we load up the userspace r1 so any bugs we hit will get
429 mfspr r5, SPRN_TEXASR
434 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
436 /* Do final sanity check on MSR to make sure we are not transactional
440 li r5, (MSR_TS_MASK)@higher
444 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
453 * Store r1 and r5 on the stack so that we can access them
454 * after we clear MSR RI.
464 /* Clear MSR RI since we are about to change r1. EE is already off */
470 * At this point we can't take an SLB miss since we have MSR_RI
471 * off. Load only to/from the stack/paca which are in SLB bolted regions
472 * until we turn MSR RI back on.
479 /* Commit register state as checkpointed state: */
484 /* Our transactional state has now changed.
486 * Now just get out of here. Transactional (current) state will be
487 * updated once restore is called on the return path in the _switch-ed
494 /* R1 is restored, so we are recoverable again. EE is still off */
500 addi r1, r1, TM_FRAME_SIZE
507 /* Load CPU's default DSCR */
508 ld r0, PACA_DSCR_DEFAULT(r13)
513 /* ****************************************************************** */