2 * Transactional memory support routines to reclaim and recheckpoint
3 * transactional process state.
5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
8 #include <asm/asm-offsets.h>
9 #include <asm/ppc_asm.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/ptrace.h>
16 /* See fpu.S, this is borrowed from there */
17 #define __SAVE_32FPRS_VSRS(n,c,base) \
20 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
21 SAVE_32FPRS(n,base); \
23 2: SAVE_32VSRS(n,c,base); \
25 #define __REST_32FPRS_VSRS(n,c,base) \
28 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
29 REST_32FPRS(n,base); \
31 2: REST_32VSRS(n,c,base); \
34 #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
35 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
37 #define SAVE_32FPRS_VSRS(n,c,base) \
38 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
39 #define REST_32FPRS_VSRS(n,c,base) \
40 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42 /* Stack frame offsets for local variables. */
43 #define TM_FRAME_L0 TM_FRAME_SIZE-16
44 #define TM_FRAME_L1 TM_FRAME_SIZE-8
47 /* In order to access the TM SPRs, TM must be enabled. So, do so: */
60 std r0, THREAD_TM_TFHAR(r3)
62 std r0, THREAD_TM_TEXASR(r3)
64 std r0, THREAD_TM_TFIAR(r3)
67 _GLOBAL(tm_restore_sprs)
68 ld r0, THREAD_TM_TFHAR(r3)
70 ld r0, THREAD_TM_TEXASR(r3)
72 ld r0, THREAD_TM_TFIAR(r3)
76 /* Passed an 8-bit failure cause as first argument. */
81 /* void tm_reclaim(struct thread_struct *thread,
82 * unsigned long orig_msr,
85 * - Performs a full reclaim. This destroys outstanding
86 * transactions and updates thread->regs.tm_ckpt_* with the
87 * original checkpointed state. Note that thread->regs is
89 * - FP regs are written back to thread->transact_fpr before
90 * reclaiming. These are the transactional (current) versions.
92 * Purpose is to both abort transactions of, and preserve the state of,
93 * a transactions at a context switch. We preserve/restore both sets of process
94 * state to restore them when the thread's scheduled again. We continue in
95 * userland as though nothing happened, but when the transaction is resumed
96 * they will abort back to the checkpointed state we save out here.
98 * Call with IRQs off, stacks get all out of sync for some periods in here!
106 stdu r1, -TM_FRAME_SIZE(r1)
108 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
110 std r3, STK_PARAM(R3)(r1)
113 /* We need to setup MSR for VSX register save instructions. */
118 ori r16, r16, MSR_EE /* IRQs hard off */
120 oris r15, r15, MSR_VEC@h
123 oris r15,r15, MSR_VSX@h
124 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
127 std r14, TM_FRAME_L0(r1)
129 /* Stash the stack pointer away for use after reclaim */
132 /* ******************** FPR/VR/VSRs ************
133 * Before reclaiming, capture the current/transactional FPR/VR
134 * versions /if used/.
136 * (If VSX used, FP and VMX are implied. Or, we don't need to look
137 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
139 * We're passed the thread's MSR as parameter 2.
141 * We enabled VEC/FP/VSX in the msr above, so we can execute these
144 andis. r0, r4, MSR_VEC@h
147 addi r7, r3, THREAD_TRANSACT_VRSTATE
148 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
153 mfspr r0, SPRN_VRSAVE
154 std r0, THREAD_TRANSACT_VRSAVE(r3)
159 addi r7, r3, THREAD_TRANSACT_FPSTATE
160 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
163 stfd fr0,FPSTATE_FPSCR(r7)
166 /* Do sanity check on MSR to make sure we are suspended */
167 li r7, (MSR_TS_S)@higher
171 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
173 /* Clear MSR RI since we are about to change r1, EE is already off. */
179 * At this point we can't take an SLB miss since we have MSR_RI
180 * off. Load only to/from the stack/paca which are in SLB bolted regions
181 * until we turn MSR RI back on.
183 * The moment we treclaim, ALL of our GPRs will switch
184 * to user register state. (FPRs, CCR etc. also!)
185 * Use an sprg and a tm_scratch in the PACA to shuffle.
187 TRECLAIM(R5) /* Cause in r5 */
189 /* ******************** GPRs ******************** */
190 /* Stash the checkpointed r13 away in the scratch SPR and get the real
196 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
199 std r1, PACATMSCRATCH(r13)
202 /* Store the PPR in r11 and reset to decent value */
203 std r11, GPR11(r1) /* Temporary stash */
205 /* Reset MSR RI so we can take SLB faults again */
212 /* Now get some more GPRS free */
213 std r7, GPR7(r1) /* Temporary stash */
214 std r12, GPR12(r1) /* '' '' '' */
215 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
217 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
219 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
221 /* Make r7 look like an exception frame so that we
222 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
224 subi r7, r7, STACK_FRAME_OVERHEAD
226 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
227 SAVE_GPR(0, r7) /* user r0 */
228 SAVE_GPR(2, r7) /* user r2 */
229 SAVE_4GPRS(3, r7) /* user r3-r6 */
230 SAVE_GPR(8, r7) /* user r8 */
231 SAVE_GPR(9, r7) /* user r9 */
232 SAVE_GPR(10, r7) /* user r10 */
233 ld r3, PACATMSCRATCH(r13) /* user r1 */
234 ld r4, GPR7(r1) /* user r7 */
235 ld r5, GPR11(r1) /* user r11 */
236 ld r6, GPR12(r1) /* user r12 */
237 GET_SCRATCH0(8) /* user r13 */
244 SAVE_NVGPRS(r7) /* user r14-r31 */
246 /* ******************** NIP ******************** */
248 std r3, _NIP(r7) /* Returns to failhandler */
249 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
250 * but is used in signal return to 'wind back' to the abort handler.
253 /* ******************** CR,LR,CCR,MSR ********** */
265 /* ******************** TAR, DSCR ********** */
269 std r3, THREAD_TM_TAR(r12)
270 std r4, THREAD_TM_DSCR(r12)
272 /* MSR and flags: We don't change CRs, and we don't need to alter
276 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
277 * been updated by the treclaim, to explain to userland the failure
280 mfspr r0, SPRN_TEXASR
283 std r0, THREAD_TM_TEXASR(r12)
284 std r3, THREAD_TM_TFHAR(r12)
285 std r4, THREAD_TM_TFIAR(r12)
287 /* AMR is checkpointed too, but is unsupported by Linux. */
289 /* Restore original MSR/IRQ state & clear TM mode */
290 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
292 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
297 addi r1, r1, TM_FRAME_SIZE
304 /* Load CPU's default DSCR */
305 ld r0, PACA_DSCR_DEFAULT(r13)
311 /* void tm_recheckpoint(struct thread_struct *thread,
312 * unsigned long orig_msr)
313 * - Restore the checkpointed register state saved by tm_reclaim
314 * when we switch_to a process.
316 * Call with IRQs off, stacks get all out of sync for
317 * some periods in here!
319 _GLOBAL(__tm_recheckpoint)
325 stdu r1, -TM_FRAME_SIZE(r1)
327 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
328 * This is used for backing up the NVGPRs:
332 /* Load complete register state from ts_ckpt* registers */
334 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
336 /* Make r7 look like an exception frame so that we
337 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
339 subi r7, r7, STACK_FRAME_OVERHEAD
344 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
346 /* Enable FP/vec in MSR if necessary! */
350 beq restore_gprs /* if neither, skip both */
354 oris r5, r5, MSR_VSX@h
355 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
357 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
360 #ifdef CONFIG_ALTIVEC
361 /* FP and VEC registers: These are recheckpointed from thread.fpr[]
362 * and thread.vr[] respectively. The thread.transact_fpr[] version
363 * is more modern, and will be loaded subsequently by any FPUnavailable
366 andis. r0, r4, MSR_VEC@h
369 addi r8, r3, THREAD_VRSTATE
373 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
375 ld r5, THREAD_VRSAVE(r3)
376 mtspr SPRN_VRSAVE, r5
382 addi r8, r3, THREAD_FPSTATE
383 lfd fr0, FPSTATE_FPSCR(r8)
385 REST_32FPRS_VSRS(0, R4, R8)
388 mtmsr r6 /* FP/Vec off again! */
392 /* ******************** CR,LR,CCR,MSR ********** */
401 /* ******************** TAR ******************** */
402 ld r4, THREAD_TM_TAR(r3)
405 /* Load up the PPR and DSCR in GPRs only at this stage */
406 ld r5, THREAD_TM_DSCR(r3)
407 ld r6, THREAD_TM_PPR(r3)
409 REST_GPR(0, r7) /* GPR0 */
410 REST_2GPRS(2, r7) /* GPR2-3 */
411 REST_GPR(4, r7) /* GPR4 */
412 REST_4GPRS(8, r7) /* GPR8-11 */
413 REST_2GPRS(12, r7) /* GPR12-13 */
415 REST_NVGPRS(r7) /* GPR14-31 */
417 /* Load up PPR and DSCR here so we don't run with user values for long
422 /* Do final sanity check on TEXASR to make sure FS is set. Do this
423 * here before we load up the userspace r1 so any bugs we hit will get
425 mfspr r5, SPRN_TEXASR
430 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
432 /* Do final sanity check on MSR to make sure we are not transactional
436 li r5, (MSR_TS_MASK)@higher
440 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
449 * Store r1 and r5 on the stack so that we can access them
450 * after we clear MSR RI.
460 /* Clear MSR RI since we are about to change r1. EE is already off */
466 * At this point we can't take an SLB miss since we have MSR_RI
467 * off. Load only to/from the stack/paca which are in SLB bolted regions
468 * until we turn MSR RI back on.
474 /* Commit register state as checkpointed state: */
479 /* Our transactional state has now changed.
481 * Now just get out of here. Transactional (current) state will be
482 * updated once restore is called on the return path in the _switch-ed
489 /* R1 is restored, so we are recoverable again. EE is still off */
495 addi r1, r1, TM_FRAME_SIZE
502 /* Load CPU's default DSCR */
503 ld r0, PACA_DSCR_DEFAULT(r13)
508 /* ****************************************************************** */