2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/extable.h>
29 #include <linux/module.h> /* print_modules */
30 #include <linux/prctl.h>
31 #include <linux/delay.h>
32 #include <linux/kprobes.h>
33 #include <linux/kexec.h>
34 #include <linux/backlight.h>
35 #include <linux/bug.h>
36 #include <linux/kdebug.h>
37 #include <linux/debugfs.h>
38 #include <linux/ratelimit.h>
39 #include <linux/context_tracking.h>
41 #include <asm/emulated_ops.h>
42 #include <asm/pgtable.h>
43 #include <asm/uaccess.h>
45 #include <asm/machdep.h>
49 #ifdef CONFIG_PMAC_BACKLIGHT
50 #include <asm/backlight.h>
53 #include <asm/firmware.h>
54 #include <asm/processor.h>
57 #include <asm/kexec.h>
58 #include <asm/ppc-opcode.h>
60 #include <asm/fadump.h>
61 #include <asm/switch_to.h>
63 #include <asm/debug.h>
64 #include <asm/asm-prototypes.h>
66 #include <sysdev/fsl_pci.h>
67 #include <asm/kprobes.h>
69 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
70 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
71 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
72 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
73 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
74 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
75 int (*__debugger_break_match
)(struct pt_regs
*regs
) __read_mostly
;
76 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
78 EXPORT_SYMBOL(__debugger
);
79 EXPORT_SYMBOL(__debugger_ipi
);
80 EXPORT_SYMBOL(__debugger_bpt
);
81 EXPORT_SYMBOL(__debugger_sstep
);
82 EXPORT_SYMBOL(__debugger_iabr_match
);
83 EXPORT_SYMBOL(__debugger_break_match
);
84 EXPORT_SYMBOL(__debugger_fault_handler
);
87 /* Transactional Memory trap debug */
89 #define TM_DEBUG(x...) printk(KERN_INFO x)
91 #define TM_DEBUG(x...) do { } while(0)
95 * Trap & Exception support
98 #ifdef CONFIG_PMAC_BACKLIGHT
99 static void pmac_backlight_unblank(void)
101 mutex_lock(&pmac_backlight_mutex
);
102 if (pmac_backlight
) {
103 struct backlight_properties
*props
;
105 props
= &pmac_backlight
->props
;
106 props
->brightness
= props
->max_brightness
;
107 props
->power
= FB_BLANK_UNBLANK
;
108 backlight_update_status(pmac_backlight
);
110 mutex_unlock(&pmac_backlight_mutex
);
113 static inline void pmac_backlight_unblank(void) { }
116 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
117 static int die_owner
= -1;
118 static unsigned int die_nest_count
;
119 static int die_counter
;
121 static unsigned long oops_begin(struct pt_regs
*regs
)
128 /* racy, but better than risking deadlock. */
129 raw_local_irq_save(flags
);
130 cpu
= smp_processor_id();
131 if (!arch_spin_trylock(&die_lock
)) {
132 if (cpu
== die_owner
)
133 /* nested oops. should stop eventually */;
135 arch_spin_lock(&die_lock
);
141 if (machine_is(powermac
))
142 pmac_backlight_unblank();
145 NOKPROBE_SYMBOL(oops_begin
);
147 static void oops_end(unsigned long flags
, struct pt_regs
*regs
,
151 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
155 if (!die_nest_count
) {
156 /* Nest count reaches zero, release the lock. */
158 arch_spin_unlock(&die_lock
);
160 raw_local_irq_restore(flags
);
162 crash_fadump(regs
, "die oops");
165 * A system reset (0x100) is a request to dump, so we always send
166 * it through the crashdump code.
168 if (kexec_should_crash(current
) || (TRAP(regs
) == 0x100)) {
172 * We aren't the primary crash CPU. We need to send it
173 * to a holding pattern to avoid it ending up in the panic
176 crash_kexec_secondary(regs
);
183 * While our oops output is serialised by a spinlock, output
184 * from panic() called below can race and corrupt it. If we
185 * know we are going to panic, delay for 1 second so we have a
186 * chance to get clean backtraces from all CPUs that are oopsing.
188 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
189 is_global_init(current
)) {
190 mdelay(MSEC_PER_SEC
);
194 panic("Fatal exception in interrupt");
196 panic("Fatal exception");
199 NOKPROBE_SYMBOL(oops_end
);
201 static int __die(const char *str
, struct pt_regs
*regs
, long err
)
203 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
204 #ifdef CONFIG_PREEMPT
208 printk("SMP NR_CPUS=%d ", NR_CPUS
);
210 if (debug_pagealloc_enabled())
211 printk("DEBUG_PAGEALLOC ");
215 printk("%s\n", ppc_md
.name
? ppc_md
.name
: "");
217 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
225 NOKPROBE_SYMBOL(__die
);
227 void die(const char *str
, struct pt_regs
*regs
, long err
)
234 flags
= oops_begin(regs
);
235 if (__die(str
, regs
, err
))
237 oops_end(flags
, regs
, err
);
240 void user_single_step_siginfo(struct task_struct
*tsk
,
241 struct pt_regs
*regs
, siginfo_t
*info
)
243 memset(info
, 0, sizeof(*info
));
244 info
->si_signo
= SIGTRAP
;
245 info
->si_code
= TRAP_TRACE
;
246 info
->si_addr
= (void __user
*)regs
->nip
;
249 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
252 const char fmt32
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
253 "at %08lx nip %08lx lr %08lx code %x\n";
254 const char fmt64
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
255 "at %016lx nip %016lx lr %016lx code %x\n";
257 if (!user_mode(regs
)) {
258 die("Exception in kernel mode", regs
, signr
);
262 if (show_unhandled_signals
&& unhandled_signal(current
, signr
)) {
263 printk_ratelimited(regs
->msr
& MSR_64BIT
? fmt64
: fmt32
,
264 current
->comm
, current
->pid
, signr
,
265 addr
, regs
->nip
, regs
->link
, code
);
268 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
271 current
->thread
.trap_nr
= code
;
272 memset(&info
, 0, sizeof(info
));
273 info
.si_signo
= signr
;
275 info
.si_addr
= (void __user
*) addr
;
276 force_sig_info(signr
, &info
, current
);
279 void system_reset_exception(struct pt_regs
*regs
)
281 /* See if any machine dependent calls */
282 if (ppc_md
.system_reset_exception
) {
283 if (ppc_md
.system_reset_exception(regs
))
287 die("System Reset", regs
, SIGABRT
);
289 /* Must die if the interrupt is not recoverable */
290 if (!(regs
->msr
& MSR_RI
))
291 panic("Unrecoverable System Reset");
293 /* What should we do here? We could issue a shutdown or hard reset. */
298 * This function is called in real mode. Strictly no printk's please.
300 * regs->nip and regs->msr contains srr0 and ssr1.
302 long machine_check_early(struct pt_regs
*regs
)
306 __this_cpu_inc(irq_stat
.mce_exceptions
);
308 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
310 if (cur_cpu_spec
&& cur_cpu_spec
->machine_check_early
)
311 handled
= cur_cpu_spec
->machine_check_early(regs
);
315 long hmi_exception_realmode(struct pt_regs
*regs
)
317 __this_cpu_inc(irq_stat
.hmi_exceptions
);
319 wait_for_subcore_guest_exit();
321 if (ppc_md
.hmi_exception_early
)
322 ppc_md
.hmi_exception_early(regs
);
324 wait_for_tb_resync();
332 * I/O accesses can cause machine checks on powermacs.
333 * Check if the NIP corresponds to the address of a sync
334 * instruction for which there is an entry in the exception
336 * Note that the 601 only takes a machine check on TEA
337 * (transfer error ack) signal assertion, and does not
338 * set any of the top 16 bits of SRR1.
341 static inline int check_io_access(struct pt_regs
*regs
)
344 unsigned long msr
= regs
->msr
;
345 const struct exception_table_entry
*entry
;
346 unsigned int *nip
= (unsigned int *)regs
->nip
;
348 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
349 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
351 * Check that it's a sync instruction, or somewhere
352 * in the twi; isync; nop sequence that inb/inw/inl uses.
353 * As the address is in the exception table
354 * we should be able to read the instr there.
355 * For the debug message, we look at the preceding
358 if (*nip
== PPC_INST_NOP
)
360 else if (*nip
== PPC_INST_ISYNC
)
362 if (*nip
== PPC_INST_SYNC
|| (*nip
>> 26) == OP_TRAP
) {
366 rb
= (*nip
>> 11) & 0x1f;
367 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
368 (*nip
& 0x100)? "OUT to": "IN from",
369 regs
->gpr
[rb
] - _IO_BASE
, nip
);
371 regs
->nip
= extable_fixup(entry
);
375 #endif /* CONFIG_PPC32 */
379 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
380 /* On 4xx, the reason for the machine check or program exception
382 #define get_reason(regs) ((regs)->dsisr)
383 #ifndef CONFIG_FSL_BOOKE
384 #define get_mc_reason(regs) ((regs)->dsisr)
386 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
388 #define REASON_FP ESR_FP
389 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
390 #define REASON_PRIVILEGED ESR_PPR
391 #define REASON_TRAP ESR_PTR
393 /* single-step stuff */
394 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
395 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
398 /* On non-4xx, the reason for the machine check or program
399 exception is in the MSR. */
400 #define get_reason(regs) ((regs)->msr)
401 #define get_mc_reason(regs) ((regs)->msr)
402 #define REASON_TM 0x200000
403 #define REASON_FP 0x100000
404 #define REASON_ILLEGAL 0x80000
405 #define REASON_PRIVILEGED 0x40000
406 #define REASON_TRAP 0x20000
408 #define single_stepping(regs) ((regs)->msr & MSR_SE)
409 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
412 #if defined(CONFIG_4xx)
413 int machine_check_4xx(struct pt_regs
*regs
)
415 unsigned long reason
= get_mc_reason(regs
);
417 if (reason
& ESR_IMCP
) {
418 printk("Instruction");
419 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
422 printk(" machine check in kernel mode.\n");
427 int machine_check_440A(struct pt_regs
*regs
)
429 unsigned long reason
= get_mc_reason(regs
);
431 printk("Machine check in kernel mode.\n");
432 if (reason
& ESR_IMCP
){
433 printk("Instruction Synchronous Machine Check exception\n");
434 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
437 u32 mcsr
= mfspr(SPRN_MCSR
);
439 printk("Instruction Read PLB Error\n");
441 printk("Data Read PLB Error\n");
443 printk("Data Write PLB Error\n");
444 if (mcsr
& MCSR_TLBP
)
445 printk("TLB Parity Error\n");
446 if (mcsr
& MCSR_ICP
){
447 flush_instruction_cache();
448 printk("I-Cache Parity Error\n");
450 if (mcsr
& MCSR_DCSP
)
451 printk("D-Cache Search Parity Error\n");
452 if (mcsr
& MCSR_DCFP
)
453 printk("D-Cache Flush Parity Error\n");
454 if (mcsr
& MCSR_IMPE
)
455 printk("Machine Check exception is imprecise\n");
458 mtspr(SPRN_MCSR
, mcsr
);
463 int machine_check_47x(struct pt_regs
*regs
)
465 unsigned long reason
= get_mc_reason(regs
);
468 printk(KERN_ERR
"Machine check in kernel mode.\n");
469 if (reason
& ESR_IMCP
) {
471 "Instruction Synchronous Machine Check exception\n");
472 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
475 mcsr
= mfspr(SPRN_MCSR
);
477 printk(KERN_ERR
"Instruction Read PLB Error\n");
479 printk(KERN_ERR
"Data Read PLB Error\n");
481 printk(KERN_ERR
"Data Write PLB Error\n");
482 if (mcsr
& MCSR_TLBP
)
483 printk(KERN_ERR
"TLB Parity Error\n");
484 if (mcsr
& MCSR_ICP
) {
485 flush_instruction_cache();
486 printk(KERN_ERR
"I-Cache Parity Error\n");
488 if (mcsr
& MCSR_DCSP
)
489 printk(KERN_ERR
"D-Cache Search Parity Error\n");
490 if (mcsr
& PPC47x_MCSR_GPR
)
491 printk(KERN_ERR
"GPR Parity Error\n");
492 if (mcsr
& PPC47x_MCSR_FPR
)
493 printk(KERN_ERR
"FPR Parity Error\n");
494 if (mcsr
& PPC47x_MCSR_IPR
)
495 printk(KERN_ERR
"Machine Check exception is imprecise\n");
498 mtspr(SPRN_MCSR
, mcsr
);
502 #elif defined(CONFIG_E500)
503 int machine_check_e500mc(struct pt_regs
*regs
)
505 unsigned long mcsr
= mfspr(SPRN_MCSR
);
506 unsigned long reason
= mcsr
;
509 if (reason
& MCSR_LD
) {
510 recoverable
= fsl_rio_mcheck_exception(regs
);
511 if (recoverable
== 1)
515 printk("Machine check in kernel mode.\n");
516 printk("Caused by (from MCSR=%lx): ", reason
);
518 if (reason
& MCSR_MCP
)
519 printk("Machine Check Signal\n");
521 if (reason
& MCSR_ICPERR
) {
522 printk("Instruction Cache Parity Error\n");
525 * This is recoverable by invalidating the i-cache.
527 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
528 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
532 * This will generally be accompanied by an instruction
533 * fetch error report -- only treat MCSR_IF as fatal
534 * if it wasn't due to an L1 parity error.
539 if (reason
& MCSR_DCPERR_MC
) {
540 printk("Data Cache Parity Error\n");
543 * In write shadow mode we auto-recover from the error, but it
544 * may still get logged and cause a machine check. We should
545 * only treat the non-write shadow case as non-recoverable.
547 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
551 if (reason
& MCSR_L2MMU_MHIT
) {
552 printk("Hit on multiple TLB entries\n");
556 if (reason
& MCSR_NMI
)
557 printk("Non-maskable interrupt\n");
559 if (reason
& MCSR_IF
) {
560 printk("Instruction Fetch Error Report\n");
564 if (reason
& MCSR_LD
) {
565 printk("Load Error Report\n");
569 if (reason
& MCSR_ST
) {
570 printk("Store Error Report\n");
574 if (reason
& MCSR_LDG
) {
575 printk("Guarded Load Error Report\n");
579 if (reason
& MCSR_TLBSYNC
)
580 printk("Simultaneous tlbsync operations\n");
582 if (reason
& MCSR_BSL2_ERR
) {
583 printk("Level 2 Cache Error\n");
587 if (reason
& MCSR_MAV
) {
590 addr
= mfspr(SPRN_MCAR
);
591 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
593 printk("Machine Check %s Address: %#llx\n",
594 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
598 mtspr(SPRN_MCSR
, mcsr
);
599 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
602 int machine_check_e500(struct pt_regs
*regs
)
604 unsigned long reason
= get_mc_reason(regs
);
606 if (reason
& MCSR_BUS_RBERR
) {
607 if (fsl_rio_mcheck_exception(regs
))
609 if (fsl_pci_mcheck_exception(regs
))
613 printk("Machine check in kernel mode.\n");
614 printk("Caused by (from MCSR=%lx): ", reason
);
616 if (reason
& MCSR_MCP
)
617 printk("Machine Check Signal\n");
618 if (reason
& MCSR_ICPERR
)
619 printk("Instruction Cache Parity Error\n");
620 if (reason
& MCSR_DCP_PERR
)
621 printk("Data Cache Push Parity Error\n");
622 if (reason
& MCSR_DCPERR
)
623 printk("Data Cache Parity Error\n");
624 if (reason
& MCSR_BUS_IAERR
)
625 printk("Bus - Instruction Address Error\n");
626 if (reason
& MCSR_BUS_RAERR
)
627 printk("Bus - Read Address Error\n");
628 if (reason
& MCSR_BUS_WAERR
)
629 printk("Bus - Write Address Error\n");
630 if (reason
& MCSR_BUS_IBERR
)
631 printk("Bus - Instruction Data Error\n");
632 if (reason
& MCSR_BUS_RBERR
)
633 printk("Bus - Read Data Bus Error\n");
634 if (reason
& MCSR_BUS_WBERR
)
635 printk("Bus - Write Data Bus Error\n");
636 if (reason
& MCSR_BUS_IPERR
)
637 printk("Bus - Instruction Parity Error\n");
638 if (reason
& MCSR_BUS_RPERR
)
639 printk("Bus - Read Parity Error\n");
644 int machine_check_generic(struct pt_regs
*regs
)
648 #elif defined(CONFIG_E200)
649 int machine_check_e200(struct pt_regs
*regs
)
651 unsigned long reason
= get_mc_reason(regs
);
653 printk("Machine check in kernel mode.\n");
654 printk("Caused by (from MCSR=%lx): ", reason
);
656 if (reason
& MCSR_MCP
)
657 printk("Machine Check Signal\n");
658 if (reason
& MCSR_CP_PERR
)
659 printk("Cache Push Parity Error\n");
660 if (reason
& MCSR_CPERR
)
661 printk("Cache Parity Error\n");
662 if (reason
& MCSR_EXCP_ERR
)
663 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
664 if (reason
& MCSR_BUS_IRERR
)
665 printk("Bus - Read Bus Error on instruction fetch\n");
666 if (reason
& MCSR_BUS_DRERR
)
667 printk("Bus - Read Bus Error on data load\n");
668 if (reason
& MCSR_BUS_WRERR
)
669 printk("Bus - Write Bus Error on buffered store or cache line push\n");
673 #elif defined(CONFIG_PPC_8xx)
674 int machine_check_8xx(struct pt_regs
*regs
)
676 unsigned long reason
= get_mc_reason(regs
);
678 pr_err("Machine check in kernel mode.\n");
679 pr_err("Caused by (from SRR1=%lx): ", reason
);
680 if (reason
& 0x40000000)
681 pr_err("Fetch error at address %lx\n", regs
->nip
);
683 pr_err("Data access error at address %lx\n", regs
->dar
);
686 /* the qspan pci read routines can cause machine checks -- Cort
688 * yuck !!! that totally needs to go away ! There are better ways
689 * to deal with that than having a wart in the mcheck handler.
692 bad_page_fault(regs
, regs
->dar
, SIGBUS
);
699 int machine_check_generic(struct pt_regs
*regs
)
701 unsigned long reason
= get_mc_reason(regs
);
703 printk("Machine check in kernel mode.\n");
704 printk("Caused by (from SRR1=%lx): ", reason
);
705 switch (reason
& 0x601F0000) {
707 printk("Machine check signal\n");
709 case 0: /* for 601 */
711 case 0x140000: /* 7450 MSS error and TEA */
712 printk("Transfer error ack signal\n");
715 printk("Data parity error signal\n");
718 printk("Address parity error signal\n");
721 printk("L1 Data Cache error\n");
724 printk("L1 Instruction Cache error\n");
727 printk("L2 data cache parity error\n");
730 printk("Unknown values in msr\n");
734 #endif /* everything else */
736 void machine_check_exception(struct pt_regs
*regs
)
738 enum ctx_state prev_state
= exception_enter();
741 __this_cpu_inc(irq_stat
.mce_exceptions
);
743 /* See if any machine dependent calls. In theory, we would want
744 * to call the CPU first, and call the ppc_md. one if the CPU
745 * one returns a positive number. However there is existing code
746 * that assumes the board gets a first chance, so let's keep it
747 * that way for now and fix things later. --BenH.
749 if (ppc_md
.machine_check_exception
)
750 recover
= ppc_md
.machine_check_exception(regs
);
751 else if (cur_cpu_spec
->machine_check
)
752 recover
= cur_cpu_spec
->machine_check(regs
);
757 if (debugger_fault_handler(regs
))
760 if (check_io_access(regs
))
763 die("Machine check", regs
, SIGBUS
);
765 /* Must die if the interrupt is not recoverable */
766 if (!(regs
->msr
& MSR_RI
))
767 panic("Unrecoverable Machine check");
770 exception_exit(prev_state
);
773 void SMIException(struct pt_regs
*regs
)
775 die("System Management Interrupt", regs
, SIGABRT
);
778 void handle_hmi_exception(struct pt_regs
*regs
)
780 struct pt_regs
*old_regs
;
782 old_regs
= set_irq_regs(regs
);
785 if (ppc_md
.handle_hmi_exception
)
786 ppc_md
.handle_hmi_exception(regs
);
789 set_irq_regs(old_regs
);
792 void unknown_exception(struct pt_regs
*regs
)
794 enum ctx_state prev_state
= exception_enter();
796 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
797 regs
->nip
, regs
->msr
, regs
->trap
);
799 _exception(SIGTRAP
, regs
, 0, 0);
801 exception_exit(prev_state
);
804 void instruction_breakpoint_exception(struct pt_regs
*regs
)
806 enum ctx_state prev_state
= exception_enter();
808 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
809 5, SIGTRAP
) == NOTIFY_STOP
)
811 if (debugger_iabr_match(regs
))
813 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
816 exception_exit(prev_state
);
819 void RunModeException(struct pt_regs
*regs
)
821 _exception(SIGTRAP
, regs
, 0, 0);
824 void single_step_exception(struct pt_regs
*regs
)
826 enum ctx_state prev_state
= exception_enter();
828 clear_single_step(regs
);
830 if (kprobe_post_handler(regs
))
833 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
834 5, SIGTRAP
) == NOTIFY_STOP
)
836 if (debugger_sstep(regs
))
839 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
842 exception_exit(prev_state
);
844 NOKPROBE_SYMBOL(single_step_exception
);
847 * After we have successfully emulated an instruction, we have to
848 * check if the instruction was being single-stepped, and if so,
849 * pretend we got a single-step exception. This was pointed out
850 * by Kumar Gala. -- paulus
852 static void emulate_single_step(struct pt_regs
*regs
)
854 if (single_stepping(regs
))
855 single_step_exception(regs
);
858 static inline int __parse_fpscr(unsigned long fpscr
)
862 /* Invalid operation */
863 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
867 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
871 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
875 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
879 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
885 static void parse_fpe(struct pt_regs
*regs
)
889 flush_fp_to_thread(current
);
891 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
893 _exception(SIGFPE
, regs
, code
, regs
->nip
);
897 * Illegal instruction emulation support. Originally written to
898 * provide the PVR to user applications using the mfspr rd, PVR.
899 * Return non-zero if we can't emulate, or -EFAULT if the associated
900 * memory access caused an access fault. Return zero on success.
902 * There are a couple of ways to do this, either "decode" the instruction
903 * or directly match lots of bits. In this case, matching lots of
904 * bits is faster and easier.
907 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
909 u8 rT
= (instword
>> 21) & 0x1f;
910 u8 rA
= (instword
>> 16) & 0x1f;
911 u8 NB_RB
= (instword
>> 11) & 0x1f;
916 /* Early out if we are an invalid form of lswx */
917 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
918 if ((rT
== rA
) || (rT
== NB_RB
))
921 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
923 switch (instword
& PPC_INST_STRING_MASK
) {
927 num_bytes
= regs
->xer
& 0x7f;
931 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
937 while (num_bytes
!= 0)
940 u32 shift
= 8 * (3 - (pos
& 0x3));
942 /* if process is 32-bit, clear upper 32 bits of EA */
943 if ((regs
->msr
& MSR_64BIT
) == 0)
946 switch ((instword
& PPC_INST_STRING_MASK
)) {
949 if (get_user(val
, (u8 __user
*)EA
))
951 /* first time updating this reg,
955 regs
->gpr
[rT
] |= val
<< shift
;
959 val
= regs
->gpr
[rT
] >> shift
;
960 if (put_user(val
, (u8 __user
*)EA
))
964 /* move EA to next address */
968 /* manage our position within the register */
979 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
984 ra
= (instword
>> 16) & 0x1f;
985 rs
= (instword
>> 21) & 0x1f;
988 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
989 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
990 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
996 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
998 u8 rT
= (instword
>> 21) & 0x1f;
999 u8 rA
= (instword
>> 16) & 0x1f;
1000 u8 rB
= (instword
>> 11) & 0x1f;
1001 u8 BC
= (instword
>> 6) & 0x1f;
1005 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
1006 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
1008 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
1013 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1014 static inline bool tm_abort_check(struct pt_regs
*regs
, int cause
)
1016 /* If we're emulating a load/store in an active transaction, we cannot
1017 * emulate it as the kernel operates in transaction suspended context.
1018 * We need to abort the transaction. This creates a persistent TM
1019 * abort so tell the user what caused it with a new code.
1021 if (MSR_TM_TRANSACTIONAL(regs
->msr
)) {
1029 static inline bool tm_abort_check(struct pt_regs
*regs
, int reason
)
1035 static int emulate_instruction(struct pt_regs
*regs
)
1040 if (!user_mode(regs
))
1042 CHECK_FULL_REGS(regs
);
1044 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
1047 /* Emulate the mfspr rD, PVR. */
1048 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
1049 PPC_WARN_EMULATED(mfpvr
, regs
);
1050 rd
= (instword
>> 21) & 0x1f;
1051 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
1055 /* Emulating the dcba insn is just a no-op. */
1056 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
1057 PPC_WARN_EMULATED(dcba
, regs
);
1061 /* Emulate the mcrxr insn. */
1062 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
1063 int shift
= (instword
>> 21) & 0x1c;
1064 unsigned long msk
= 0xf0000000UL
>> shift
;
1066 PPC_WARN_EMULATED(mcrxr
, regs
);
1067 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
1068 regs
->xer
&= ~0xf0000000UL
;
1072 /* Emulate load/store string insn. */
1073 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
1074 if (tm_abort_check(regs
,
1075 TM_CAUSE_EMULATE
| TM_CAUSE_PERSISTENT
))
1077 PPC_WARN_EMULATED(string
, regs
);
1078 return emulate_string_inst(regs
, instword
);
1081 /* Emulate the popcntb (Population Count Bytes) instruction. */
1082 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
1083 PPC_WARN_EMULATED(popcntb
, regs
);
1084 return emulate_popcntb_inst(regs
, instword
);
1087 /* Emulate isel (Integer Select) instruction */
1088 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
1089 PPC_WARN_EMULATED(isel
, regs
);
1090 return emulate_isel(regs
, instword
);
1093 /* Emulate sync instruction variants */
1094 if ((instword
& PPC_INST_SYNC_MASK
) == PPC_INST_SYNC
) {
1095 PPC_WARN_EMULATED(sync
, regs
);
1096 asm volatile("sync");
1101 /* Emulate the mfspr rD, DSCR. */
1102 if ((((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
) ==
1103 PPC_INST_MFSPR_DSCR_USER
) ||
1104 ((instword
& PPC_INST_MFSPR_DSCR_MASK
) ==
1105 PPC_INST_MFSPR_DSCR
)) &&
1106 cpu_has_feature(CPU_FTR_DSCR
)) {
1107 PPC_WARN_EMULATED(mfdscr
, regs
);
1108 rd
= (instword
>> 21) & 0x1f;
1109 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
1112 /* Emulate the mtspr DSCR, rD. */
1113 if ((((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
) ==
1114 PPC_INST_MTSPR_DSCR_USER
) ||
1115 ((instword
& PPC_INST_MTSPR_DSCR_MASK
) ==
1116 PPC_INST_MTSPR_DSCR
)) &&
1117 cpu_has_feature(CPU_FTR_DSCR
)) {
1118 PPC_WARN_EMULATED(mtdscr
, regs
);
1119 rd
= (instword
>> 21) & 0x1f;
1120 current
->thread
.dscr
= regs
->gpr
[rd
];
1121 current
->thread
.dscr_inherit
= 1;
1122 mtspr(SPRN_DSCR
, current
->thread
.dscr
);
1130 int is_valid_bugaddr(unsigned long addr
)
1132 return is_kernel_addr(addr
);
1135 #ifdef CONFIG_MATH_EMULATION
1136 static int emulate_math(struct pt_regs
*regs
)
1139 extern int do_mathemu(struct pt_regs
*regs
);
1141 ret
= do_mathemu(regs
);
1143 PPC_WARN_EMULATED(math
, regs
);
1147 emulate_single_step(regs
);
1151 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1152 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1156 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1163 static inline int emulate_math(struct pt_regs
*regs
) { return -1; }
1166 void program_check_exception(struct pt_regs
*regs
)
1168 enum ctx_state prev_state
= exception_enter();
1169 unsigned int reason
= get_reason(regs
);
1171 /* We can now get here via a FP Unavailable exception if the core
1172 * has no FPU, in that case the reason flags will be 0 */
1174 if (reason
& REASON_FP
) {
1175 /* IEEE FP exception */
1179 if (reason
& REASON_TRAP
) {
1180 unsigned long bugaddr
;
1181 /* Debugger is first in line to stop recursive faults in
1182 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1183 if (debugger_bpt(regs
))
1186 if (kprobe_handler(regs
))
1189 /* trap exception */
1190 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1194 bugaddr
= regs
->nip
;
1196 * Fixup bugaddr for BUG_ON() in real mode
1198 if (!is_kernel_addr(bugaddr
) && !(regs
->msr
& MSR_IR
))
1199 bugaddr
+= PAGE_OFFSET
;
1201 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1202 report_bug(bugaddr
, regs
) == BUG_TRAP_TYPE_WARN
) {
1206 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1209 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1210 if (reason
& REASON_TM
) {
1211 /* This is a TM "Bad Thing Exception" program check.
1213 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1214 * transition in TM states.
1215 * - A trechkpt is attempted when transactional.
1216 * - A treclaim is attempted when non transactional.
1217 * - A tend is illegally attempted.
1218 * - writing a TM SPR when transactional.
1220 if (!user_mode(regs
) &&
1221 report_bug(regs
->nip
, regs
) == BUG_TRAP_TYPE_WARN
) {
1225 /* If usermode caused this, it's done something illegal and
1226 * gets a SIGILL slap on the wrist. We call it an illegal
1227 * operand to distinguish from the instruction just being bad
1228 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1229 * illegal /placement/ of a valid instruction.
1231 if (user_mode(regs
)) {
1232 _exception(SIGILL
, regs
, ILL_ILLOPN
, regs
->nip
);
1235 printk(KERN_EMERG
"Unexpected TM Bad Thing exception "
1236 "at %lx (msr 0x%x)\n", regs
->nip
, reason
);
1237 die("Unrecoverable exception", regs
, SIGABRT
);
1243 * If we took the program check in the kernel skip down to sending a
1244 * SIGILL. The subsequent cases all relate to emulating instructions
1245 * which we should only do for userspace. We also do not want to enable
1246 * interrupts for kernel faults because that might lead to further
1247 * faults, and loose the context of the original exception.
1249 if (!user_mode(regs
))
1252 /* We restore the interrupt state now */
1253 if (!arch_irq_disabled_regs(regs
))
1256 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1257 * but there seems to be a hardware bug on the 405GP (RevD)
1258 * that means ESR is sometimes set incorrectly - either to
1259 * ESR_DST (!?) or 0. In the process of chasing this with the
1260 * hardware people - not sure if it can happen on any illegal
1261 * instruction or only on FP instructions, whether there is a
1262 * pattern to occurrences etc. -dgibson 31/Mar/2003
1264 if (!emulate_math(regs
))
1267 /* Try to emulate it if we should. */
1268 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1269 switch (emulate_instruction(regs
)) {
1272 emulate_single_step(regs
);
1275 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1281 if (reason
& REASON_PRIVILEGED
)
1282 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1284 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1287 exception_exit(prev_state
);
1289 NOKPROBE_SYMBOL(program_check_exception
);
1292 * This occurs when running in hypervisor mode on POWER6 or later
1293 * and an illegal instruction is encountered.
1295 void emulation_assist_interrupt(struct pt_regs
*regs
)
1297 regs
->msr
|= REASON_ILLEGAL
;
1298 program_check_exception(regs
);
1300 NOKPROBE_SYMBOL(emulation_assist_interrupt
);
1302 void alignment_exception(struct pt_regs
*regs
)
1304 enum ctx_state prev_state
= exception_enter();
1305 int sig
, code
, fixed
= 0;
1307 /* We restore the interrupt state now */
1308 if (!arch_irq_disabled_regs(regs
))
1311 if (tm_abort_check(regs
, TM_CAUSE_ALIGNMENT
| TM_CAUSE_PERSISTENT
))
1314 /* we don't implement logging of alignment exceptions */
1315 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1316 fixed
= fix_alignment(regs
);
1319 regs
->nip
+= 4; /* skip over emulated instruction */
1320 emulate_single_step(regs
);
1324 /* Operand address was bad */
1325 if (fixed
== -EFAULT
) {
1332 if (user_mode(regs
))
1333 _exception(sig
, regs
, code
, regs
->dar
);
1335 bad_page_fault(regs
, regs
->dar
, sig
);
1338 exception_exit(prev_state
);
1341 void slb_miss_bad_addr(struct pt_regs
*regs
)
1343 enum ctx_state prev_state
= exception_enter();
1345 if (user_mode(regs
))
1346 _exception(SIGSEGV
, regs
, SEGV_BNDERR
, regs
->dar
);
1348 bad_page_fault(regs
, regs
->dar
, SIGSEGV
);
1350 exception_exit(prev_state
);
1353 void StackOverflow(struct pt_regs
*regs
)
1355 printk(KERN_CRIT
"Kernel stack overflow in process %p, r1=%lx\n",
1356 current
, regs
->gpr
[1]);
1359 panic("kernel stack overflow");
1362 void nonrecoverable_exception(struct pt_regs
*regs
)
1364 printk(KERN_ERR
"Non-recoverable exception at PC=%lx MSR=%lx\n",
1365 regs
->nip
, regs
->msr
);
1367 die("nonrecoverable exception", regs
, SIGKILL
);
1370 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1372 enum ctx_state prev_state
= exception_enter();
1374 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1375 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1376 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1378 exception_exit(prev_state
);
1381 void altivec_unavailable_exception(struct pt_regs
*regs
)
1383 enum ctx_state prev_state
= exception_enter();
1385 if (user_mode(regs
)) {
1386 /* A user program has executed an altivec instruction,
1387 but this kernel doesn't support altivec. */
1388 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1392 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1393 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1394 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1397 exception_exit(prev_state
);
1400 void vsx_unavailable_exception(struct pt_regs
*regs
)
1402 if (user_mode(regs
)) {
1403 /* A user program has executed an vsx instruction,
1404 but this kernel doesn't support vsx. */
1405 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1409 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1410 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1411 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1415 static void tm_unavailable(struct pt_regs
*regs
)
1417 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1418 if (user_mode(regs
)) {
1419 current
->thread
.load_tm
++;
1420 regs
->msr
|= MSR_TM
;
1422 tm_restore_sprs(¤t
->thread
);
1426 pr_emerg("Unrecoverable TM Unavailable Exception "
1427 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1428 die("Unrecoverable TM Unavailable Exception", regs
, SIGABRT
);
1431 void facility_unavailable_exception(struct pt_regs
*regs
)
1433 static char *facility_strings
[] = {
1434 [FSCR_FP_LG
] = "FPU",
1435 [FSCR_VECVSX_LG
] = "VMX/VSX",
1436 [FSCR_DSCR_LG
] = "DSCR",
1437 [FSCR_PM_LG
] = "PMU SPRs",
1438 [FSCR_BHRB_LG
] = "BHRB",
1439 [FSCR_TM_LG
] = "TM",
1440 [FSCR_EBB_LG
] = "EBB",
1441 [FSCR_TAR_LG
] = "TAR",
1443 char *facility
= "unknown";
1449 hv
= (regs
->trap
== 0xf80);
1451 value
= mfspr(SPRN_HFSCR
);
1453 value
= mfspr(SPRN_FSCR
);
1455 status
= value
>> 56;
1456 if (status
== FSCR_DSCR_LG
) {
1458 * User is accessing the DSCR register using the problem
1459 * state only SPR number (0x03) either through a mfspr or
1460 * a mtspr instruction. If it is a write attempt through
1461 * a mtspr, then we set the inherit bit. This also allows
1462 * the user to write or read the register directly in the
1463 * future by setting via the FSCR DSCR bit. But in case it
1464 * is a read DSCR attempt through a mfspr instruction, we
1465 * just emulate the instruction instead. This code path will
1466 * always emulate all the mfspr instructions till the user
1467 * has attempted at least one mtspr instruction. This way it
1468 * preserves the same behaviour when the user is accessing
1469 * the DSCR through privilege level only SPR number (0x11)
1470 * which is emulated through illegal instruction exception.
1471 * We always leave HFSCR DSCR set.
1473 if (get_user(instword
, (u32 __user
*)(regs
->nip
))) {
1474 pr_err("Failed to fetch the user instruction\n");
1478 /* Write into DSCR (mtspr 0x03, RS) */
1479 if ((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
)
1480 == PPC_INST_MTSPR_DSCR_USER
) {
1481 rd
= (instword
>> 21) & 0x1f;
1482 current
->thread
.dscr
= regs
->gpr
[rd
];
1483 current
->thread
.dscr_inherit
= 1;
1484 current
->thread
.fscr
|= FSCR_DSCR
;
1485 mtspr(SPRN_FSCR
, current
->thread
.fscr
);
1488 /* Read from DSCR (mfspr RT, 0x03) */
1489 if ((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
)
1490 == PPC_INST_MFSPR_DSCR_USER
) {
1491 if (emulate_instruction(regs
)) {
1492 pr_err("DSCR based mfspr emulation failed\n");
1496 emulate_single_step(regs
);
1501 if (status
== FSCR_TM_LG
) {
1503 * If we're here then the hardware is TM aware because it
1504 * generated an exception with FSRM_TM set.
1506 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1507 * told us not to do TM, or the kernel is not built with TM
1510 * If both of those things are true, then userspace can spam the
1511 * console by triggering the printk() below just by continually
1512 * doing tbegin (or any TM instruction). So in that case just
1513 * send the process a SIGILL immediately.
1515 if (!cpu_has_feature(CPU_FTR_TM
))
1518 tm_unavailable(regs
);
1522 if ((hv
|| status
>= 2) &&
1523 (status
< ARRAY_SIZE(facility_strings
)) &&
1524 facility_strings
[status
])
1525 facility
= facility_strings
[status
];
1527 /* We restore the interrupt state now */
1528 if (!arch_irq_disabled_regs(regs
))
1531 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1532 hv
? "Hypervisor " : "", facility
, status
, regs
->nip
, regs
->msr
);
1535 if (user_mode(regs
)) {
1536 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1540 die("Unexpected facility unavailable exception", regs
, SIGABRT
);
1544 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1546 void fp_unavailable_tm(struct pt_regs
*regs
)
1548 /* Note: This does not handle any kind of FP laziness. */
1550 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1551 regs
->nip
, regs
->msr
);
1553 /* We can only have got here if the task started using FP after
1554 * beginning the transaction. So, the transactional regs are just a
1555 * copy of the checkpointed ones. But, we still need to recheckpoint
1556 * as we're enabling FP for the process; it will return, abort the
1557 * transaction, and probably retry but now with FP enabled. So the
1558 * checkpointed FP registers need to be loaded.
1560 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1561 /* Reclaim didn't save out any FPRs to transact_fprs. */
1563 /* Enable FP for the task: */
1564 regs
->msr
|= (MSR_FP
| current
->thread
.fpexc_mode
);
1566 /* This loads and recheckpoints the FP registers from
1567 * thread.fpr[]. They will remain in registers after the
1568 * checkpoint so we don't need to reload them after.
1569 * If VMX is in use, the VRs now hold checkpointed values,
1570 * so we don't want to load the VRs from the thread_struct.
1572 tm_recheckpoint(¤t
->thread
, MSR_FP
);
1574 /* If VMX is in use, get the transactional values back */
1575 if (regs
->msr
& MSR_VEC
) {
1576 msr_check_and_set(MSR_VEC
);
1577 load_vr_state(¤t
->thread
.vr_state
);
1578 /* At this point all the VSX state is loaded, so enable it */
1579 regs
->msr
|= MSR_VSX
;
1583 void altivec_unavailable_tm(struct pt_regs
*regs
)
1585 /* See the comments in fp_unavailable_tm(). This function operates
1589 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1591 regs
->nip
, regs
->msr
);
1592 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1593 regs
->msr
|= MSR_VEC
;
1594 tm_recheckpoint(¤t
->thread
, MSR_VEC
);
1595 current
->thread
.used_vr
= 1;
1597 if (regs
->msr
& MSR_FP
) {
1598 msr_check_and_set(MSR_FP
);
1599 load_fp_state(¤t
->thread
.fp_state
);
1600 regs
->msr
|= MSR_VSX
;
1604 void vsx_unavailable_tm(struct pt_regs
*regs
)
1606 unsigned long orig_msr
= regs
->msr
;
1608 /* See the comments in fp_unavailable_tm(). This works similarly,
1609 * though we're loading both FP and VEC registers in here.
1611 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1612 * regs. Either way, set MSR_VSX.
1615 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1617 regs
->nip
, regs
->msr
);
1619 current
->thread
.used_vsr
= 1;
1621 /* If FP and VMX are already loaded, we have all the state we need */
1622 if ((orig_msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
)) {
1623 regs
->msr
|= MSR_VSX
;
1627 /* This reclaims FP and/or VR regs if they're already enabled */
1628 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1630 regs
->msr
|= MSR_VEC
| MSR_FP
| current
->thread
.fpexc_mode
|
1633 /* This loads & recheckpoints FP and VRs; but we have
1634 * to be sure not to overwrite previously-valid state.
1636 tm_recheckpoint(¤t
->thread
, regs
->msr
& ~orig_msr
);
1638 msr_check_and_set(orig_msr
& (MSR_FP
| MSR_VEC
));
1640 if (orig_msr
& MSR_FP
)
1641 load_fp_state(¤t
->thread
.fp_state
);
1642 if (orig_msr
& MSR_VEC
)
1643 load_vr_state(¤t
->thread
.vr_state
);
1645 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1647 void performance_monitor_exception(struct pt_regs
*regs
)
1649 __this_cpu_inc(irq_stat
.pmu_irqs
);
1655 void SoftwareEmulation(struct pt_regs
*regs
)
1657 CHECK_FULL_REGS(regs
);
1659 if (!user_mode(regs
)) {
1661 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1665 if (!emulate_math(regs
))
1668 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1670 #endif /* CONFIG_8xx */
1672 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1673 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1677 * Determine the cause of the debug event, clear the
1678 * event flags and send a trap to the handler. Torez
1680 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1681 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1682 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1683 current
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
1685 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
, TRAP_HWBKPT
,
1688 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1689 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1690 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
, TRAP_HWBKPT
,
1693 } else if (debug_status
& DBSR_IAC1
) {
1694 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
1695 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1696 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
, TRAP_HWBKPT
,
1699 } else if (debug_status
& DBSR_IAC2
) {
1700 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
1701 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
, TRAP_HWBKPT
,
1704 } else if (debug_status
& DBSR_IAC3
) {
1705 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
1706 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1707 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
, TRAP_HWBKPT
,
1710 } else if (debug_status
& DBSR_IAC4
) {
1711 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
1712 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
, TRAP_HWBKPT
,
1717 * At the point this routine was called, the MSR(DE) was turned off.
1718 * Check all other debug flags and see if that bit needs to be turned
1721 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1722 current
->thread
.debug
.dbcr1
))
1723 regs
->msr
|= MSR_DE
;
1725 /* Make sure the IDM flag is off */
1726 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1729 mtspr(SPRN_DBCR0
, current
->thread
.debug
.dbcr0
);
1732 void DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1734 current
->thread
.debug
.dbsr
= debug_status
;
1736 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1737 * on server, it stops on the target of the branch. In order to simulate
1738 * the server behaviour, we thus restart right away with a single step
1739 * instead of stopping here when hitting a BT
1741 if (debug_status
& DBSR_BT
) {
1742 regs
->msr
&= ~MSR_DE
;
1745 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1746 /* Clear the BT event */
1747 mtspr(SPRN_DBSR
, DBSR_BT
);
1749 /* Do the single step trick only when coming from userspace */
1750 if (user_mode(regs
)) {
1751 current
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
1752 current
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1753 regs
->msr
|= MSR_DE
;
1757 if (kprobe_post_handler(regs
))
1760 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1761 5, SIGTRAP
) == NOTIFY_STOP
) {
1764 if (debugger_sstep(regs
))
1766 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
1767 regs
->msr
&= ~MSR_DE
;
1769 /* Disable instruction completion */
1770 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
1771 /* Clear the instruction completion event */
1772 mtspr(SPRN_DBSR
, DBSR_IC
);
1774 if (kprobe_post_handler(regs
))
1777 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1778 5, SIGTRAP
) == NOTIFY_STOP
) {
1782 if (debugger_sstep(regs
))
1785 if (user_mode(regs
)) {
1786 current
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
1787 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1788 current
->thread
.debug
.dbcr1
))
1789 regs
->msr
|= MSR_DE
;
1791 /* Make sure the IDM bit is off */
1792 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1795 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1797 handle_debug(regs
, debug_status
);
1799 NOKPROBE_SYMBOL(DebugException
);
1800 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1802 #if !defined(CONFIG_TAU_INT)
1803 void TAUException(struct pt_regs
*regs
)
1805 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1806 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
1808 #endif /* CONFIG_INT_TAU */
1810 #ifdef CONFIG_ALTIVEC
1811 void altivec_assist_exception(struct pt_regs
*regs
)
1815 if (!user_mode(regs
)) {
1816 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
1817 " at %lx\n", regs
->nip
);
1818 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
1821 flush_altivec_to_thread(current
);
1823 PPC_WARN_EMULATED(altivec
, regs
);
1824 err
= emulate_altivec(regs
);
1826 regs
->nip
+= 4; /* skip emulated instruction */
1827 emulate_single_step(regs
);
1831 if (err
== -EFAULT
) {
1832 /* got an error reading the instruction */
1833 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1835 /* didn't recognize the instruction */
1836 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1837 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
1838 "in %s at %lx\n", current
->comm
, regs
->nip
);
1839 current
->thread
.vr_state
.vscr
.u
[3] |= 0x10000;
1842 #endif /* CONFIG_ALTIVEC */
1844 #ifdef CONFIG_FSL_BOOKE
1845 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
1846 unsigned long error_code
)
1848 /* We treat cache locking instructions from the user
1849 * as priv ops, in the future we could try to do
1852 if (error_code
& (ESR_DLK
|ESR_ILK
))
1853 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1856 #endif /* CONFIG_FSL_BOOKE */
1859 void SPEFloatingPointException(struct pt_regs
*regs
)
1861 extern int do_spe_mathemu(struct pt_regs
*regs
);
1862 unsigned long spefscr
;
1867 flush_spe_to_thread(current
);
1869 spefscr
= current
->thread
.spefscr
;
1870 fpexc_mode
= current
->thread
.fpexc_mode
;
1872 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
1875 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
1878 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
1880 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
1883 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
1886 err
= do_spe_mathemu(regs
);
1888 regs
->nip
+= 4; /* skip emulated instruction */
1889 emulate_single_step(regs
);
1893 if (err
== -EFAULT
) {
1894 /* got an error reading the instruction */
1895 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1896 } else if (err
== -EINVAL
) {
1897 /* didn't recognize the instruction */
1898 printk(KERN_ERR
"unrecognized spe instruction "
1899 "in %s at %lx\n", current
->comm
, regs
->nip
);
1901 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1907 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
1909 extern int speround_handler(struct pt_regs
*regs
);
1913 if (regs
->msr
& MSR_SPE
)
1914 giveup_spe(current
);
1918 err
= speround_handler(regs
);
1920 regs
->nip
+= 4; /* skip emulated instruction */
1921 emulate_single_step(regs
);
1925 if (err
== -EFAULT
) {
1926 /* got an error reading the instruction */
1927 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1928 } else if (err
== -EINVAL
) {
1929 /* didn't recognize the instruction */
1930 printk(KERN_ERR
"unrecognized spe instruction "
1931 "in %s at %lx\n", current
->comm
, regs
->nip
);
1933 _exception(SIGFPE
, regs
, 0, regs
->nip
);
1940 * We enter here if we get an unrecoverable exception, that is, one
1941 * that happened at a point where the RI (recoverable interrupt) bit
1942 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1943 * we therefore lost state by taking this exception.
1945 void unrecoverable_exception(struct pt_regs
*regs
)
1947 printk(KERN_EMERG
"Unrecoverable exception %lx at %lx\n",
1948 regs
->trap
, regs
->nip
);
1949 die("Unrecoverable exception", regs
, SIGABRT
);
1952 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1954 * Default handler for a Watchdog exception,
1955 * spins until a reboot occurs
1957 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
1959 /* Generic WatchdogHandler, implement your own */
1960 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
1964 void WatchdogException(struct pt_regs
*regs
)
1966 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
1967 WatchdogHandler(regs
);
1972 * We enter here if we discover during exception entry that we are
1973 * running in supervisor mode with a userspace value in the stack pointer.
1975 void kernel_bad_stack(struct pt_regs
*regs
)
1977 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
1978 regs
->gpr
[1], regs
->nip
);
1979 die("Bad kernel stack pointer", regs
, SIGABRT
);
1982 void __init
trap_init(void)
1987 #ifdef CONFIG_PPC_EMULATED_STATS
1989 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1991 struct ppc_emulated ppc_emulated
= {
1992 #ifdef CONFIG_ALTIVEC
1993 WARN_EMULATED_SETUP(altivec
),
1995 WARN_EMULATED_SETUP(dcba
),
1996 WARN_EMULATED_SETUP(dcbz
),
1997 WARN_EMULATED_SETUP(fp_pair
),
1998 WARN_EMULATED_SETUP(isel
),
1999 WARN_EMULATED_SETUP(mcrxr
),
2000 WARN_EMULATED_SETUP(mfpvr
),
2001 WARN_EMULATED_SETUP(multiple
),
2002 WARN_EMULATED_SETUP(popcntb
),
2003 WARN_EMULATED_SETUP(spe
),
2004 WARN_EMULATED_SETUP(string
),
2005 WARN_EMULATED_SETUP(sync
),
2006 WARN_EMULATED_SETUP(unaligned
),
2007 #ifdef CONFIG_MATH_EMULATION
2008 WARN_EMULATED_SETUP(math
),
2011 WARN_EMULATED_SETUP(vsx
),
2014 WARN_EMULATED_SETUP(mfdscr
),
2015 WARN_EMULATED_SETUP(mtdscr
),
2016 WARN_EMULATED_SETUP(lq_stq
),
2020 u32 ppc_warn_emulated
;
2022 void ppc_warn_emulated_print(const char *type
)
2024 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
2028 static int __init
ppc_warn_emulated_init(void)
2030 struct dentry
*dir
, *d
;
2032 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
2034 if (!powerpc_debugfs_root
)
2037 dir
= debugfs_create_dir("emulated_instructions",
2038 powerpc_debugfs_root
);
2042 d
= debugfs_create_u32("do_warn", S_IRUGO
| S_IWUSR
, dir
,
2043 &ppc_warn_emulated
);
2047 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
2048 d
= debugfs_create_u32(entries
[i
].name
, S_IRUGO
| S_IWUSR
, dir
,
2049 (u32
*)&entries
[i
].val
.counter
);
2057 debugfs_remove_recursive(dir
);
2061 device_initcall(ppc_warn_emulated_init
);
2063 #endif /* CONFIG_PPC_EMULATED_STATS */