2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/kernel.h>
23 #include <linux/pkeys.h>
24 #include <linux/stddef.h>
25 #include <linux/unistd.h>
26 #include <linux/ptrace.h>
27 #include <linux/user.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/extable.h>
31 #include <linux/module.h> /* print_modules */
32 #include <linux/prctl.h>
33 #include <linux/delay.h>
34 #include <linux/kprobes.h>
35 #include <linux/kexec.h>
36 #include <linux/backlight.h>
37 #include <linux/bug.h>
38 #include <linux/kdebug.h>
39 #include <linux/ratelimit.h>
40 #include <linux/context_tracking.h>
41 #include <linux/smp.h>
42 #include <linux/console.h>
43 #include <linux/kmsg_dump.h>
45 #include <asm/emulated_ops.h>
46 #include <asm/pgtable.h>
47 #include <linux/uaccess.h>
48 #include <asm/debugfs.h>
50 #include <asm/machdep.h>
54 #ifdef CONFIG_PMAC_BACKLIGHT
55 #include <asm/backlight.h>
58 #include <asm/firmware.h>
59 #include <asm/processor.h>
62 #include <asm/kexec.h>
63 #include <asm/ppc-opcode.h>
65 #include <asm/fadump.h>
66 #include <asm/switch_to.h>
68 #include <asm/debug.h>
69 #include <asm/asm-prototypes.h>
71 #include <sysdev/fsl_pci.h>
72 #include <asm/kprobes.h>
73 #include <asm/stacktrace.h>
75 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
76 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
77 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
78 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
79 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
80 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
81 int (*__debugger_break_match
)(struct pt_regs
*regs
) __read_mostly
;
82 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
84 EXPORT_SYMBOL(__debugger
);
85 EXPORT_SYMBOL(__debugger_ipi
);
86 EXPORT_SYMBOL(__debugger_bpt
);
87 EXPORT_SYMBOL(__debugger_sstep
);
88 EXPORT_SYMBOL(__debugger_iabr_match
);
89 EXPORT_SYMBOL(__debugger_break_match
);
90 EXPORT_SYMBOL(__debugger_fault_handler
);
93 /* Transactional Memory trap debug */
95 #define TM_DEBUG(x...) printk(KERN_INFO x)
97 #define TM_DEBUG(x...) do { } while(0)
100 static const char *signame(int signr
)
103 case SIGBUS
: return "bus error";
104 case SIGFPE
: return "floating point exception";
105 case SIGILL
: return "illegal instruction";
106 case SIGSEGV
: return "segfault";
107 case SIGTRAP
: return "unhandled trap";
110 return "unknown signal";
114 * Trap & Exception support
117 #ifdef CONFIG_PMAC_BACKLIGHT
118 static void pmac_backlight_unblank(void)
120 mutex_lock(&pmac_backlight_mutex
);
121 if (pmac_backlight
) {
122 struct backlight_properties
*props
;
124 props
= &pmac_backlight
->props
;
125 props
->brightness
= props
->max_brightness
;
126 props
->power
= FB_BLANK_UNBLANK
;
127 backlight_update_status(pmac_backlight
);
129 mutex_unlock(&pmac_backlight_mutex
);
132 static inline void pmac_backlight_unblank(void) { }
136 * If oops/die is expected to crash the machine, return true here.
138 * This should not be expected to be 100% accurate, there may be
139 * notifiers registered or other unexpected conditions that may bring
140 * down the kernel. Or if the current process in the kernel is holding
141 * locks or has other critical state, the kernel may become effectively
144 bool die_will_crash(void)
146 if (should_fadump_crash())
148 if (kexec_should_crash(current
))
150 if (in_interrupt() || panic_on_oops
||
151 !current
->pid
|| is_global_init(current
))
157 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
158 static int die_owner
= -1;
159 static unsigned int die_nest_count
;
160 static int die_counter
;
162 extern void panic_flush_kmsg_start(void)
165 * These are mostly taken from kernel/panic.c, but tries to do
166 * relatively minimal work. Don't use delay functions (TB may
167 * be broken), don't crash dump (need to set a firmware log),
168 * don't run notifiers. We do want to get some information to
175 extern void panic_flush_kmsg_end(void)
177 printk_safe_flush_on_panic();
178 kmsg_dump(KMSG_DUMP_PANIC
);
181 console_flush_on_panic();
184 static unsigned long oops_begin(struct pt_regs
*regs
)
191 /* racy, but better than risking deadlock. */
192 raw_local_irq_save(flags
);
193 cpu
= smp_processor_id();
194 if (!arch_spin_trylock(&die_lock
)) {
195 if (cpu
== die_owner
)
196 /* nested oops. should stop eventually */;
198 arch_spin_lock(&die_lock
);
204 if (machine_is(powermac
))
205 pmac_backlight_unblank();
208 NOKPROBE_SYMBOL(oops_begin
);
210 static void oops_end(unsigned long flags
, struct pt_regs
*regs
,
214 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
218 if (!die_nest_count
) {
219 /* Nest count reaches zero, release the lock. */
221 arch_spin_unlock(&die_lock
);
223 raw_local_irq_restore(flags
);
226 * system_reset_excption handles debugger, crash dump, panic, for 0x100
228 if (TRAP(regs
) == 0x100)
231 crash_fadump(regs
, "die oops");
233 if (kexec_should_crash(current
))
240 * While our oops output is serialised by a spinlock, output
241 * from panic() called below can race and corrupt it. If we
242 * know we are going to panic, delay for 1 second so we have a
243 * chance to get clean backtraces from all CPUs that are oopsing.
245 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
246 is_global_init(current
)) {
247 mdelay(MSEC_PER_SEC
);
251 panic("Fatal exception");
254 NOKPROBE_SYMBOL(oops_end
);
256 static int __die(const char *str
, struct pt_regs
*regs
, long err
)
258 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
260 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s%s %s\n",
261 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN
) ? "LE" : "BE",
263 early_radix_enabled() ? " MMU=Radix" : "",
264 early_mmu_has_feature(MMU_FTR_HPTE_TABLE
) ? " MMU=Hash" : "",
265 IS_ENABLED(CONFIG_PREEMPT
) ? " PREEMPT" : "",
266 IS_ENABLED(CONFIG_SMP
) ? " SMP" : "",
267 IS_ENABLED(CONFIG_SMP
) ? (" NR_CPUS=" __stringify(NR_CPUS
)) : "",
268 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
269 IS_ENABLED(CONFIG_NUMA
) ? " NUMA" : "",
270 ppc_md
.name
? ppc_md
.name
: "");
272 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
280 NOKPROBE_SYMBOL(__die
);
282 void die(const char *str
, struct pt_regs
*regs
, long err
)
287 * system_reset_excption handles debugger, crash dump, panic, for 0x100
289 if (TRAP(regs
) != 0x100) {
294 flags
= oops_begin(regs
);
295 if (__die(str
, regs
, err
))
297 oops_end(flags
, regs
, err
);
299 NOKPROBE_SYMBOL(die
);
301 void user_single_step_report(struct pt_regs
*regs
)
303 force_sig_fault(SIGTRAP
, TRAP_TRACE
, (void __user
*)regs
->nip
, current
);
306 static void show_signal_msg(int signr
, struct pt_regs
*regs
, int code
,
309 static DEFINE_RATELIMIT_STATE(rs
, DEFAULT_RATELIMIT_INTERVAL
,
310 DEFAULT_RATELIMIT_BURST
);
312 if (!show_unhandled_signals
)
315 if (!unhandled_signal(current
, signr
))
318 if (!__ratelimit(&rs
))
321 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
322 current
->comm
, current
->pid
, signame(signr
), signr
,
323 addr
, regs
->nip
, regs
->link
, code
);
325 print_vma_addr(KERN_CONT
" in ", regs
->nip
);
329 show_user_instructions(regs
);
332 static bool exception_common(int signr
, struct pt_regs
*regs
, int code
,
335 if (!user_mode(regs
)) {
336 die("Exception in kernel mode", regs
, signr
);
340 show_signal_msg(signr
, regs
, code
, addr
);
342 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
345 current
->thread
.trap_nr
= code
;
348 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need
349 * to capture the content, if the task gets killed.
351 thread_pkey_regs_save(¤t
->thread
);
356 void _exception_pkey(struct pt_regs
*regs
, unsigned long addr
, int key
)
358 if (!exception_common(SIGSEGV
, regs
, SEGV_PKUERR
, addr
))
361 force_sig_pkuerr((void __user
*) addr
, key
);
364 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
366 if (!exception_common(signr
, regs
, code
, addr
))
369 force_sig_fault(signr
, code
, (void __user
*)addr
, current
);
373 * The interrupt architecture has a quirk in that the HV interrupts excluding
374 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing
375 * that an interrupt handler must do is save off a GPR into a scratch register,
376 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch.
377 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing
378 * that it is non-reentrant, which leads to random data corruption.
380 * The solution is for NMI interrupts in HV mode to check if they originated
381 * from these critical HV interrupt regions. If so, then mark them not
384 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the
385 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux
386 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so
387 * that would work. However any other guest OS that may have the SPRG live
388 * and MSR[RI]=1 could encounter silent corruption.
390 * Builds that do not support KVM could take this second option to increase
391 * the recoverability of NMIs.
393 void hv_nmi_check_nonrecoverable(struct pt_regs
*regs
)
395 #ifdef CONFIG_PPC_POWERNV
396 unsigned long kbase
= (unsigned long)_stext
;
397 unsigned long nip
= regs
->nip
;
399 if (!(regs
->msr
& MSR_RI
))
401 if (!(regs
->msr
& MSR_HV
))
403 if (regs
->msr
& MSR_PR
)
407 * Now test if the interrupt has hit a range that may be using
408 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The
409 * problem ranges all run un-relocated. Test real and virt modes
410 * at the same time by droping the high bit of the nip (virt mode
411 * entry points still have the +0x4000 offset).
413 nip
&= ~0xc000000000000000ULL
;
414 if ((nip
>= 0x500 && nip
< 0x600) || (nip
>= 0x4500 && nip
< 0x4600))
416 if ((nip
>= 0x980 && nip
< 0xa00) || (nip
>= 0x4980 && nip
< 0x4a00))
418 if ((nip
>= 0xe00 && nip
< 0xec0) || (nip
>= 0x4e00 && nip
< 0x4ec0))
420 if ((nip
>= 0xf80 && nip
< 0xfa0) || (nip
>= 0x4f80 && nip
< 0x4fa0))
423 /* Trampoline code runs un-relocated so subtract kbase. */
424 if (nip
>= (unsigned long)(start_real_trampolines
- kbase
) &&
425 nip
< (unsigned long)(end_real_trampolines
- kbase
))
427 if (nip
>= (unsigned long)(start_virt_trampolines
- kbase
) &&
428 nip
< (unsigned long)(end_virt_trampolines
- kbase
))
433 regs
->msr
&= ~MSR_RI
;
437 void system_reset_exception(struct pt_regs
*regs
)
439 unsigned long hsrr0
, hsrr1
;
440 bool nested
= in_nmi();
441 bool saved_hsrrs
= false;
444 * Avoid crashes in case of nested NMI exceptions. Recoverability
445 * is determined by RI and in_nmi
451 * System reset can interrupt code where HSRRs are live and MSR[RI]=1.
452 * The system reset interrupt itself may clobber HSRRs (e.g., to call
453 * OPAL), so save them here and restore them before returning.
455 * Machine checks don't need to save HSRRs, as the real mode handler
456 * is careful to avoid them, and the regular handler is not delivered
459 if (cpu_has_feature(CPU_FTR_HVMODE
)) {
460 hsrr0
= mfspr(SPRN_HSRR0
);
461 hsrr1
= mfspr(SPRN_HSRR1
);
465 hv_nmi_check_nonrecoverable(regs
);
467 __this_cpu_inc(irq_stat
.sreset_irqs
);
469 /* See if any machine dependent calls */
470 if (ppc_md
.system_reset_exception
) {
471 if (ppc_md
.system_reset_exception(regs
))
479 * A system reset is a request to dump, so we always send
480 * it through the crashdump code (if fadump or kdump are
483 crash_fadump(regs
, "System Reset");
488 * We aren't the primary crash CPU. We need to send it
489 * to a holding pattern to avoid it ending up in the panic
492 crash_kexec_secondary(regs
);
495 * No debugger or crash dump registered, print logs then
498 die("System Reset", regs
, SIGABRT
);
500 mdelay(2*MSEC_PER_SEC
); /* Wait a little while for others to print */
501 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
502 nmi_panic(regs
, "System Reset");
505 #ifdef CONFIG_PPC_BOOK3S_64
506 BUG_ON(get_paca()->in_nmi
== 0);
507 if (get_paca()->in_nmi
> 1)
508 nmi_panic(regs
, "Unrecoverable nested System Reset");
510 /* Must die if the interrupt is not recoverable */
511 if (!(regs
->msr
& MSR_RI
))
512 nmi_panic(regs
, "Unrecoverable System Reset");
515 mtspr(SPRN_HSRR0
, hsrr0
);
516 mtspr(SPRN_HSRR1
, hsrr1
);
522 /* What should we do here? We could issue a shutdown or hard reset. */
526 * I/O accesses can cause machine checks on powermacs.
527 * Check if the NIP corresponds to the address of a sync
528 * instruction for which there is an entry in the exception
530 * Note that the 601 only takes a machine check on TEA
531 * (transfer error ack) signal assertion, and does not
532 * set any of the top 16 bits of SRR1.
535 static inline int check_io_access(struct pt_regs
*regs
)
538 unsigned long msr
= regs
->msr
;
539 const struct exception_table_entry
*entry
;
540 unsigned int *nip
= (unsigned int *)regs
->nip
;
542 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
543 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
545 * Check that it's a sync instruction, or somewhere
546 * in the twi; isync; nop sequence that inb/inw/inl uses.
547 * As the address is in the exception table
548 * we should be able to read the instr there.
549 * For the debug message, we look at the preceding
552 if (*nip
== PPC_INST_NOP
)
554 else if (*nip
== PPC_INST_ISYNC
)
556 if (*nip
== PPC_INST_SYNC
|| (*nip
>> 26) == OP_TRAP
) {
560 rb
= (*nip
>> 11) & 0x1f;
561 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
562 (*nip
& 0x100)? "OUT to": "IN from",
563 regs
->gpr
[rb
] - _IO_BASE
, nip
);
565 regs
->nip
= extable_fixup(entry
);
569 #endif /* CONFIG_PPC32 */
573 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
574 /* On 4xx, the reason for the machine check or program exception
576 #define get_reason(regs) ((regs)->dsisr)
577 #define REASON_FP ESR_FP
578 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
579 #define REASON_PRIVILEGED ESR_PPR
580 #define REASON_TRAP ESR_PTR
582 /* single-step stuff */
583 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
584 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
585 #define clear_br_trace(regs) do {} while(0)
587 /* On non-4xx, the reason for the machine check or program
588 exception is in the MSR. */
589 #define get_reason(regs) ((regs)->msr)
590 #define REASON_TM SRR1_PROGTM
591 #define REASON_FP SRR1_PROGFPE
592 #define REASON_ILLEGAL SRR1_PROGILL
593 #define REASON_PRIVILEGED SRR1_PROGPRIV
594 #define REASON_TRAP SRR1_PROGTRAP
596 #define single_stepping(regs) ((regs)->msr & MSR_SE)
597 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
598 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE)
601 #if defined(CONFIG_E500)
602 int machine_check_e500mc(struct pt_regs
*regs
)
604 unsigned long mcsr
= mfspr(SPRN_MCSR
);
605 unsigned long pvr
= mfspr(SPRN_PVR
);
606 unsigned long reason
= mcsr
;
609 if (reason
& MCSR_LD
) {
610 recoverable
= fsl_rio_mcheck_exception(regs
);
611 if (recoverable
== 1)
615 printk("Machine check in kernel mode.\n");
616 printk("Caused by (from MCSR=%lx): ", reason
);
618 if (reason
& MCSR_MCP
)
619 pr_cont("Machine Check Signal\n");
621 if (reason
& MCSR_ICPERR
) {
622 pr_cont("Instruction Cache Parity Error\n");
625 * This is recoverable by invalidating the i-cache.
627 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
628 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
632 * This will generally be accompanied by an instruction
633 * fetch error report -- only treat MCSR_IF as fatal
634 * if it wasn't due to an L1 parity error.
639 if (reason
& MCSR_DCPERR_MC
) {
640 pr_cont("Data Cache Parity Error\n");
643 * In write shadow mode we auto-recover from the error, but it
644 * may still get logged and cause a machine check. We should
645 * only treat the non-write shadow case as non-recoverable.
647 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
648 * is not implemented but L1 data cache always runs in write
649 * shadow mode. Hence on data cache parity errors HW will
650 * automatically invalidate the L1 Data Cache.
652 if (PVR_VER(pvr
) != PVR_VER_E6500
) {
653 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
658 if (reason
& MCSR_L2MMU_MHIT
) {
659 pr_cont("Hit on multiple TLB entries\n");
663 if (reason
& MCSR_NMI
)
664 pr_cont("Non-maskable interrupt\n");
666 if (reason
& MCSR_IF
) {
667 pr_cont("Instruction Fetch Error Report\n");
671 if (reason
& MCSR_LD
) {
672 pr_cont("Load Error Report\n");
676 if (reason
& MCSR_ST
) {
677 pr_cont("Store Error Report\n");
681 if (reason
& MCSR_LDG
) {
682 pr_cont("Guarded Load Error Report\n");
686 if (reason
& MCSR_TLBSYNC
)
687 pr_cont("Simultaneous tlbsync operations\n");
689 if (reason
& MCSR_BSL2_ERR
) {
690 pr_cont("Level 2 Cache Error\n");
694 if (reason
& MCSR_MAV
) {
697 addr
= mfspr(SPRN_MCAR
);
698 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
700 pr_cont("Machine Check %s Address: %#llx\n",
701 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
705 mtspr(SPRN_MCSR
, mcsr
);
706 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
709 int machine_check_e500(struct pt_regs
*regs
)
711 unsigned long reason
= mfspr(SPRN_MCSR
);
713 if (reason
& MCSR_BUS_RBERR
) {
714 if (fsl_rio_mcheck_exception(regs
))
716 if (fsl_pci_mcheck_exception(regs
))
720 printk("Machine check in kernel mode.\n");
721 printk("Caused by (from MCSR=%lx): ", reason
);
723 if (reason
& MCSR_MCP
)
724 pr_cont("Machine Check Signal\n");
725 if (reason
& MCSR_ICPERR
)
726 pr_cont("Instruction Cache Parity Error\n");
727 if (reason
& MCSR_DCP_PERR
)
728 pr_cont("Data Cache Push Parity Error\n");
729 if (reason
& MCSR_DCPERR
)
730 pr_cont("Data Cache Parity Error\n");
731 if (reason
& MCSR_BUS_IAERR
)
732 pr_cont("Bus - Instruction Address Error\n");
733 if (reason
& MCSR_BUS_RAERR
)
734 pr_cont("Bus - Read Address Error\n");
735 if (reason
& MCSR_BUS_WAERR
)
736 pr_cont("Bus - Write Address Error\n");
737 if (reason
& MCSR_BUS_IBERR
)
738 pr_cont("Bus - Instruction Data Error\n");
739 if (reason
& MCSR_BUS_RBERR
)
740 pr_cont("Bus - Read Data Bus Error\n");
741 if (reason
& MCSR_BUS_WBERR
)
742 pr_cont("Bus - Write Data Bus Error\n");
743 if (reason
& MCSR_BUS_IPERR
)
744 pr_cont("Bus - Instruction Parity Error\n");
745 if (reason
& MCSR_BUS_RPERR
)
746 pr_cont("Bus - Read Parity Error\n");
751 int machine_check_generic(struct pt_regs
*regs
)
755 #elif defined(CONFIG_E200)
756 int machine_check_e200(struct pt_regs
*regs
)
758 unsigned long reason
= mfspr(SPRN_MCSR
);
760 printk("Machine check in kernel mode.\n");
761 printk("Caused by (from MCSR=%lx): ", reason
);
763 if (reason
& MCSR_MCP
)
764 pr_cont("Machine Check Signal\n");
765 if (reason
& MCSR_CP_PERR
)
766 pr_cont("Cache Push Parity Error\n");
767 if (reason
& MCSR_CPERR
)
768 pr_cont("Cache Parity Error\n");
769 if (reason
& MCSR_EXCP_ERR
)
770 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
771 if (reason
& MCSR_BUS_IRERR
)
772 pr_cont("Bus - Read Bus Error on instruction fetch\n");
773 if (reason
& MCSR_BUS_DRERR
)
774 pr_cont("Bus - Read Bus Error on data load\n");
775 if (reason
& MCSR_BUS_WRERR
)
776 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n");
780 #elif defined(CONFIG_PPC32)
781 int machine_check_generic(struct pt_regs
*regs
)
783 unsigned long reason
= regs
->msr
;
785 printk("Machine check in kernel mode.\n");
786 printk("Caused by (from SRR1=%lx): ", reason
);
787 switch (reason
& 0x601F0000) {
789 pr_cont("Machine check signal\n");
791 case 0: /* for 601 */
793 case 0x140000: /* 7450 MSS error and TEA */
794 pr_cont("Transfer error ack signal\n");
797 pr_cont("Data parity error signal\n");
800 pr_cont("Address parity error signal\n");
803 pr_cont("L1 Data Cache error\n");
806 pr_cont("L1 Instruction Cache error\n");
809 pr_cont("L2 data cache parity error\n");
812 pr_cont("Unknown values in msr\n");
816 #endif /* everything else */
818 void machine_check_exception(struct pt_regs
*regs
)
821 bool nested
= in_nmi();
825 __this_cpu_inc(irq_stat
.mce_exceptions
);
827 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
829 /* See if any machine dependent calls. In theory, we would want
830 * to call the CPU first, and call the ppc_md. one if the CPU
831 * one returns a positive number. However there is existing code
832 * that assumes the board gets a first chance, so let's keep it
833 * that way for now and fix things later. --BenH.
835 if (ppc_md
.machine_check_exception
)
836 recover
= ppc_md
.machine_check_exception(regs
);
837 else if (cur_cpu_spec
->machine_check
)
838 recover
= cur_cpu_spec
->machine_check(regs
);
843 if (debugger_fault_handler(regs
))
846 if (check_io_access(regs
))
852 die("Machine check", regs
, SIGBUS
);
854 /* Must die if the interrupt is not recoverable */
855 if (!(regs
->msr
& MSR_RI
))
856 nmi_panic(regs
, "Unrecoverable Machine check");
865 void SMIException(struct pt_regs
*regs
)
867 die("System Management Interrupt", regs
, SIGABRT
);
871 static void p9_hmi_special_emu(struct pt_regs
*regs
)
873 unsigned int ra
, rb
, t
, i
, sel
, instr
, rc
;
874 const void __user
*addr
;
876 unsigned long ea
, msr
, msr_mask
;
879 if (__get_user_inatomic(instr
, (unsigned int __user
*)regs
->nip
))
883 * lxvb16x opcode: 0x7c0006d8
884 * lxvd2x opcode: 0x7c000698
885 * lxvh8x opcode: 0x7c000658
886 * lxvw4x opcode: 0x7c000618
888 if ((instr
& 0xfc00073e) != 0x7c000618) {
889 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
891 smp_processor_id(), current
->comm
, current
->pid
,
896 /* Grab vector registers into the task struct */
897 msr
= regs
->msr
; /* Grab msr before we flush the bits */
898 flush_vsx_to_thread(current
);
899 enable_kernel_altivec();
902 * Is userspace running with a different endian (this is rare but
905 swap
= (msr
& MSR_LE
) != (MSR_KERNEL
& MSR_LE
);
907 /* Decode the instruction */
908 ra
= (instr
>> 16) & 0x1f;
909 rb
= (instr
>> 11) & 0x1f;
910 t
= (instr
>> 21) & 0x1f;
912 vdst
= (u8
*)¤t
->thread
.vr_state
.vr
[t
];
914 vdst
= (u8
*)¤t
->thread
.fp_state
.fpr
[t
][0];
916 /* Grab the vector address */
917 ea
= regs
->gpr
[rb
] + (ra
? regs
->gpr
[ra
] : 0);
920 addr
= (__force
const void __user
*)ea
;
923 if (!access_ok(addr
, 16)) {
924 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
925 " instr=%08x addr=%016lx\n",
926 smp_processor_id(), current
->comm
, current
->pid
,
927 regs
->nip
, instr
, (unsigned long)addr
);
931 /* Read the vector */
933 if ((unsigned long)addr
& 0xfUL
)
935 rc
= __copy_from_user_inatomic(vbuf
, addr
, 16);
937 __get_user_atomic_128_aligned(vbuf
, addr
, rc
);
939 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
940 " instr=%08x addr=%016lx\n",
941 smp_processor_id(), current
->comm
, current
->pid
,
942 regs
->nip
, instr
, (unsigned long)addr
);
946 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
947 " instr=%08x addr=%016lx\n",
948 smp_processor_id(), current
->comm
, current
->pid
, regs
->nip
,
949 instr
, (unsigned long) addr
);
951 /* Grab instruction "selector" */
952 sel
= (instr
>> 6) & 3;
955 * Check to make sure the facility is actually enabled. This
956 * could happen if we get a false positive hit.
958 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
959 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
962 if ((sel
& 1) && (instr
& 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
964 if (!(msr
& msr_mask
)) {
965 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
966 " instr=%08x msr:%016lx\n",
967 smp_processor_id(), current
->comm
, current
->pid
,
968 regs
->nip
, instr
, msr
);
972 /* Do logging here before we modify sel based on endian */
975 PPC_WARN_EMULATED(lxvw4x
, regs
);
978 PPC_WARN_EMULATED(lxvh8x
, regs
);
981 PPC_WARN_EMULATED(lxvd2x
, regs
);
983 case 3: /* lxvb16x */
984 PPC_WARN_EMULATED(lxvb16x
, regs
);
988 #ifdef __LITTLE_ENDIAN__
990 * An LE kernel stores the vector in the task struct as an LE
991 * byte array (effectively swapping both the components and
992 * the content of the components). Those instructions expect
993 * the components to remain in ascending address order, so we
996 * If we are running a BE user space, the expectation is that
997 * of a simple memcpy, so forcing the emulation to look like
998 * a lxvb16x should do the trick.
1004 case 0: /* lxvw4x */
1005 for (i
= 0; i
< 4; i
++)
1006 ((u32
*)vdst
)[i
] = ((u32
*)vbuf
)[3-i
];
1008 case 1: /* lxvh8x */
1009 for (i
= 0; i
< 8; i
++)
1010 ((u16
*)vdst
)[i
] = ((u16
*)vbuf
)[7-i
];
1012 case 2: /* lxvd2x */
1013 for (i
= 0; i
< 2; i
++)
1014 ((u64
*)vdst
)[i
] = ((u64
*)vbuf
)[1-i
];
1016 case 3: /* lxvb16x */
1017 for (i
= 0; i
< 16; i
++)
1018 vdst
[i
] = vbuf
[15-i
];
1021 #else /* __LITTLE_ENDIAN__ */
1022 /* On a big endian kernel, a BE userspace only needs a memcpy */
1026 /* Otherwise, we need to swap the content of the components */
1028 case 0: /* lxvw4x */
1029 for (i
= 0; i
< 4; i
++)
1030 ((u32
*)vdst
)[i
] = cpu_to_le32(((u32
*)vbuf
)[i
]);
1032 case 1: /* lxvh8x */
1033 for (i
= 0; i
< 8; i
++)
1034 ((u16
*)vdst
)[i
] = cpu_to_le16(((u16
*)vbuf
)[i
]);
1036 case 2: /* lxvd2x */
1037 for (i
= 0; i
< 2; i
++)
1038 ((u64
*)vdst
)[i
] = cpu_to_le64(((u64
*)vbuf
)[i
]);
1040 case 3: /* lxvb16x */
1041 memcpy(vdst
, vbuf
, 16);
1044 #endif /* !__LITTLE_ENDIAN__ */
1046 /* Go to next instruction */
1049 #endif /* CONFIG_VSX */
1051 void handle_hmi_exception(struct pt_regs
*regs
)
1053 struct pt_regs
*old_regs
;
1055 old_regs
= set_irq_regs(regs
);
1059 /* Real mode flagged P9 special emu is needed */
1060 if (local_paca
->hmi_p9_special_emu
) {
1061 local_paca
->hmi_p9_special_emu
= 0;
1064 * We don't want to take page faults while doing the
1065 * emulation, we just replay the instruction if necessary.
1067 pagefault_disable();
1068 p9_hmi_special_emu(regs
);
1071 #endif /* CONFIG_VSX */
1073 if (ppc_md
.handle_hmi_exception
)
1074 ppc_md
.handle_hmi_exception(regs
);
1077 set_irq_regs(old_regs
);
1080 void unknown_exception(struct pt_regs
*regs
)
1082 enum ctx_state prev_state
= exception_enter();
1084 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1085 regs
->nip
, regs
->msr
, regs
->trap
);
1087 _exception(SIGTRAP
, regs
, TRAP_UNK
, 0);
1089 exception_exit(prev_state
);
1092 void instruction_breakpoint_exception(struct pt_regs
*regs
)
1094 enum ctx_state prev_state
= exception_enter();
1096 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
1097 5, SIGTRAP
) == NOTIFY_STOP
)
1099 if (debugger_iabr_match(regs
))
1101 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1104 exception_exit(prev_state
);
1107 void RunModeException(struct pt_regs
*regs
)
1109 _exception(SIGTRAP
, regs
, TRAP_UNK
, 0);
1112 void single_step_exception(struct pt_regs
*regs
)
1114 enum ctx_state prev_state
= exception_enter();
1116 clear_single_step(regs
);
1117 clear_br_trace(regs
);
1119 if (kprobe_post_handler(regs
))
1122 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1123 5, SIGTRAP
) == NOTIFY_STOP
)
1125 if (debugger_sstep(regs
))
1128 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1131 exception_exit(prev_state
);
1133 NOKPROBE_SYMBOL(single_step_exception
);
1136 * After we have successfully emulated an instruction, we have to
1137 * check if the instruction was being single-stepped, and if so,
1138 * pretend we got a single-step exception. This was pointed out
1139 * by Kumar Gala. -- paulus
1141 static void emulate_single_step(struct pt_regs
*regs
)
1143 if (single_stepping(regs
))
1144 single_step_exception(regs
);
1147 static inline int __parse_fpscr(unsigned long fpscr
)
1149 int ret
= FPE_FLTUNK
;
1151 /* Invalid operation */
1152 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
1156 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
1160 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
1163 /* Divide by zero */
1164 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
1167 /* Inexact result */
1168 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
1174 static void parse_fpe(struct pt_regs
*regs
)
1178 flush_fp_to_thread(current
);
1180 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1182 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1186 * Illegal instruction emulation support. Originally written to
1187 * provide the PVR to user applications using the mfspr rd, PVR.
1188 * Return non-zero if we can't emulate, or -EFAULT if the associated
1189 * memory access caused an access fault. Return zero on success.
1191 * There are a couple of ways to do this, either "decode" the instruction
1192 * or directly match lots of bits. In this case, matching lots of
1193 * bits is faster and easier.
1196 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
1198 u8 rT
= (instword
>> 21) & 0x1f;
1199 u8 rA
= (instword
>> 16) & 0x1f;
1200 u8 NB_RB
= (instword
>> 11) & 0x1f;
1205 /* Early out if we are an invalid form of lswx */
1206 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
1207 if ((rT
== rA
) || (rT
== NB_RB
))
1210 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
1212 switch (instword
& PPC_INST_STRING_MASK
) {
1214 case PPC_INST_STSWX
:
1216 num_bytes
= regs
->xer
& 0x7f;
1219 case PPC_INST_STSWI
:
1220 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
1226 while (num_bytes
!= 0)
1229 u32 shift
= 8 * (3 - (pos
& 0x3));
1231 /* if process is 32-bit, clear upper 32 bits of EA */
1232 if ((regs
->msr
& MSR_64BIT
) == 0)
1235 switch ((instword
& PPC_INST_STRING_MASK
)) {
1238 if (get_user(val
, (u8 __user
*)EA
))
1240 /* first time updating this reg,
1244 regs
->gpr
[rT
] |= val
<< shift
;
1246 case PPC_INST_STSWI
:
1247 case PPC_INST_STSWX
:
1248 val
= regs
->gpr
[rT
] >> shift
;
1249 if (put_user(val
, (u8 __user
*)EA
))
1253 /* move EA to next address */
1257 /* manage our position within the register */
1268 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
1273 ra
= (instword
>> 16) & 0x1f;
1274 rs
= (instword
>> 21) & 0x1f;
1276 tmp
= regs
->gpr
[rs
];
1277 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
1278 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
1279 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
1280 regs
->gpr
[ra
] = tmp
;
1285 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
1287 u8 rT
= (instword
>> 21) & 0x1f;
1288 u8 rA
= (instword
>> 16) & 0x1f;
1289 u8 rB
= (instword
>> 11) & 0x1f;
1290 u8 BC
= (instword
>> 6) & 0x1f;
1294 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
1295 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
1297 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
1302 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1303 static inline bool tm_abort_check(struct pt_regs
*regs
, int cause
)
1305 /* If we're emulating a load/store in an active transaction, we cannot
1306 * emulate it as the kernel operates in transaction suspended context.
1307 * We need to abort the transaction. This creates a persistent TM
1308 * abort so tell the user what caused it with a new code.
1310 if (MSR_TM_TRANSACTIONAL(regs
->msr
)) {
1318 static inline bool tm_abort_check(struct pt_regs
*regs
, int reason
)
1324 static int emulate_instruction(struct pt_regs
*regs
)
1329 if (!user_mode(regs
))
1331 CHECK_FULL_REGS(regs
);
1333 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
1336 /* Emulate the mfspr rD, PVR. */
1337 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
1338 PPC_WARN_EMULATED(mfpvr
, regs
);
1339 rd
= (instword
>> 21) & 0x1f;
1340 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
1344 /* Emulating the dcba insn is just a no-op. */
1345 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
1346 PPC_WARN_EMULATED(dcba
, regs
);
1350 /* Emulate the mcrxr insn. */
1351 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
1352 int shift
= (instword
>> 21) & 0x1c;
1353 unsigned long msk
= 0xf0000000UL
>> shift
;
1355 PPC_WARN_EMULATED(mcrxr
, regs
);
1356 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
1357 regs
->xer
&= ~0xf0000000UL
;
1361 /* Emulate load/store string insn. */
1362 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
1363 if (tm_abort_check(regs
,
1364 TM_CAUSE_EMULATE
| TM_CAUSE_PERSISTENT
))
1366 PPC_WARN_EMULATED(string
, regs
);
1367 return emulate_string_inst(regs
, instword
);
1370 /* Emulate the popcntb (Population Count Bytes) instruction. */
1371 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
1372 PPC_WARN_EMULATED(popcntb
, regs
);
1373 return emulate_popcntb_inst(regs
, instword
);
1376 /* Emulate isel (Integer Select) instruction */
1377 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
1378 PPC_WARN_EMULATED(isel
, regs
);
1379 return emulate_isel(regs
, instword
);
1382 /* Emulate sync instruction variants */
1383 if ((instword
& PPC_INST_SYNC_MASK
) == PPC_INST_SYNC
) {
1384 PPC_WARN_EMULATED(sync
, regs
);
1385 asm volatile("sync");
1390 /* Emulate the mfspr rD, DSCR. */
1391 if ((((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
) ==
1392 PPC_INST_MFSPR_DSCR_USER
) ||
1393 ((instword
& PPC_INST_MFSPR_DSCR_MASK
) ==
1394 PPC_INST_MFSPR_DSCR
)) &&
1395 cpu_has_feature(CPU_FTR_DSCR
)) {
1396 PPC_WARN_EMULATED(mfdscr
, regs
);
1397 rd
= (instword
>> 21) & 0x1f;
1398 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
1401 /* Emulate the mtspr DSCR, rD. */
1402 if ((((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
) ==
1403 PPC_INST_MTSPR_DSCR_USER
) ||
1404 ((instword
& PPC_INST_MTSPR_DSCR_MASK
) ==
1405 PPC_INST_MTSPR_DSCR
)) &&
1406 cpu_has_feature(CPU_FTR_DSCR
)) {
1407 PPC_WARN_EMULATED(mtdscr
, regs
);
1408 rd
= (instword
>> 21) & 0x1f;
1409 current
->thread
.dscr
= regs
->gpr
[rd
];
1410 current
->thread
.dscr_inherit
= 1;
1411 mtspr(SPRN_DSCR
, current
->thread
.dscr
);
1419 int is_valid_bugaddr(unsigned long addr
)
1421 return is_kernel_addr(addr
);
1424 #ifdef CONFIG_MATH_EMULATION
1425 static int emulate_math(struct pt_regs
*regs
)
1428 extern int do_mathemu(struct pt_regs
*regs
);
1430 ret
= do_mathemu(regs
);
1432 PPC_WARN_EMULATED(math
, regs
);
1436 emulate_single_step(regs
);
1440 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1441 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1445 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1452 static inline int emulate_math(struct pt_regs
*regs
) { return -1; }
1455 void program_check_exception(struct pt_regs
*regs
)
1457 enum ctx_state prev_state
= exception_enter();
1458 unsigned int reason
= get_reason(regs
);
1460 /* We can now get here via a FP Unavailable exception if the core
1461 * has no FPU, in that case the reason flags will be 0 */
1463 if (reason
& REASON_FP
) {
1464 /* IEEE FP exception */
1468 if (reason
& REASON_TRAP
) {
1469 unsigned long bugaddr
;
1470 /* Debugger is first in line to stop recursive faults in
1471 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1472 if (debugger_bpt(regs
))
1475 if (kprobe_handler(regs
))
1478 /* trap exception */
1479 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1483 bugaddr
= regs
->nip
;
1485 * Fixup bugaddr for BUG_ON() in real mode
1487 if (!is_kernel_addr(bugaddr
) && !(regs
->msr
& MSR_IR
))
1488 bugaddr
+= PAGE_OFFSET
;
1490 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1491 report_bug(bugaddr
, regs
) == BUG_TRAP_TYPE_WARN
) {
1495 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1498 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1499 if (reason
& REASON_TM
) {
1500 /* This is a TM "Bad Thing Exception" program check.
1502 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1503 * transition in TM states.
1504 * - A trechkpt is attempted when transactional.
1505 * - A treclaim is attempted when non transactional.
1506 * - A tend is illegally attempted.
1507 * - writing a TM SPR when transactional.
1509 * If usermode caused this, it's done something illegal and
1510 * gets a SIGILL slap on the wrist. We call it an illegal
1511 * operand to distinguish from the instruction just being bad
1512 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1513 * illegal /placement/ of a valid instruction.
1515 if (user_mode(regs
)) {
1516 _exception(SIGILL
, regs
, ILL_ILLOPN
, regs
->nip
);
1519 printk(KERN_EMERG
"Unexpected TM Bad Thing exception "
1520 "at %lx (msr 0x%lx) tm_scratch=%llx\n",
1521 regs
->nip
, regs
->msr
, get_paca()->tm_scratch
);
1522 die("Unrecoverable exception", regs
, SIGABRT
);
1528 * If we took the program check in the kernel skip down to sending a
1529 * SIGILL. The subsequent cases all relate to emulating instructions
1530 * which we should only do for userspace. We also do not want to enable
1531 * interrupts for kernel faults because that might lead to further
1532 * faults, and loose the context of the original exception.
1534 if (!user_mode(regs
))
1537 /* We restore the interrupt state now */
1538 if (!arch_irq_disabled_regs(regs
))
1541 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1542 * but there seems to be a hardware bug on the 405GP (RevD)
1543 * that means ESR is sometimes set incorrectly - either to
1544 * ESR_DST (!?) or 0. In the process of chasing this with the
1545 * hardware people - not sure if it can happen on any illegal
1546 * instruction or only on FP instructions, whether there is a
1547 * pattern to occurrences etc. -dgibson 31/Mar/2003
1549 if (!emulate_math(regs
))
1552 /* Try to emulate it if we should. */
1553 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1554 switch (emulate_instruction(regs
)) {
1557 emulate_single_step(regs
);
1560 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1566 if (reason
& REASON_PRIVILEGED
)
1567 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1569 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1572 exception_exit(prev_state
);
1574 NOKPROBE_SYMBOL(program_check_exception
);
1577 * This occurs when running in hypervisor mode on POWER6 or later
1578 * and an illegal instruction is encountered.
1580 void emulation_assist_interrupt(struct pt_regs
*regs
)
1582 regs
->msr
|= REASON_ILLEGAL
;
1583 program_check_exception(regs
);
1585 NOKPROBE_SYMBOL(emulation_assist_interrupt
);
1587 void alignment_exception(struct pt_regs
*regs
)
1589 enum ctx_state prev_state
= exception_enter();
1590 int sig
, code
, fixed
= 0;
1592 /* We restore the interrupt state now */
1593 if (!arch_irq_disabled_regs(regs
))
1596 if (tm_abort_check(regs
, TM_CAUSE_ALIGNMENT
| TM_CAUSE_PERSISTENT
))
1599 /* we don't implement logging of alignment exceptions */
1600 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1601 fixed
= fix_alignment(regs
);
1604 regs
->nip
+= 4; /* skip over emulated instruction */
1605 emulate_single_step(regs
);
1609 /* Operand address was bad */
1610 if (fixed
== -EFAULT
) {
1617 if (user_mode(regs
))
1618 _exception(sig
, regs
, code
, regs
->dar
);
1620 bad_page_fault(regs
, regs
->dar
, sig
);
1623 exception_exit(prev_state
);
1626 void StackOverflow(struct pt_regs
*regs
)
1628 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n",
1629 current
->comm
, task_pid_nr(current
), regs
->gpr
[1]);
1632 panic("kernel stack overflow");
1635 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1637 enum ctx_state prev_state
= exception_enter();
1639 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1640 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1641 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1643 exception_exit(prev_state
);
1646 void altivec_unavailable_exception(struct pt_regs
*regs
)
1648 enum ctx_state prev_state
= exception_enter();
1650 if (user_mode(regs
)) {
1651 /* A user program has executed an altivec instruction,
1652 but this kernel doesn't support altivec. */
1653 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1657 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1658 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1659 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1662 exception_exit(prev_state
);
1665 void vsx_unavailable_exception(struct pt_regs
*regs
)
1667 if (user_mode(regs
)) {
1668 /* A user program has executed an vsx instruction,
1669 but this kernel doesn't support vsx. */
1670 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1674 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1675 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1676 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1680 static void tm_unavailable(struct pt_regs
*regs
)
1682 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1683 if (user_mode(regs
)) {
1684 current
->thread
.load_tm
++;
1685 regs
->msr
|= MSR_TM
;
1687 tm_restore_sprs(¤t
->thread
);
1691 pr_emerg("Unrecoverable TM Unavailable Exception "
1692 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1693 die("Unrecoverable TM Unavailable Exception", regs
, SIGABRT
);
1696 void facility_unavailable_exception(struct pt_regs
*regs
)
1698 static char *facility_strings
[] = {
1699 [FSCR_FP_LG
] = "FPU",
1700 [FSCR_VECVSX_LG
] = "VMX/VSX",
1701 [FSCR_DSCR_LG
] = "DSCR",
1702 [FSCR_PM_LG
] = "PMU SPRs",
1703 [FSCR_BHRB_LG
] = "BHRB",
1704 [FSCR_TM_LG
] = "TM",
1705 [FSCR_EBB_LG
] = "EBB",
1706 [FSCR_TAR_LG
] = "TAR",
1707 [FSCR_MSGP_LG
] = "MSGP",
1708 [FSCR_SCV_LG
] = "SCV",
1710 char *facility
= "unknown";
1716 hv
= (TRAP(regs
) == 0xf80);
1718 value
= mfspr(SPRN_HFSCR
);
1720 value
= mfspr(SPRN_FSCR
);
1722 status
= value
>> 56;
1723 if ((hv
|| status
>= 2) &&
1724 (status
< ARRAY_SIZE(facility_strings
)) &&
1725 facility_strings
[status
])
1726 facility
= facility_strings
[status
];
1728 /* We should not have taken this interrupt in kernel */
1729 if (!user_mode(regs
)) {
1730 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1731 facility
, status
, regs
->nip
);
1732 die("Unexpected facility unavailable exception", regs
, SIGABRT
);
1735 /* We restore the interrupt state now */
1736 if (!arch_irq_disabled_regs(regs
))
1739 if (status
== FSCR_DSCR_LG
) {
1741 * User is accessing the DSCR register using the problem
1742 * state only SPR number (0x03) either through a mfspr or
1743 * a mtspr instruction. If it is a write attempt through
1744 * a mtspr, then we set the inherit bit. This also allows
1745 * the user to write or read the register directly in the
1746 * future by setting via the FSCR DSCR bit. But in case it
1747 * is a read DSCR attempt through a mfspr instruction, we
1748 * just emulate the instruction instead. This code path will
1749 * always emulate all the mfspr instructions till the user
1750 * has attempted at least one mtspr instruction. This way it
1751 * preserves the same behaviour when the user is accessing
1752 * the DSCR through privilege level only SPR number (0x11)
1753 * which is emulated through illegal instruction exception.
1754 * We always leave HFSCR DSCR set.
1756 if (get_user(instword
, (u32 __user
*)(regs
->nip
))) {
1757 pr_err("Failed to fetch the user instruction\n");
1761 /* Write into DSCR (mtspr 0x03, RS) */
1762 if ((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
)
1763 == PPC_INST_MTSPR_DSCR_USER
) {
1764 rd
= (instword
>> 21) & 0x1f;
1765 current
->thread
.dscr
= regs
->gpr
[rd
];
1766 current
->thread
.dscr_inherit
= 1;
1767 current
->thread
.fscr
|= FSCR_DSCR
;
1768 mtspr(SPRN_FSCR
, current
->thread
.fscr
);
1771 /* Read from DSCR (mfspr RT, 0x03) */
1772 if ((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
)
1773 == PPC_INST_MFSPR_DSCR_USER
) {
1774 if (emulate_instruction(regs
)) {
1775 pr_err("DSCR based mfspr emulation failed\n");
1779 emulate_single_step(regs
);
1784 if (status
== FSCR_TM_LG
) {
1786 * If we're here then the hardware is TM aware because it
1787 * generated an exception with FSRM_TM set.
1789 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1790 * told us not to do TM, or the kernel is not built with TM
1793 * If both of those things are true, then userspace can spam the
1794 * console by triggering the printk() below just by continually
1795 * doing tbegin (or any TM instruction). So in that case just
1796 * send the process a SIGILL immediately.
1798 if (!cpu_has_feature(CPU_FTR_TM
))
1801 tm_unavailable(regs
);
1805 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1806 hv
? "Hypervisor " : "", facility
, status
, regs
->nip
, regs
->msr
);
1809 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1813 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1815 void fp_unavailable_tm(struct pt_regs
*regs
)
1817 /* Note: This does not handle any kind of FP laziness. */
1819 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1820 regs
->nip
, regs
->msr
);
1822 /* We can only have got here if the task started using FP after
1823 * beginning the transaction. So, the transactional regs are just a
1824 * copy of the checkpointed ones. But, we still need to recheckpoint
1825 * as we're enabling FP for the process; it will return, abort the
1826 * transaction, and probably retry but now with FP enabled. So the
1827 * checkpointed FP registers need to be loaded.
1829 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1832 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and
1833 * then it was overwrite by the thr->fp_state by tm_reclaim_thread().
1835 * At this point, ck{fp,vr}_state contains the exact values we want to
1839 /* Enable FP for the task: */
1840 current
->thread
.load_fp
= 1;
1843 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers.
1845 tm_recheckpoint(¤t
->thread
);
1848 void altivec_unavailable_tm(struct pt_regs
*regs
)
1850 /* See the comments in fp_unavailable_tm(). This function operates
1854 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1856 regs
->nip
, regs
->msr
);
1857 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1858 current
->thread
.load_vec
= 1;
1859 tm_recheckpoint(¤t
->thread
);
1860 current
->thread
.used_vr
= 1;
1863 void vsx_unavailable_tm(struct pt_regs
*regs
)
1865 /* See the comments in fp_unavailable_tm(). This works similarly,
1866 * though we're loading both FP and VEC registers in here.
1868 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1869 * regs. Either way, set MSR_VSX.
1872 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1874 regs
->nip
, regs
->msr
);
1876 current
->thread
.used_vsr
= 1;
1878 /* This reclaims FP and/or VR regs if they're already enabled */
1879 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1881 current
->thread
.load_vec
= 1;
1882 current
->thread
.load_fp
= 1;
1884 tm_recheckpoint(¤t
->thread
);
1886 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1888 void performance_monitor_exception(struct pt_regs
*regs
)
1890 __this_cpu_inc(irq_stat
.pmu_irqs
);
1895 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1896 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1900 * Determine the cause of the debug event, clear the
1901 * event flags and send a trap to the handler. Torez
1903 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1904 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1905 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1906 current
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
1908 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
,
1911 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1912 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1913 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
,
1916 } else if (debug_status
& DBSR_IAC1
) {
1917 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
1918 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1919 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
,
1922 } else if (debug_status
& DBSR_IAC2
) {
1923 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
1924 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
,
1927 } else if (debug_status
& DBSR_IAC3
) {
1928 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
1929 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1930 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
,
1933 } else if (debug_status
& DBSR_IAC4
) {
1934 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
1935 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
,
1940 * At the point this routine was called, the MSR(DE) was turned off.
1941 * Check all other debug flags and see if that bit needs to be turned
1944 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1945 current
->thread
.debug
.dbcr1
))
1946 regs
->msr
|= MSR_DE
;
1948 /* Make sure the IDM flag is off */
1949 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1952 mtspr(SPRN_DBCR0
, current
->thread
.debug
.dbcr0
);
1955 void DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1957 current
->thread
.debug
.dbsr
= debug_status
;
1959 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1960 * on server, it stops on the target of the branch. In order to simulate
1961 * the server behaviour, we thus restart right away with a single step
1962 * instead of stopping here when hitting a BT
1964 if (debug_status
& DBSR_BT
) {
1965 regs
->msr
&= ~MSR_DE
;
1968 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1969 /* Clear the BT event */
1970 mtspr(SPRN_DBSR
, DBSR_BT
);
1972 /* Do the single step trick only when coming from userspace */
1973 if (user_mode(regs
)) {
1974 current
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
1975 current
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1976 regs
->msr
|= MSR_DE
;
1980 if (kprobe_post_handler(regs
))
1983 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1984 5, SIGTRAP
) == NOTIFY_STOP
) {
1987 if (debugger_sstep(regs
))
1989 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
1990 regs
->msr
&= ~MSR_DE
;
1992 /* Disable instruction completion */
1993 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
1994 /* Clear the instruction completion event */
1995 mtspr(SPRN_DBSR
, DBSR_IC
);
1997 if (kprobe_post_handler(regs
))
2000 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
2001 5, SIGTRAP
) == NOTIFY_STOP
) {
2005 if (debugger_sstep(regs
))
2008 if (user_mode(regs
)) {
2009 current
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
2010 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
2011 current
->thread
.debug
.dbcr1
))
2012 regs
->msr
|= MSR_DE
;
2014 /* Make sure the IDM bit is off */
2015 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
2018 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
2020 handle_debug(regs
, debug_status
);
2022 NOKPROBE_SYMBOL(DebugException
);
2023 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2025 #if !defined(CONFIG_TAU_INT)
2026 void TAUException(struct pt_regs
*regs
)
2028 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
2029 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
2031 #endif /* CONFIG_INT_TAU */
2033 #ifdef CONFIG_ALTIVEC
2034 void altivec_assist_exception(struct pt_regs
*regs
)
2038 if (!user_mode(regs
)) {
2039 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
2040 " at %lx\n", regs
->nip
);
2041 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
2044 flush_altivec_to_thread(current
);
2046 PPC_WARN_EMULATED(altivec
, regs
);
2047 err
= emulate_altivec(regs
);
2049 regs
->nip
+= 4; /* skip emulated instruction */
2050 emulate_single_step(regs
);
2054 if (err
== -EFAULT
) {
2055 /* got an error reading the instruction */
2056 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
2058 /* didn't recognize the instruction */
2059 /* XXX quick hack for now: set the non-Java bit in the VSCR */
2060 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
2061 "in %s at %lx\n", current
->comm
, regs
->nip
);
2062 current
->thread
.vr_state
.vscr
.u
[3] |= 0x10000;
2065 #endif /* CONFIG_ALTIVEC */
2067 #ifdef CONFIG_FSL_BOOKE
2068 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
2069 unsigned long error_code
)
2071 /* We treat cache locking instructions from the user
2072 * as priv ops, in the future we could try to do
2075 if (error_code
& (ESR_DLK
|ESR_ILK
))
2076 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
2079 #endif /* CONFIG_FSL_BOOKE */
2082 void SPEFloatingPointException(struct pt_regs
*regs
)
2084 extern int do_spe_mathemu(struct pt_regs
*regs
);
2085 unsigned long spefscr
;
2087 int code
= FPE_FLTUNK
;
2090 flush_spe_to_thread(current
);
2092 spefscr
= current
->thread
.spefscr
;
2093 fpexc_mode
= current
->thread
.fpexc_mode
;
2095 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
2098 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
2101 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
2103 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
2106 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
2109 err
= do_spe_mathemu(regs
);
2111 regs
->nip
+= 4; /* skip emulated instruction */
2112 emulate_single_step(regs
);
2116 if (err
== -EFAULT
) {
2117 /* got an error reading the instruction */
2118 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
2119 } else if (err
== -EINVAL
) {
2120 /* didn't recognize the instruction */
2121 printk(KERN_ERR
"unrecognized spe instruction "
2122 "in %s at %lx\n", current
->comm
, regs
->nip
);
2124 _exception(SIGFPE
, regs
, code
, regs
->nip
);
2130 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
2132 extern int speround_handler(struct pt_regs
*regs
);
2136 if (regs
->msr
& MSR_SPE
)
2137 giveup_spe(current
);
2141 err
= speround_handler(regs
);
2143 regs
->nip
+= 4; /* skip emulated instruction */
2144 emulate_single_step(regs
);
2148 if (err
== -EFAULT
) {
2149 /* got an error reading the instruction */
2150 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
2151 } else if (err
== -EINVAL
) {
2152 /* didn't recognize the instruction */
2153 printk(KERN_ERR
"unrecognized spe instruction "
2154 "in %s at %lx\n", current
->comm
, regs
->nip
);
2156 _exception(SIGFPE
, regs
, FPE_FLTUNK
, regs
->nip
);
2163 * We enter here if we get an unrecoverable exception, that is, one
2164 * that happened at a point where the RI (recoverable interrupt) bit
2165 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2166 * we therefore lost state by taking this exception.
2168 void unrecoverable_exception(struct pt_regs
*regs
)
2170 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
2171 regs
->trap
, regs
->nip
, regs
->msr
);
2172 die("Unrecoverable exception", regs
, SIGABRT
);
2174 NOKPROBE_SYMBOL(unrecoverable_exception
);
2176 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2178 * Default handler for a Watchdog exception,
2179 * spins until a reboot occurs
2181 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
2183 /* Generic WatchdogHandler, implement your own */
2184 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
2188 void WatchdogException(struct pt_regs
*regs
)
2190 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
2191 WatchdogHandler(regs
);
2196 * We enter here if we discover during exception entry that we are
2197 * running in supervisor mode with a userspace value in the stack pointer.
2199 void kernel_bad_stack(struct pt_regs
*regs
)
2201 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
2202 regs
->gpr
[1], regs
->nip
);
2203 die("Bad kernel stack pointer", regs
, SIGABRT
);
2205 NOKPROBE_SYMBOL(kernel_bad_stack
);
2207 void __init
trap_init(void)
2212 #ifdef CONFIG_PPC_EMULATED_STATS
2214 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2216 struct ppc_emulated ppc_emulated
= {
2217 #ifdef CONFIG_ALTIVEC
2218 WARN_EMULATED_SETUP(altivec
),
2220 WARN_EMULATED_SETUP(dcba
),
2221 WARN_EMULATED_SETUP(dcbz
),
2222 WARN_EMULATED_SETUP(fp_pair
),
2223 WARN_EMULATED_SETUP(isel
),
2224 WARN_EMULATED_SETUP(mcrxr
),
2225 WARN_EMULATED_SETUP(mfpvr
),
2226 WARN_EMULATED_SETUP(multiple
),
2227 WARN_EMULATED_SETUP(popcntb
),
2228 WARN_EMULATED_SETUP(spe
),
2229 WARN_EMULATED_SETUP(string
),
2230 WARN_EMULATED_SETUP(sync
),
2231 WARN_EMULATED_SETUP(unaligned
),
2232 #ifdef CONFIG_MATH_EMULATION
2233 WARN_EMULATED_SETUP(math
),
2236 WARN_EMULATED_SETUP(vsx
),
2239 WARN_EMULATED_SETUP(mfdscr
),
2240 WARN_EMULATED_SETUP(mtdscr
),
2241 WARN_EMULATED_SETUP(lq_stq
),
2242 WARN_EMULATED_SETUP(lxvw4x
),
2243 WARN_EMULATED_SETUP(lxvh8x
),
2244 WARN_EMULATED_SETUP(lxvd2x
),
2245 WARN_EMULATED_SETUP(lxvb16x
),
2249 u32 ppc_warn_emulated
;
2251 void ppc_warn_emulated_print(const char *type
)
2253 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
2257 static int __init
ppc_warn_emulated_init(void)
2259 struct dentry
*dir
, *d
;
2261 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
2263 if (!powerpc_debugfs_root
)
2266 dir
= debugfs_create_dir("emulated_instructions",
2267 powerpc_debugfs_root
);
2271 d
= debugfs_create_u32("do_warn", 0644, dir
,
2272 &ppc_warn_emulated
);
2276 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
2277 d
= debugfs_create_u32(entries
[i
].name
, 0644, dir
,
2278 (u32
*)&entries
[i
].val
.counter
);
2286 debugfs_remove_recursive(dir
);
2290 device_initcall(ppc_warn_emulated_init
);
2292 #endif /* CONFIG_PPC_EMULATED_STATS */