2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/kernel.h>
23 #include <linux/stddef.h>
24 #include <linux/unistd.h>
25 #include <linux/ptrace.h>
26 #include <linux/user.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/extable.h>
30 #include <linux/module.h> /* print_modules */
31 #include <linux/prctl.h>
32 #include <linux/delay.h>
33 #include <linux/kprobes.h>
34 #include <linux/kexec.h>
35 #include <linux/backlight.h>
36 #include <linux/bug.h>
37 #include <linux/kdebug.h>
38 #include <linux/ratelimit.h>
39 #include <linux/context_tracking.h>
41 #include <asm/emulated_ops.h>
42 #include <asm/pgtable.h>
43 #include <linux/uaccess.h>
44 #include <asm/debugfs.h>
46 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
64 #include <asm/debug.h>
65 #include <asm/asm-prototypes.h>
67 #include <sysdev/fsl_pci.h>
68 #include <asm/kprobes.h>
70 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
71 int (*__debugger
)(struct pt_regs
*regs
) __read_mostly
;
72 int (*__debugger_ipi
)(struct pt_regs
*regs
) __read_mostly
;
73 int (*__debugger_bpt
)(struct pt_regs
*regs
) __read_mostly
;
74 int (*__debugger_sstep
)(struct pt_regs
*regs
) __read_mostly
;
75 int (*__debugger_iabr_match
)(struct pt_regs
*regs
) __read_mostly
;
76 int (*__debugger_break_match
)(struct pt_regs
*regs
) __read_mostly
;
77 int (*__debugger_fault_handler
)(struct pt_regs
*regs
) __read_mostly
;
79 EXPORT_SYMBOL(__debugger
);
80 EXPORT_SYMBOL(__debugger_ipi
);
81 EXPORT_SYMBOL(__debugger_bpt
);
82 EXPORT_SYMBOL(__debugger_sstep
);
83 EXPORT_SYMBOL(__debugger_iabr_match
);
84 EXPORT_SYMBOL(__debugger_break_match
);
85 EXPORT_SYMBOL(__debugger_fault_handler
);
88 /* Transactional Memory trap debug */
90 #define TM_DEBUG(x...) printk(KERN_INFO x)
92 #define TM_DEBUG(x...) do { } while(0)
96 * Trap & Exception support
99 #ifdef CONFIG_PMAC_BACKLIGHT
100 static void pmac_backlight_unblank(void)
102 mutex_lock(&pmac_backlight_mutex
);
103 if (pmac_backlight
) {
104 struct backlight_properties
*props
;
106 props
= &pmac_backlight
->props
;
107 props
->brightness
= props
->max_brightness
;
108 props
->power
= FB_BLANK_UNBLANK
;
109 backlight_update_status(pmac_backlight
);
111 mutex_unlock(&pmac_backlight_mutex
);
114 static inline void pmac_backlight_unblank(void) { }
117 static arch_spinlock_t die_lock
= __ARCH_SPIN_LOCK_UNLOCKED
;
118 static int die_owner
= -1;
119 static unsigned int die_nest_count
;
120 static int die_counter
;
122 static unsigned long oops_begin(struct pt_regs
*regs
)
129 /* racy, but better than risking deadlock. */
130 raw_local_irq_save(flags
);
131 cpu
= smp_processor_id();
132 if (!arch_spin_trylock(&die_lock
)) {
133 if (cpu
== die_owner
)
134 /* nested oops. should stop eventually */;
136 arch_spin_lock(&die_lock
);
142 if (machine_is(powermac
))
143 pmac_backlight_unblank();
146 NOKPROBE_SYMBOL(oops_begin
);
148 static void oops_end(unsigned long flags
, struct pt_regs
*regs
,
152 add_taint(TAINT_DIE
, LOCKDEP_NOW_UNRELIABLE
);
156 if (!die_nest_count
) {
157 /* Nest count reaches zero, release the lock. */
159 arch_spin_unlock(&die_lock
);
161 raw_local_irq_restore(flags
);
163 crash_fadump(regs
, "die oops");
166 * A system reset (0x100) is a request to dump, so we always send
167 * it through the crashdump code.
169 if (kexec_should_crash(current
) || (TRAP(regs
) == 0x100)) {
173 * We aren't the primary crash CPU. We need to send it
174 * to a holding pattern to avoid it ending up in the panic
177 crash_kexec_secondary(regs
);
184 * While our oops output is serialised by a spinlock, output
185 * from panic() called below can race and corrupt it. If we
186 * know we are going to panic, delay for 1 second so we have a
187 * chance to get clean backtraces from all CPUs that are oopsing.
189 if (in_interrupt() || panic_on_oops
|| !current
->pid
||
190 is_global_init(current
)) {
191 mdelay(MSEC_PER_SEC
);
195 panic("Fatal exception in interrupt");
197 panic("Fatal exception");
200 NOKPROBE_SYMBOL(oops_end
);
202 static int __die(const char *str
, struct pt_regs
*regs
, long err
)
204 printk("Oops: %s, sig: %ld [#%d]\n", str
, err
, ++die_counter
);
205 #ifdef CONFIG_PREEMPT
209 printk("SMP NR_CPUS=%d ", NR_CPUS
);
211 if (debug_pagealloc_enabled())
212 printk("DEBUG_PAGEALLOC ");
216 printk("%s\n", ppc_md
.name
? ppc_md
.name
: "");
218 if (notify_die(DIE_OOPS
, str
, regs
, err
, 255, SIGSEGV
) == NOTIFY_STOP
)
226 NOKPROBE_SYMBOL(__die
);
228 void die(const char *str
, struct pt_regs
*regs
, long err
)
235 flags
= oops_begin(regs
);
236 if (__die(str
, regs
, err
))
238 oops_end(flags
, regs
, err
);
241 void user_single_step_siginfo(struct task_struct
*tsk
,
242 struct pt_regs
*regs
, siginfo_t
*info
)
244 memset(info
, 0, sizeof(*info
));
245 info
->si_signo
= SIGTRAP
;
246 info
->si_code
= TRAP_TRACE
;
247 info
->si_addr
= (void __user
*)regs
->nip
;
250 void _exception(int signr
, struct pt_regs
*regs
, int code
, unsigned long addr
)
253 const char fmt32
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
254 "at %08lx nip %08lx lr %08lx code %x\n";
255 const char fmt64
[] = KERN_INFO
"%s[%d]: unhandled signal %d " \
256 "at %016lx nip %016lx lr %016lx code %x\n";
258 if (!user_mode(regs
)) {
259 die("Exception in kernel mode", regs
, signr
);
263 if (show_unhandled_signals
&& unhandled_signal(current
, signr
)) {
264 printk_ratelimited(regs
->msr
& MSR_64BIT
? fmt64
: fmt32
,
265 current
->comm
, current
->pid
, signr
,
266 addr
, regs
->nip
, regs
->link
, code
);
269 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs
))
272 current
->thread
.trap_nr
= code
;
273 memset(&info
, 0, sizeof(info
));
274 info
.si_signo
= signr
;
276 info
.si_addr
= (void __user
*) addr
;
277 force_sig_info(signr
, &info
, current
);
280 void system_reset_exception(struct pt_regs
*regs
)
283 * Avoid crashes in case of nested NMI exceptions. Recoverability
284 * is determined by RI and in_nmi
286 bool nested
= in_nmi();
290 /* See if any machine dependent calls */
291 if (ppc_md
.system_reset_exception
) {
292 if (ppc_md
.system_reset_exception(regs
))
296 die("System Reset", regs
, SIGABRT
);
299 #ifdef CONFIG_PPC_BOOK3S_64
300 BUG_ON(get_paca()->in_nmi
== 0);
301 if (get_paca()->in_nmi
> 1)
302 panic("Unrecoverable nested System Reset");
304 /* Must die if the interrupt is not recoverable */
305 if (!(regs
->msr
& MSR_RI
))
306 panic("Unrecoverable System Reset");
311 /* What should we do here? We could issue a shutdown or hard reset. */
316 * This function is called in real mode. Strictly no printk's please.
318 * regs->nip and regs->msr contains srr0 and ssr1.
320 long machine_check_early(struct pt_regs
*regs
)
324 __this_cpu_inc(irq_stat
.mce_exceptions
);
326 if (cur_cpu_spec
&& cur_cpu_spec
->machine_check_early
)
327 handled
= cur_cpu_spec
->machine_check_early(regs
);
331 long hmi_exception_realmode(struct pt_regs
*regs
)
333 __this_cpu_inc(irq_stat
.hmi_exceptions
);
335 wait_for_subcore_guest_exit();
337 if (ppc_md
.hmi_exception_early
)
338 ppc_md
.hmi_exception_early(regs
);
340 wait_for_tb_resync();
348 * I/O accesses can cause machine checks on powermacs.
349 * Check if the NIP corresponds to the address of a sync
350 * instruction for which there is an entry in the exception
352 * Note that the 601 only takes a machine check on TEA
353 * (transfer error ack) signal assertion, and does not
354 * set any of the top 16 bits of SRR1.
357 static inline int check_io_access(struct pt_regs
*regs
)
360 unsigned long msr
= regs
->msr
;
361 const struct exception_table_entry
*entry
;
362 unsigned int *nip
= (unsigned int *)regs
->nip
;
364 if (((msr
& 0xffff0000) == 0 || (msr
& (0x80000 | 0x40000)))
365 && (entry
= search_exception_tables(regs
->nip
)) != NULL
) {
367 * Check that it's a sync instruction, or somewhere
368 * in the twi; isync; nop sequence that inb/inw/inl uses.
369 * As the address is in the exception table
370 * we should be able to read the instr there.
371 * For the debug message, we look at the preceding
374 if (*nip
== PPC_INST_NOP
)
376 else if (*nip
== PPC_INST_ISYNC
)
378 if (*nip
== PPC_INST_SYNC
|| (*nip
>> 26) == OP_TRAP
) {
382 rb
= (*nip
>> 11) & 0x1f;
383 printk(KERN_DEBUG
"%s bad port %lx at %p\n",
384 (*nip
& 0x100)? "OUT to": "IN from",
385 regs
->gpr
[rb
] - _IO_BASE
, nip
);
387 regs
->nip
= extable_fixup(entry
);
391 #endif /* CONFIG_PPC32 */
395 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
396 /* On 4xx, the reason for the machine check or program exception
398 #define get_reason(regs) ((regs)->dsisr)
399 #ifndef CONFIG_FSL_BOOKE
400 #define get_mc_reason(regs) ((regs)->dsisr)
402 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
404 #define REASON_FP ESR_FP
405 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
406 #define REASON_PRIVILEGED ESR_PPR
407 #define REASON_TRAP ESR_PTR
409 /* single-step stuff */
410 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
411 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
414 /* On non-4xx, the reason for the machine check or program
415 exception is in the MSR. */
416 #define get_reason(regs) ((regs)->msr)
417 #define get_mc_reason(regs) ((regs)->msr)
418 #define REASON_TM 0x200000
419 #define REASON_FP 0x100000
420 #define REASON_ILLEGAL 0x80000
421 #define REASON_PRIVILEGED 0x40000
422 #define REASON_TRAP 0x20000
424 #define single_stepping(regs) ((regs)->msr & MSR_SE)
425 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
428 #if defined(CONFIG_4xx)
429 int machine_check_4xx(struct pt_regs
*regs
)
431 unsigned long reason
= get_mc_reason(regs
);
433 if (reason
& ESR_IMCP
) {
434 printk("Instruction");
435 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
438 printk(" machine check in kernel mode.\n");
443 int machine_check_440A(struct pt_regs
*regs
)
445 unsigned long reason
= get_mc_reason(regs
);
447 printk("Machine check in kernel mode.\n");
448 if (reason
& ESR_IMCP
){
449 printk("Instruction Synchronous Machine Check exception\n");
450 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
453 u32 mcsr
= mfspr(SPRN_MCSR
);
455 printk("Instruction Read PLB Error\n");
457 printk("Data Read PLB Error\n");
459 printk("Data Write PLB Error\n");
460 if (mcsr
& MCSR_TLBP
)
461 printk("TLB Parity Error\n");
462 if (mcsr
& MCSR_ICP
){
463 flush_instruction_cache();
464 printk("I-Cache Parity Error\n");
466 if (mcsr
& MCSR_DCSP
)
467 printk("D-Cache Search Parity Error\n");
468 if (mcsr
& MCSR_DCFP
)
469 printk("D-Cache Flush Parity Error\n");
470 if (mcsr
& MCSR_IMPE
)
471 printk("Machine Check exception is imprecise\n");
474 mtspr(SPRN_MCSR
, mcsr
);
479 int machine_check_47x(struct pt_regs
*regs
)
481 unsigned long reason
= get_mc_reason(regs
);
484 printk(KERN_ERR
"Machine check in kernel mode.\n");
485 if (reason
& ESR_IMCP
) {
487 "Instruction Synchronous Machine Check exception\n");
488 mtspr(SPRN_ESR
, reason
& ~ESR_IMCP
);
491 mcsr
= mfspr(SPRN_MCSR
);
493 printk(KERN_ERR
"Instruction Read PLB Error\n");
495 printk(KERN_ERR
"Data Read PLB Error\n");
497 printk(KERN_ERR
"Data Write PLB Error\n");
498 if (mcsr
& MCSR_TLBP
)
499 printk(KERN_ERR
"TLB Parity Error\n");
500 if (mcsr
& MCSR_ICP
) {
501 flush_instruction_cache();
502 printk(KERN_ERR
"I-Cache Parity Error\n");
504 if (mcsr
& MCSR_DCSP
)
505 printk(KERN_ERR
"D-Cache Search Parity Error\n");
506 if (mcsr
& PPC47x_MCSR_GPR
)
507 printk(KERN_ERR
"GPR Parity Error\n");
508 if (mcsr
& PPC47x_MCSR_FPR
)
509 printk(KERN_ERR
"FPR Parity Error\n");
510 if (mcsr
& PPC47x_MCSR_IPR
)
511 printk(KERN_ERR
"Machine Check exception is imprecise\n");
514 mtspr(SPRN_MCSR
, mcsr
);
518 #elif defined(CONFIG_E500)
519 int machine_check_e500mc(struct pt_regs
*regs
)
521 unsigned long mcsr
= mfspr(SPRN_MCSR
);
522 unsigned long reason
= mcsr
;
525 if (reason
& MCSR_LD
) {
526 recoverable
= fsl_rio_mcheck_exception(regs
);
527 if (recoverable
== 1)
531 printk("Machine check in kernel mode.\n");
532 printk("Caused by (from MCSR=%lx): ", reason
);
534 if (reason
& MCSR_MCP
)
535 printk("Machine Check Signal\n");
537 if (reason
& MCSR_ICPERR
) {
538 printk("Instruction Cache Parity Error\n");
541 * This is recoverable by invalidating the i-cache.
543 mtspr(SPRN_L1CSR1
, mfspr(SPRN_L1CSR1
) | L1CSR1_ICFI
);
544 while (mfspr(SPRN_L1CSR1
) & L1CSR1_ICFI
)
548 * This will generally be accompanied by an instruction
549 * fetch error report -- only treat MCSR_IF as fatal
550 * if it wasn't due to an L1 parity error.
555 if (reason
& MCSR_DCPERR_MC
) {
556 printk("Data Cache Parity Error\n");
559 * In write shadow mode we auto-recover from the error, but it
560 * may still get logged and cause a machine check. We should
561 * only treat the non-write shadow case as non-recoverable.
563 if (!(mfspr(SPRN_L1CSR2
) & L1CSR2_DCWS
))
567 if (reason
& MCSR_L2MMU_MHIT
) {
568 printk("Hit on multiple TLB entries\n");
572 if (reason
& MCSR_NMI
)
573 printk("Non-maskable interrupt\n");
575 if (reason
& MCSR_IF
) {
576 printk("Instruction Fetch Error Report\n");
580 if (reason
& MCSR_LD
) {
581 printk("Load Error Report\n");
585 if (reason
& MCSR_ST
) {
586 printk("Store Error Report\n");
590 if (reason
& MCSR_LDG
) {
591 printk("Guarded Load Error Report\n");
595 if (reason
& MCSR_TLBSYNC
)
596 printk("Simultaneous tlbsync operations\n");
598 if (reason
& MCSR_BSL2_ERR
) {
599 printk("Level 2 Cache Error\n");
603 if (reason
& MCSR_MAV
) {
606 addr
= mfspr(SPRN_MCAR
);
607 addr
|= (u64
)mfspr(SPRN_MCARU
) << 32;
609 printk("Machine Check %s Address: %#llx\n",
610 reason
& MCSR_MEA
? "Effective" : "Physical", addr
);
614 mtspr(SPRN_MCSR
, mcsr
);
615 return mfspr(SPRN_MCSR
) == 0 && recoverable
;
618 int machine_check_e500(struct pt_regs
*regs
)
620 unsigned long reason
= get_mc_reason(regs
);
622 if (reason
& MCSR_BUS_RBERR
) {
623 if (fsl_rio_mcheck_exception(regs
))
625 if (fsl_pci_mcheck_exception(regs
))
629 printk("Machine check in kernel mode.\n");
630 printk("Caused by (from MCSR=%lx): ", reason
);
632 if (reason
& MCSR_MCP
)
633 printk("Machine Check Signal\n");
634 if (reason
& MCSR_ICPERR
)
635 printk("Instruction Cache Parity Error\n");
636 if (reason
& MCSR_DCP_PERR
)
637 printk("Data Cache Push Parity Error\n");
638 if (reason
& MCSR_DCPERR
)
639 printk("Data Cache Parity Error\n");
640 if (reason
& MCSR_BUS_IAERR
)
641 printk("Bus - Instruction Address Error\n");
642 if (reason
& MCSR_BUS_RAERR
)
643 printk("Bus - Read Address Error\n");
644 if (reason
& MCSR_BUS_WAERR
)
645 printk("Bus - Write Address Error\n");
646 if (reason
& MCSR_BUS_IBERR
)
647 printk("Bus - Instruction Data Error\n");
648 if (reason
& MCSR_BUS_RBERR
)
649 printk("Bus - Read Data Bus Error\n");
650 if (reason
& MCSR_BUS_WBERR
)
651 printk("Bus - Write Data Bus Error\n");
652 if (reason
& MCSR_BUS_IPERR
)
653 printk("Bus - Instruction Parity Error\n");
654 if (reason
& MCSR_BUS_RPERR
)
655 printk("Bus - Read Parity Error\n");
660 int machine_check_generic(struct pt_regs
*regs
)
664 #elif defined(CONFIG_E200)
665 int machine_check_e200(struct pt_regs
*regs
)
667 unsigned long reason
= get_mc_reason(regs
);
669 printk("Machine check in kernel mode.\n");
670 printk("Caused by (from MCSR=%lx): ", reason
);
672 if (reason
& MCSR_MCP
)
673 printk("Machine Check Signal\n");
674 if (reason
& MCSR_CP_PERR
)
675 printk("Cache Push Parity Error\n");
676 if (reason
& MCSR_CPERR
)
677 printk("Cache Parity Error\n");
678 if (reason
& MCSR_EXCP_ERR
)
679 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
680 if (reason
& MCSR_BUS_IRERR
)
681 printk("Bus - Read Bus Error on instruction fetch\n");
682 if (reason
& MCSR_BUS_DRERR
)
683 printk("Bus - Read Bus Error on data load\n");
684 if (reason
& MCSR_BUS_WRERR
)
685 printk("Bus - Write Bus Error on buffered store or cache line push\n");
689 #elif defined(CONFIG_PPC_8xx)
690 int machine_check_8xx(struct pt_regs
*regs
)
692 unsigned long reason
= get_mc_reason(regs
);
694 pr_err("Machine check in kernel mode.\n");
695 pr_err("Caused by (from SRR1=%lx): ", reason
);
696 if (reason
& 0x40000000)
697 pr_err("Fetch error at address %lx\n", regs
->nip
);
699 pr_err("Data access error at address %lx\n", regs
->dar
);
702 /* the qspan pci read routines can cause machine checks -- Cort
704 * yuck !!! that totally needs to go away ! There are better ways
705 * to deal with that than having a wart in the mcheck handler.
708 bad_page_fault(regs
, regs
->dar
, SIGBUS
);
715 int machine_check_generic(struct pt_regs
*regs
)
717 unsigned long reason
= get_mc_reason(regs
);
719 printk("Machine check in kernel mode.\n");
720 printk("Caused by (from SRR1=%lx): ", reason
);
721 switch (reason
& 0x601F0000) {
723 printk("Machine check signal\n");
725 case 0: /* for 601 */
727 case 0x140000: /* 7450 MSS error and TEA */
728 printk("Transfer error ack signal\n");
731 printk("Data parity error signal\n");
734 printk("Address parity error signal\n");
737 printk("L1 Data Cache error\n");
740 printk("L1 Instruction Cache error\n");
743 printk("L2 data cache parity error\n");
746 printk("Unknown values in msr\n");
750 #endif /* everything else */
752 void machine_check_exception(struct pt_regs
*regs
)
754 enum ctx_state prev_state
= exception_enter();
757 __this_cpu_inc(irq_stat
.mce_exceptions
);
759 add_taint(TAINT_MACHINE_CHECK
, LOCKDEP_NOW_UNRELIABLE
);
761 /* See if any machine dependent calls. In theory, we would want
762 * to call the CPU first, and call the ppc_md. one if the CPU
763 * one returns a positive number. However there is existing code
764 * that assumes the board gets a first chance, so let's keep it
765 * that way for now and fix things later. --BenH.
767 if (ppc_md
.machine_check_exception
)
768 recover
= ppc_md
.machine_check_exception(regs
);
769 else if (cur_cpu_spec
->machine_check
)
770 recover
= cur_cpu_spec
->machine_check(regs
);
775 if (debugger_fault_handler(regs
))
778 if (check_io_access(regs
))
781 die("Machine check", regs
, SIGBUS
);
783 /* Must die if the interrupt is not recoverable */
784 if (!(regs
->msr
& MSR_RI
))
785 panic("Unrecoverable Machine check");
788 exception_exit(prev_state
);
791 void SMIException(struct pt_regs
*regs
)
793 die("System Management Interrupt", regs
, SIGABRT
);
796 void handle_hmi_exception(struct pt_regs
*regs
)
798 struct pt_regs
*old_regs
;
800 old_regs
= set_irq_regs(regs
);
803 if (ppc_md
.handle_hmi_exception
)
804 ppc_md
.handle_hmi_exception(regs
);
807 set_irq_regs(old_regs
);
810 void unknown_exception(struct pt_regs
*regs
)
812 enum ctx_state prev_state
= exception_enter();
814 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
815 regs
->nip
, regs
->msr
, regs
->trap
);
817 _exception(SIGTRAP
, regs
, 0, 0);
819 exception_exit(prev_state
);
822 void instruction_breakpoint_exception(struct pt_regs
*regs
)
824 enum ctx_state prev_state
= exception_enter();
826 if (notify_die(DIE_IABR_MATCH
, "iabr_match", regs
, 5,
827 5, SIGTRAP
) == NOTIFY_STOP
)
829 if (debugger_iabr_match(regs
))
831 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
834 exception_exit(prev_state
);
837 void RunModeException(struct pt_regs
*regs
)
839 _exception(SIGTRAP
, regs
, 0, 0);
842 void single_step_exception(struct pt_regs
*regs
)
844 enum ctx_state prev_state
= exception_enter();
846 clear_single_step(regs
);
848 if (kprobe_post_handler(regs
))
851 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
852 5, SIGTRAP
) == NOTIFY_STOP
)
854 if (debugger_sstep(regs
))
857 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
860 exception_exit(prev_state
);
862 NOKPROBE_SYMBOL(single_step_exception
);
865 * After we have successfully emulated an instruction, we have to
866 * check if the instruction was being single-stepped, and if so,
867 * pretend we got a single-step exception. This was pointed out
868 * by Kumar Gala. -- paulus
870 static void emulate_single_step(struct pt_regs
*regs
)
872 if (single_stepping(regs
))
873 single_step_exception(regs
);
876 static inline int __parse_fpscr(unsigned long fpscr
)
880 /* Invalid operation */
881 if ((fpscr
& FPSCR_VE
) && (fpscr
& FPSCR_VX
))
885 else if ((fpscr
& FPSCR_OE
) && (fpscr
& FPSCR_OX
))
889 else if ((fpscr
& FPSCR_UE
) && (fpscr
& FPSCR_UX
))
893 else if ((fpscr
& FPSCR_ZE
) && (fpscr
& FPSCR_ZX
))
897 else if ((fpscr
& FPSCR_XE
) && (fpscr
& FPSCR_XX
))
903 static void parse_fpe(struct pt_regs
*regs
)
907 flush_fp_to_thread(current
);
909 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
911 _exception(SIGFPE
, regs
, code
, regs
->nip
);
915 * Illegal instruction emulation support. Originally written to
916 * provide the PVR to user applications using the mfspr rd, PVR.
917 * Return non-zero if we can't emulate, or -EFAULT if the associated
918 * memory access caused an access fault. Return zero on success.
920 * There are a couple of ways to do this, either "decode" the instruction
921 * or directly match lots of bits. In this case, matching lots of
922 * bits is faster and easier.
925 static int emulate_string_inst(struct pt_regs
*regs
, u32 instword
)
927 u8 rT
= (instword
>> 21) & 0x1f;
928 u8 rA
= (instword
>> 16) & 0x1f;
929 u8 NB_RB
= (instword
>> 11) & 0x1f;
934 /* Early out if we are an invalid form of lswx */
935 if ((instword
& PPC_INST_STRING_MASK
) == PPC_INST_LSWX
)
936 if ((rT
== rA
) || (rT
== NB_RB
))
939 EA
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
941 switch (instword
& PPC_INST_STRING_MASK
) {
945 num_bytes
= regs
->xer
& 0x7f;
949 num_bytes
= (NB_RB
== 0) ? 32 : NB_RB
;
955 while (num_bytes
!= 0)
958 u32 shift
= 8 * (3 - (pos
& 0x3));
960 /* if process is 32-bit, clear upper 32 bits of EA */
961 if ((regs
->msr
& MSR_64BIT
) == 0)
964 switch ((instword
& PPC_INST_STRING_MASK
)) {
967 if (get_user(val
, (u8 __user
*)EA
))
969 /* first time updating this reg,
973 regs
->gpr
[rT
] |= val
<< shift
;
977 val
= regs
->gpr
[rT
] >> shift
;
978 if (put_user(val
, (u8 __user
*)EA
))
982 /* move EA to next address */
986 /* manage our position within the register */
997 static int emulate_popcntb_inst(struct pt_regs
*regs
, u32 instword
)
1002 ra
= (instword
>> 16) & 0x1f;
1003 rs
= (instword
>> 21) & 0x1f;
1005 tmp
= regs
->gpr
[rs
];
1006 tmp
= tmp
- ((tmp
>> 1) & 0x5555555555555555ULL
);
1007 tmp
= (tmp
& 0x3333333333333333ULL
) + ((tmp
>> 2) & 0x3333333333333333ULL
);
1008 tmp
= (tmp
+ (tmp
>> 4)) & 0x0f0f0f0f0f0f0f0fULL
;
1009 regs
->gpr
[ra
] = tmp
;
1014 static int emulate_isel(struct pt_regs
*regs
, u32 instword
)
1016 u8 rT
= (instword
>> 21) & 0x1f;
1017 u8 rA
= (instword
>> 16) & 0x1f;
1018 u8 rB
= (instword
>> 11) & 0x1f;
1019 u8 BC
= (instword
>> 6) & 0x1f;
1023 tmp
= (rA
== 0) ? 0 : regs
->gpr
[rA
];
1024 bit
= (regs
->ccr
>> (31 - BC
)) & 0x1;
1026 regs
->gpr
[rT
] = bit
? tmp
: regs
->gpr
[rB
];
1031 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1032 static inline bool tm_abort_check(struct pt_regs
*regs
, int cause
)
1034 /* If we're emulating a load/store in an active transaction, we cannot
1035 * emulate it as the kernel operates in transaction suspended context.
1036 * We need to abort the transaction. This creates a persistent TM
1037 * abort so tell the user what caused it with a new code.
1039 if (MSR_TM_TRANSACTIONAL(regs
->msr
)) {
1047 static inline bool tm_abort_check(struct pt_regs
*regs
, int reason
)
1053 static int emulate_instruction(struct pt_regs
*regs
)
1058 if (!user_mode(regs
))
1060 CHECK_FULL_REGS(regs
);
1062 if (get_user(instword
, (u32 __user
*)(regs
->nip
)))
1065 /* Emulate the mfspr rD, PVR. */
1066 if ((instword
& PPC_INST_MFSPR_PVR_MASK
) == PPC_INST_MFSPR_PVR
) {
1067 PPC_WARN_EMULATED(mfpvr
, regs
);
1068 rd
= (instword
>> 21) & 0x1f;
1069 regs
->gpr
[rd
] = mfspr(SPRN_PVR
);
1073 /* Emulating the dcba insn is just a no-op. */
1074 if ((instword
& PPC_INST_DCBA_MASK
) == PPC_INST_DCBA
) {
1075 PPC_WARN_EMULATED(dcba
, regs
);
1079 /* Emulate the mcrxr insn. */
1080 if ((instword
& PPC_INST_MCRXR_MASK
) == PPC_INST_MCRXR
) {
1081 int shift
= (instword
>> 21) & 0x1c;
1082 unsigned long msk
= 0xf0000000UL
>> shift
;
1084 PPC_WARN_EMULATED(mcrxr
, regs
);
1085 regs
->ccr
= (regs
->ccr
& ~msk
) | ((regs
->xer
>> shift
) & msk
);
1086 regs
->xer
&= ~0xf0000000UL
;
1090 /* Emulate load/store string insn. */
1091 if ((instword
& PPC_INST_STRING_GEN_MASK
) == PPC_INST_STRING
) {
1092 if (tm_abort_check(regs
,
1093 TM_CAUSE_EMULATE
| TM_CAUSE_PERSISTENT
))
1095 PPC_WARN_EMULATED(string
, regs
);
1096 return emulate_string_inst(regs
, instword
);
1099 /* Emulate the popcntb (Population Count Bytes) instruction. */
1100 if ((instword
& PPC_INST_POPCNTB_MASK
) == PPC_INST_POPCNTB
) {
1101 PPC_WARN_EMULATED(popcntb
, regs
);
1102 return emulate_popcntb_inst(regs
, instword
);
1105 /* Emulate isel (Integer Select) instruction */
1106 if ((instword
& PPC_INST_ISEL_MASK
) == PPC_INST_ISEL
) {
1107 PPC_WARN_EMULATED(isel
, regs
);
1108 return emulate_isel(regs
, instword
);
1111 /* Emulate sync instruction variants */
1112 if ((instword
& PPC_INST_SYNC_MASK
) == PPC_INST_SYNC
) {
1113 PPC_WARN_EMULATED(sync
, regs
);
1114 asm volatile("sync");
1119 /* Emulate the mfspr rD, DSCR. */
1120 if ((((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
) ==
1121 PPC_INST_MFSPR_DSCR_USER
) ||
1122 ((instword
& PPC_INST_MFSPR_DSCR_MASK
) ==
1123 PPC_INST_MFSPR_DSCR
)) &&
1124 cpu_has_feature(CPU_FTR_DSCR
)) {
1125 PPC_WARN_EMULATED(mfdscr
, regs
);
1126 rd
= (instword
>> 21) & 0x1f;
1127 regs
->gpr
[rd
] = mfspr(SPRN_DSCR
);
1130 /* Emulate the mtspr DSCR, rD. */
1131 if ((((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
) ==
1132 PPC_INST_MTSPR_DSCR_USER
) ||
1133 ((instword
& PPC_INST_MTSPR_DSCR_MASK
) ==
1134 PPC_INST_MTSPR_DSCR
)) &&
1135 cpu_has_feature(CPU_FTR_DSCR
)) {
1136 PPC_WARN_EMULATED(mtdscr
, regs
);
1137 rd
= (instword
>> 21) & 0x1f;
1138 current
->thread
.dscr
= regs
->gpr
[rd
];
1139 current
->thread
.dscr_inherit
= 1;
1140 mtspr(SPRN_DSCR
, current
->thread
.dscr
);
1148 int is_valid_bugaddr(unsigned long addr
)
1150 return is_kernel_addr(addr
);
1153 #ifdef CONFIG_MATH_EMULATION
1154 static int emulate_math(struct pt_regs
*regs
)
1157 extern int do_mathemu(struct pt_regs
*regs
);
1159 ret
= do_mathemu(regs
);
1161 PPC_WARN_EMULATED(math
, regs
);
1165 emulate_single_step(regs
);
1169 code
= __parse_fpscr(current
->thread
.fp_state
.fpscr
);
1170 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1174 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1181 static inline int emulate_math(struct pt_regs
*regs
) { return -1; }
1184 void program_check_exception(struct pt_regs
*regs
)
1186 enum ctx_state prev_state
= exception_enter();
1187 unsigned int reason
= get_reason(regs
);
1189 /* We can now get here via a FP Unavailable exception if the core
1190 * has no FPU, in that case the reason flags will be 0 */
1192 if (reason
& REASON_FP
) {
1193 /* IEEE FP exception */
1197 if (reason
& REASON_TRAP
) {
1198 unsigned long bugaddr
;
1199 /* Debugger is first in line to stop recursive faults in
1200 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1201 if (debugger_bpt(regs
))
1204 if (kprobe_handler(regs
))
1207 /* trap exception */
1208 if (notify_die(DIE_BPT
, "breakpoint", regs
, 5, 5, SIGTRAP
)
1212 bugaddr
= regs
->nip
;
1214 * Fixup bugaddr for BUG_ON() in real mode
1216 if (!is_kernel_addr(bugaddr
) && !(regs
->msr
& MSR_IR
))
1217 bugaddr
+= PAGE_OFFSET
;
1219 if (!(regs
->msr
& MSR_PR
) && /* not user-mode */
1220 report_bug(bugaddr
, regs
) == BUG_TRAP_TYPE_WARN
) {
1224 _exception(SIGTRAP
, regs
, TRAP_BRKPT
, regs
->nip
);
1227 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1228 if (reason
& REASON_TM
) {
1229 /* This is a TM "Bad Thing Exception" program check.
1231 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1232 * transition in TM states.
1233 * - A trechkpt is attempted when transactional.
1234 * - A treclaim is attempted when non transactional.
1235 * - A tend is illegally attempted.
1236 * - writing a TM SPR when transactional.
1238 if (!user_mode(regs
) &&
1239 report_bug(regs
->nip
, regs
) == BUG_TRAP_TYPE_WARN
) {
1243 /* If usermode caused this, it's done something illegal and
1244 * gets a SIGILL slap on the wrist. We call it an illegal
1245 * operand to distinguish from the instruction just being bad
1246 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1247 * illegal /placement/ of a valid instruction.
1249 if (user_mode(regs
)) {
1250 _exception(SIGILL
, regs
, ILL_ILLOPN
, regs
->nip
);
1253 printk(KERN_EMERG
"Unexpected TM Bad Thing exception "
1254 "at %lx (msr 0x%x)\n", regs
->nip
, reason
);
1255 die("Unrecoverable exception", regs
, SIGABRT
);
1261 * If we took the program check in the kernel skip down to sending a
1262 * SIGILL. The subsequent cases all relate to emulating instructions
1263 * which we should only do for userspace. We also do not want to enable
1264 * interrupts for kernel faults because that might lead to further
1265 * faults, and loose the context of the original exception.
1267 if (!user_mode(regs
))
1270 /* We restore the interrupt state now */
1271 if (!arch_irq_disabled_regs(regs
))
1274 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1275 * but there seems to be a hardware bug on the 405GP (RevD)
1276 * that means ESR is sometimes set incorrectly - either to
1277 * ESR_DST (!?) or 0. In the process of chasing this with the
1278 * hardware people - not sure if it can happen on any illegal
1279 * instruction or only on FP instructions, whether there is a
1280 * pattern to occurrences etc. -dgibson 31/Mar/2003
1282 if (!emulate_math(regs
))
1285 /* Try to emulate it if we should. */
1286 if (reason
& (REASON_ILLEGAL
| REASON_PRIVILEGED
)) {
1287 switch (emulate_instruction(regs
)) {
1290 emulate_single_step(regs
);
1293 _exception(SIGSEGV
, regs
, SEGV_MAPERR
, regs
->nip
);
1299 if (reason
& REASON_PRIVILEGED
)
1300 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1302 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1305 exception_exit(prev_state
);
1307 NOKPROBE_SYMBOL(program_check_exception
);
1310 * This occurs when running in hypervisor mode on POWER6 or later
1311 * and an illegal instruction is encountered.
1313 void emulation_assist_interrupt(struct pt_regs
*regs
)
1315 regs
->msr
|= REASON_ILLEGAL
;
1316 program_check_exception(regs
);
1318 NOKPROBE_SYMBOL(emulation_assist_interrupt
);
1320 void alignment_exception(struct pt_regs
*regs
)
1322 enum ctx_state prev_state
= exception_enter();
1323 int sig
, code
, fixed
= 0;
1325 /* We restore the interrupt state now */
1326 if (!arch_irq_disabled_regs(regs
))
1329 if (tm_abort_check(regs
, TM_CAUSE_ALIGNMENT
| TM_CAUSE_PERSISTENT
))
1332 /* we don't implement logging of alignment exceptions */
1333 if (!(current
->thread
.align_ctl
& PR_UNALIGN_SIGBUS
))
1334 fixed
= fix_alignment(regs
);
1337 regs
->nip
+= 4; /* skip over emulated instruction */
1338 emulate_single_step(regs
);
1342 /* Operand address was bad */
1343 if (fixed
== -EFAULT
) {
1350 if (user_mode(regs
))
1351 _exception(sig
, regs
, code
, regs
->dar
);
1353 bad_page_fault(regs
, regs
->dar
, sig
);
1356 exception_exit(prev_state
);
1359 void slb_miss_bad_addr(struct pt_regs
*regs
)
1361 enum ctx_state prev_state
= exception_enter();
1363 if (user_mode(regs
))
1364 _exception(SIGSEGV
, regs
, SEGV_BNDERR
, regs
->dar
);
1366 bad_page_fault(regs
, regs
->dar
, SIGSEGV
);
1368 exception_exit(prev_state
);
1371 void StackOverflow(struct pt_regs
*regs
)
1373 printk(KERN_CRIT
"Kernel stack overflow in process %p, r1=%lx\n",
1374 current
, regs
->gpr
[1]);
1377 panic("kernel stack overflow");
1380 void nonrecoverable_exception(struct pt_regs
*regs
)
1382 printk(KERN_ERR
"Non-recoverable exception at PC=%lx MSR=%lx\n",
1383 regs
->nip
, regs
->msr
);
1385 die("nonrecoverable exception", regs
, SIGKILL
);
1388 void kernel_fp_unavailable_exception(struct pt_regs
*regs
)
1390 enum ctx_state prev_state
= exception_enter();
1392 printk(KERN_EMERG
"Unrecoverable FP Unavailable Exception "
1393 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1394 die("Unrecoverable FP Unavailable Exception", regs
, SIGABRT
);
1396 exception_exit(prev_state
);
1399 void altivec_unavailable_exception(struct pt_regs
*regs
)
1401 enum ctx_state prev_state
= exception_enter();
1403 if (user_mode(regs
)) {
1404 /* A user program has executed an altivec instruction,
1405 but this kernel doesn't support altivec. */
1406 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1410 printk(KERN_EMERG
"Unrecoverable VMX/Altivec Unavailable Exception "
1411 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1412 die("Unrecoverable VMX/Altivec Unavailable Exception", regs
, SIGABRT
);
1415 exception_exit(prev_state
);
1418 void vsx_unavailable_exception(struct pt_regs
*regs
)
1420 if (user_mode(regs
)) {
1421 /* A user program has executed an vsx instruction,
1422 but this kernel doesn't support vsx. */
1423 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1427 printk(KERN_EMERG
"Unrecoverable VSX Unavailable Exception "
1428 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1429 die("Unrecoverable VSX Unavailable Exception", regs
, SIGABRT
);
1433 static void tm_unavailable(struct pt_regs
*regs
)
1435 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1436 if (user_mode(regs
)) {
1437 current
->thread
.load_tm
++;
1438 regs
->msr
|= MSR_TM
;
1440 tm_restore_sprs(¤t
->thread
);
1444 pr_emerg("Unrecoverable TM Unavailable Exception "
1445 "%lx at %lx\n", regs
->trap
, regs
->nip
);
1446 die("Unrecoverable TM Unavailable Exception", regs
, SIGABRT
);
1449 void facility_unavailable_exception(struct pt_regs
*regs
)
1451 static char *facility_strings
[] = {
1452 [FSCR_FP_LG
] = "FPU",
1453 [FSCR_VECVSX_LG
] = "VMX/VSX",
1454 [FSCR_DSCR_LG
] = "DSCR",
1455 [FSCR_PM_LG
] = "PMU SPRs",
1456 [FSCR_BHRB_LG
] = "BHRB",
1457 [FSCR_TM_LG
] = "TM",
1458 [FSCR_EBB_LG
] = "EBB",
1459 [FSCR_TAR_LG
] = "TAR",
1460 [FSCR_MSGP_LG
] = "MSGP",
1461 [FSCR_SCV_LG
] = "SCV",
1463 char *facility
= "unknown";
1469 hv
= (regs
->trap
== 0xf80);
1471 value
= mfspr(SPRN_HFSCR
);
1473 value
= mfspr(SPRN_FSCR
);
1475 status
= value
>> 56;
1476 if (status
== FSCR_DSCR_LG
) {
1478 * User is accessing the DSCR register using the problem
1479 * state only SPR number (0x03) either through a mfspr or
1480 * a mtspr instruction. If it is a write attempt through
1481 * a mtspr, then we set the inherit bit. This also allows
1482 * the user to write or read the register directly in the
1483 * future by setting via the FSCR DSCR bit. But in case it
1484 * is a read DSCR attempt through a mfspr instruction, we
1485 * just emulate the instruction instead. This code path will
1486 * always emulate all the mfspr instructions till the user
1487 * has attempted at least one mtspr instruction. This way it
1488 * preserves the same behaviour when the user is accessing
1489 * the DSCR through privilege level only SPR number (0x11)
1490 * which is emulated through illegal instruction exception.
1491 * We always leave HFSCR DSCR set.
1493 if (get_user(instword
, (u32 __user
*)(regs
->nip
))) {
1494 pr_err("Failed to fetch the user instruction\n");
1498 /* Write into DSCR (mtspr 0x03, RS) */
1499 if ((instword
& PPC_INST_MTSPR_DSCR_USER_MASK
)
1500 == PPC_INST_MTSPR_DSCR_USER
) {
1501 rd
= (instword
>> 21) & 0x1f;
1502 current
->thread
.dscr
= regs
->gpr
[rd
];
1503 current
->thread
.dscr_inherit
= 1;
1504 current
->thread
.fscr
|= FSCR_DSCR
;
1505 mtspr(SPRN_FSCR
, current
->thread
.fscr
);
1508 /* Read from DSCR (mfspr RT, 0x03) */
1509 if ((instword
& PPC_INST_MFSPR_DSCR_USER_MASK
)
1510 == PPC_INST_MFSPR_DSCR_USER
) {
1511 if (emulate_instruction(regs
)) {
1512 pr_err("DSCR based mfspr emulation failed\n");
1516 emulate_single_step(regs
);
1521 if (status
== FSCR_TM_LG
) {
1523 * If we're here then the hardware is TM aware because it
1524 * generated an exception with FSRM_TM set.
1526 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1527 * told us not to do TM, or the kernel is not built with TM
1530 * If both of those things are true, then userspace can spam the
1531 * console by triggering the printk() below just by continually
1532 * doing tbegin (or any TM instruction). So in that case just
1533 * send the process a SIGILL immediately.
1535 if (!cpu_has_feature(CPU_FTR_TM
))
1538 tm_unavailable(regs
);
1542 if ((hv
|| status
>= 2) &&
1543 (status
< ARRAY_SIZE(facility_strings
)) &&
1544 facility_strings
[status
])
1545 facility
= facility_strings
[status
];
1547 /* We restore the interrupt state now */
1548 if (!arch_irq_disabled_regs(regs
))
1551 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1552 hv
? "Hypervisor " : "", facility
, status
, regs
->nip
, regs
->msr
);
1555 if (user_mode(regs
)) {
1556 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1560 die("Unexpected facility unavailable exception", regs
, SIGABRT
);
1564 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1566 void fp_unavailable_tm(struct pt_regs
*regs
)
1568 /* Note: This does not handle any kind of FP laziness. */
1570 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1571 regs
->nip
, regs
->msr
);
1573 /* We can only have got here if the task started using FP after
1574 * beginning the transaction. So, the transactional regs are just a
1575 * copy of the checkpointed ones. But, we still need to recheckpoint
1576 * as we're enabling FP for the process; it will return, abort the
1577 * transaction, and probably retry but now with FP enabled. So the
1578 * checkpointed FP registers need to be loaded.
1580 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1581 /* Reclaim didn't save out any FPRs to transact_fprs. */
1583 /* Enable FP for the task: */
1584 regs
->msr
|= (MSR_FP
| current
->thread
.fpexc_mode
);
1586 /* This loads and recheckpoints the FP registers from
1587 * thread.fpr[]. They will remain in registers after the
1588 * checkpoint so we don't need to reload them after.
1589 * If VMX is in use, the VRs now hold checkpointed values,
1590 * so we don't want to load the VRs from the thread_struct.
1592 tm_recheckpoint(¤t
->thread
, MSR_FP
);
1594 /* If VMX is in use, get the transactional values back */
1595 if (regs
->msr
& MSR_VEC
) {
1596 msr_check_and_set(MSR_VEC
);
1597 load_vr_state(¤t
->thread
.vr_state
);
1598 /* At this point all the VSX state is loaded, so enable it */
1599 regs
->msr
|= MSR_VSX
;
1603 void altivec_unavailable_tm(struct pt_regs
*regs
)
1605 /* See the comments in fp_unavailable_tm(). This function operates
1609 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1611 regs
->nip
, regs
->msr
);
1612 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1613 regs
->msr
|= MSR_VEC
;
1614 tm_recheckpoint(¤t
->thread
, MSR_VEC
);
1615 current
->thread
.used_vr
= 1;
1617 if (regs
->msr
& MSR_FP
) {
1618 msr_check_and_set(MSR_FP
);
1619 load_fp_state(¤t
->thread
.fp_state
);
1620 regs
->msr
|= MSR_VSX
;
1624 void vsx_unavailable_tm(struct pt_regs
*regs
)
1626 unsigned long orig_msr
= regs
->msr
;
1628 /* See the comments in fp_unavailable_tm(). This works similarly,
1629 * though we're loading both FP and VEC registers in here.
1631 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1632 * regs. Either way, set MSR_VSX.
1635 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1637 regs
->nip
, regs
->msr
);
1639 current
->thread
.used_vsr
= 1;
1641 /* If FP and VMX are already loaded, we have all the state we need */
1642 if ((orig_msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
)) {
1643 regs
->msr
|= MSR_VSX
;
1647 /* This reclaims FP and/or VR regs if they're already enabled */
1648 tm_reclaim_current(TM_CAUSE_FAC_UNAV
);
1650 regs
->msr
|= MSR_VEC
| MSR_FP
| current
->thread
.fpexc_mode
|
1653 /* This loads & recheckpoints FP and VRs; but we have
1654 * to be sure not to overwrite previously-valid state.
1656 tm_recheckpoint(¤t
->thread
, regs
->msr
& ~orig_msr
);
1658 msr_check_and_set(orig_msr
& (MSR_FP
| MSR_VEC
));
1660 if (orig_msr
& MSR_FP
)
1661 load_fp_state(¤t
->thread
.fp_state
);
1662 if (orig_msr
& MSR_VEC
)
1663 load_vr_state(¤t
->thread
.vr_state
);
1665 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1667 void performance_monitor_exception(struct pt_regs
*regs
)
1669 __this_cpu_inc(irq_stat
.pmu_irqs
);
1675 void SoftwareEmulation(struct pt_regs
*regs
)
1677 CHECK_FULL_REGS(regs
);
1679 if (!user_mode(regs
)) {
1681 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1685 if (!emulate_math(regs
))
1688 _exception(SIGILL
, regs
, ILL_ILLOPC
, regs
->nip
);
1690 #endif /* CONFIG_8xx */
1692 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1693 static void handle_debug(struct pt_regs
*regs
, unsigned long debug_status
)
1697 * Determine the cause of the debug event, clear the
1698 * event flags and send a trap to the handler. Torez
1700 if (debug_status
& (DBSR_DAC1R
| DBSR_DAC1W
)) {
1701 dbcr_dac(current
) &= ~(DBCR_DAC1R
| DBCR_DAC1W
);
1702 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1703 current
->thread
.debug
.dbcr2
&= ~DBCR2_DAC12MODE
;
1705 do_send_trap(regs
, mfspr(SPRN_DAC1
), debug_status
, TRAP_HWBKPT
,
1708 } else if (debug_status
& (DBSR_DAC2R
| DBSR_DAC2W
)) {
1709 dbcr_dac(current
) &= ~(DBCR_DAC2R
| DBCR_DAC2W
);
1710 do_send_trap(regs
, mfspr(SPRN_DAC2
), debug_status
, TRAP_HWBKPT
,
1713 } else if (debug_status
& DBSR_IAC1
) {
1714 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC1
;
1715 dbcr_iac_range(current
) &= ~DBCR_IAC12MODE
;
1716 do_send_trap(regs
, mfspr(SPRN_IAC1
), debug_status
, TRAP_HWBKPT
,
1719 } else if (debug_status
& DBSR_IAC2
) {
1720 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC2
;
1721 do_send_trap(regs
, mfspr(SPRN_IAC2
), debug_status
, TRAP_HWBKPT
,
1724 } else if (debug_status
& DBSR_IAC3
) {
1725 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC3
;
1726 dbcr_iac_range(current
) &= ~DBCR_IAC34MODE
;
1727 do_send_trap(regs
, mfspr(SPRN_IAC3
), debug_status
, TRAP_HWBKPT
,
1730 } else if (debug_status
& DBSR_IAC4
) {
1731 current
->thread
.debug
.dbcr0
&= ~DBCR0_IAC4
;
1732 do_send_trap(regs
, mfspr(SPRN_IAC4
), debug_status
, TRAP_HWBKPT
,
1737 * At the point this routine was called, the MSR(DE) was turned off.
1738 * Check all other debug flags and see if that bit needs to be turned
1741 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1742 current
->thread
.debug
.dbcr1
))
1743 regs
->msr
|= MSR_DE
;
1745 /* Make sure the IDM flag is off */
1746 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1749 mtspr(SPRN_DBCR0
, current
->thread
.debug
.dbcr0
);
1752 void DebugException(struct pt_regs
*regs
, unsigned long debug_status
)
1754 current
->thread
.debug
.dbsr
= debug_status
;
1756 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1757 * on server, it stops on the target of the branch. In order to simulate
1758 * the server behaviour, we thus restart right away with a single step
1759 * instead of stopping here when hitting a BT
1761 if (debug_status
& DBSR_BT
) {
1762 regs
->msr
&= ~MSR_DE
;
1765 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_BT
);
1766 /* Clear the BT event */
1767 mtspr(SPRN_DBSR
, DBSR_BT
);
1769 /* Do the single step trick only when coming from userspace */
1770 if (user_mode(regs
)) {
1771 current
->thread
.debug
.dbcr0
&= ~DBCR0_BT
;
1772 current
->thread
.debug
.dbcr0
|= DBCR0_IDM
| DBCR0_IC
;
1773 regs
->msr
|= MSR_DE
;
1777 if (kprobe_post_handler(regs
))
1780 if (notify_die(DIE_SSTEP
, "block_step", regs
, 5,
1781 5, SIGTRAP
) == NOTIFY_STOP
) {
1784 if (debugger_sstep(regs
))
1786 } else if (debug_status
& DBSR_IC
) { /* Instruction complete */
1787 regs
->msr
&= ~MSR_DE
;
1789 /* Disable instruction completion */
1790 mtspr(SPRN_DBCR0
, mfspr(SPRN_DBCR0
) & ~DBCR0_IC
);
1791 /* Clear the instruction completion event */
1792 mtspr(SPRN_DBSR
, DBSR_IC
);
1794 if (kprobe_post_handler(regs
))
1797 if (notify_die(DIE_SSTEP
, "single_step", regs
, 5,
1798 5, SIGTRAP
) == NOTIFY_STOP
) {
1802 if (debugger_sstep(regs
))
1805 if (user_mode(regs
)) {
1806 current
->thread
.debug
.dbcr0
&= ~DBCR0_IC
;
1807 if (DBCR_ACTIVE_EVENTS(current
->thread
.debug
.dbcr0
,
1808 current
->thread
.debug
.dbcr1
))
1809 regs
->msr
|= MSR_DE
;
1811 /* Make sure the IDM bit is off */
1812 current
->thread
.debug
.dbcr0
&= ~DBCR0_IDM
;
1815 _exception(SIGTRAP
, regs
, TRAP_TRACE
, regs
->nip
);
1817 handle_debug(regs
, debug_status
);
1819 NOKPROBE_SYMBOL(DebugException
);
1820 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1822 #if !defined(CONFIG_TAU_INT)
1823 void TAUException(struct pt_regs
*regs
)
1825 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1826 regs
->nip
, regs
->msr
, regs
->trap
, print_tainted());
1828 #endif /* CONFIG_INT_TAU */
1830 #ifdef CONFIG_ALTIVEC
1831 void altivec_assist_exception(struct pt_regs
*regs
)
1835 if (!user_mode(regs
)) {
1836 printk(KERN_EMERG
"VMX/Altivec assist exception in kernel mode"
1837 " at %lx\n", regs
->nip
);
1838 die("Kernel VMX/Altivec assist exception", regs
, SIGILL
);
1841 flush_altivec_to_thread(current
);
1843 PPC_WARN_EMULATED(altivec
, regs
);
1844 err
= emulate_altivec(regs
);
1846 regs
->nip
+= 4; /* skip emulated instruction */
1847 emulate_single_step(regs
);
1851 if (err
== -EFAULT
) {
1852 /* got an error reading the instruction */
1853 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1855 /* didn't recognize the instruction */
1856 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1857 printk_ratelimited(KERN_ERR
"Unrecognized altivec instruction "
1858 "in %s at %lx\n", current
->comm
, regs
->nip
);
1859 current
->thread
.vr_state
.vscr
.u
[3] |= 0x10000;
1862 #endif /* CONFIG_ALTIVEC */
1864 #ifdef CONFIG_FSL_BOOKE
1865 void CacheLockingException(struct pt_regs
*regs
, unsigned long address
,
1866 unsigned long error_code
)
1868 /* We treat cache locking instructions from the user
1869 * as priv ops, in the future we could try to do
1872 if (error_code
& (ESR_DLK
|ESR_ILK
))
1873 _exception(SIGILL
, regs
, ILL_PRVOPC
, regs
->nip
);
1876 #endif /* CONFIG_FSL_BOOKE */
1879 void SPEFloatingPointException(struct pt_regs
*regs
)
1881 extern int do_spe_mathemu(struct pt_regs
*regs
);
1882 unsigned long spefscr
;
1887 flush_spe_to_thread(current
);
1889 spefscr
= current
->thread
.spefscr
;
1890 fpexc_mode
= current
->thread
.fpexc_mode
;
1892 if ((spefscr
& SPEFSCR_FOVF
) && (fpexc_mode
& PR_FP_EXC_OVF
)) {
1895 else if ((spefscr
& SPEFSCR_FUNF
) && (fpexc_mode
& PR_FP_EXC_UND
)) {
1898 else if ((spefscr
& SPEFSCR_FDBZ
) && (fpexc_mode
& PR_FP_EXC_DIV
))
1900 else if ((spefscr
& SPEFSCR_FINV
) && (fpexc_mode
& PR_FP_EXC_INV
)) {
1903 else if ((spefscr
& (SPEFSCR_FG
| SPEFSCR_FX
)) && (fpexc_mode
& PR_FP_EXC_RES
))
1906 err
= do_spe_mathemu(regs
);
1908 regs
->nip
+= 4; /* skip emulated instruction */
1909 emulate_single_step(regs
);
1913 if (err
== -EFAULT
) {
1914 /* got an error reading the instruction */
1915 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1916 } else if (err
== -EINVAL
) {
1917 /* didn't recognize the instruction */
1918 printk(KERN_ERR
"unrecognized spe instruction "
1919 "in %s at %lx\n", current
->comm
, regs
->nip
);
1921 _exception(SIGFPE
, regs
, code
, regs
->nip
);
1927 void SPEFloatingPointRoundException(struct pt_regs
*regs
)
1929 extern int speround_handler(struct pt_regs
*regs
);
1933 if (regs
->msr
& MSR_SPE
)
1934 giveup_spe(current
);
1938 err
= speround_handler(regs
);
1940 regs
->nip
+= 4; /* skip emulated instruction */
1941 emulate_single_step(regs
);
1945 if (err
== -EFAULT
) {
1946 /* got an error reading the instruction */
1947 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, regs
->nip
);
1948 } else if (err
== -EINVAL
) {
1949 /* didn't recognize the instruction */
1950 printk(KERN_ERR
"unrecognized spe instruction "
1951 "in %s at %lx\n", current
->comm
, regs
->nip
);
1953 _exception(SIGFPE
, regs
, 0, regs
->nip
);
1960 * We enter here if we get an unrecoverable exception, that is, one
1961 * that happened at a point where the RI (recoverable interrupt) bit
1962 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1963 * we therefore lost state by taking this exception.
1965 void unrecoverable_exception(struct pt_regs
*regs
)
1967 printk(KERN_EMERG
"Unrecoverable exception %lx at %lx\n",
1968 regs
->trap
, regs
->nip
);
1969 die("Unrecoverable exception", regs
, SIGABRT
);
1972 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1974 * Default handler for a Watchdog exception,
1975 * spins until a reboot occurs
1977 void __attribute__ ((weak
)) WatchdogHandler(struct pt_regs
*regs
)
1979 /* Generic WatchdogHandler, implement your own */
1980 mtspr(SPRN_TCR
, mfspr(SPRN_TCR
)&(~TCR_WIE
));
1984 void WatchdogException(struct pt_regs
*regs
)
1986 printk (KERN_EMERG
"PowerPC Book-E Watchdog Exception\n");
1987 WatchdogHandler(regs
);
1992 * We enter here if we discover during exception entry that we are
1993 * running in supervisor mode with a userspace value in the stack pointer.
1995 void kernel_bad_stack(struct pt_regs
*regs
)
1997 printk(KERN_EMERG
"Bad kernel stack pointer %lx at %lx\n",
1998 regs
->gpr
[1], regs
->nip
);
1999 die("Bad kernel stack pointer", regs
, SIGABRT
);
2002 void __init
trap_init(void)
2007 #ifdef CONFIG_PPC_EMULATED_STATS
2009 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2011 struct ppc_emulated ppc_emulated
= {
2012 #ifdef CONFIG_ALTIVEC
2013 WARN_EMULATED_SETUP(altivec
),
2015 WARN_EMULATED_SETUP(dcba
),
2016 WARN_EMULATED_SETUP(dcbz
),
2017 WARN_EMULATED_SETUP(fp_pair
),
2018 WARN_EMULATED_SETUP(isel
),
2019 WARN_EMULATED_SETUP(mcrxr
),
2020 WARN_EMULATED_SETUP(mfpvr
),
2021 WARN_EMULATED_SETUP(multiple
),
2022 WARN_EMULATED_SETUP(popcntb
),
2023 WARN_EMULATED_SETUP(spe
),
2024 WARN_EMULATED_SETUP(string
),
2025 WARN_EMULATED_SETUP(sync
),
2026 WARN_EMULATED_SETUP(unaligned
),
2027 #ifdef CONFIG_MATH_EMULATION
2028 WARN_EMULATED_SETUP(math
),
2031 WARN_EMULATED_SETUP(vsx
),
2034 WARN_EMULATED_SETUP(mfdscr
),
2035 WARN_EMULATED_SETUP(mtdscr
),
2036 WARN_EMULATED_SETUP(lq_stq
),
2040 u32 ppc_warn_emulated
;
2042 void ppc_warn_emulated_print(const char *type
)
2044 pr_warn_ratelimited("%s used emulated %s instruction\n", current
->comm
,
2048 static int __init
ppc_warn_emulated_init(void)
2050 struct dentry
*dir
, *d
;
2052 struct ppc_emulated_entry
*entries
= (void *)&ppc_emulated
;
2054 if (!powerpc_debugfs_root
)
2057 dir
= debugfs_create_dir("emulated_instructions",
2058 powerpc_debugfs_root
);
2062 d
= debugfs_create_u32("do_warn", S_IRUGO
| S_IWUSR
, dir
,
2063 &ppc_warn_emulated
);
2067 for (i
= 0; i
< sizeof(ppc_emulated
)/sizeof(*entries
); i
++) {
2068 d
= debugfs_create_u32(entries
[i
].name
, S_IRUGO
| S_IWUSR
, dir
,
2069 (u32
*)&entries
[i
].val
.counter
);
2077 debugfs_remove_recursive(dir
);
2081 device_initcall(ppc_warn_emulated_init
);
2083 #endif /* CONFIG_PPC_EMULATED_STATS */