2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
33 #include <asm/xive-regs.h>
35 /* Sign-extend HDEC if not on POWER9 */
36 #define EXTEND_HDEC(reg) \
39 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
41 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
43 /* Values in HSTATE_NAPPING(r13) */
44 #define NAPPING_CEDE 1
45 #define NAPPING_NOVCPU 2
48 * Call kvmppc_hv_entry in real mode.
49 * Must be called with interrupts hard-disabled.
53 * LR = return address to continue at after eventually re-enabling MMU
55 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
57 std r0, PPC_LR_STKOFF(r1)
60 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
65 mtmsrd r0,1 /* clear RI in MSR */
71 ld r4, HSTATE_KVM_VCPU(r13)
74 /* Back from guest - restore host state and return to caller */
77 /* Restore host DABR and DABRX */
78 ld r5,HSTATE_DABR(r13)
82 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
85 ld r3,PACA_SPRG_VDSO(r13)
86 mtspr SPRN_SPRG_VDSO_WRITE,r3
88 /* Reload the host's PMU registers */
89 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
90 lbz r4, LPPACA_PMCINUSE(r3)
92 beq 23f /* skip if not */
94 ld r3, HSTATE_MMCR0(r13)
95 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
98 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
99 lwz r3, HSTATE_PMC1(r13)
100 lwz r4, HSTATE_PMC2(r13)
101 lwz r5, HSTATE_PMC3(r13)
102 lwz r6, HSTATE_PMC4(r13)
103 lwz r8, HSTATE_PMC5(r13)
104 lwz r9, HSTATE_PMC6(r13)
111 ld r3, HSTATE_MMCR0(r13)
112 ld r4, HSTATE_MMCR1(r13)
113 ld r5, HSTATE_MMCRA(r13)
114 ld r6, HSTATE_SIAR(r13)
115 ld r7, HSTATE_SDAR(r13)
121 ld r8, HSTATE_MMCR2(r13)
122 ld r9, HSTATE_SIER(r13)
125 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
131 * Reload DEC. HDEC interrupts were disabled when
132 * we reloaded the host's LPCR value.
134 ld r3, HSTATE_DECEXP(r13)
139 /* hwthread_req may have got set by cede or no vcpu, so clear it */
141 stb r0, HSTATE_HWTHREAD_REQ(r13)
144 * For external and machine check interrupts, we need
145 * to call the Linux handler to process the interrupt.
146 * We do that by jumping to absolute address 0x500 for
147 * external interrupts, or the machine_check_fwnmi label
148 * for machine checks (since firmware might have patched
149 * the vector area at 0x200). The [h]rfid at the end of the
150 * handler will return to the book3s_hv_interrupts.S code.
151 * For other interrupts we do the rfid to get back
152 * to the book3s_hv_interrupts.S code here.
154 ld r8, 112+PPC_LR_STKOFF(r1)
156 ld r7, HSTATE_HOST_MSR(r13)
159 * If we came back from the guest via a relocation-on interrupt,
160 * we will be in virtual mode at this point, which makes it a
161 * little easier to get back to the caller.
164 andi. r0, r0, MSR_IR /* in real mode? */
167 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
168 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
170 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
171 beq 15f /* Invoke the H_DOORBELL handler */
172 cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI
173 beq cr2, 14f /* HMI check */
175 /* RFI into the highmem handler, or branch to interrupt handler */
179 mtmsrd r6, 1 /* Clear RI in MSR */
182 beq cr1, 13f /* machine check */
185 /* On POWER7, we have external interrupts set to use HSRR0/1 */
186 11: mtspr SPRN_HSRR0, r8
190 13: b machine_check_fwnmi
192 14: mtspr SPRN_HSRR0, r8
194 b hmi_exception_after_realmode
196 15: mtspr SPRN_HSRR0, r8
200 /* Virtual-mode return - can't get here for HMI or machine check */
202 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
204 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
206 andi. r0, r7, MSR_EE /* were interrupts hard-enabled? */
208 mtmsrd r7, 1 /* if so then re-enable them */
212 16: mtspr SPRN_HSRR0, r8 /* jump to reloc-on external vector */
214 b exc_virt_0x4500_hardware_interrupt
216 17: mtspr SPRN_HSRR0, r8
218 b exc_virt_0x4e80_h_doorbell
220 kvmppc_primary_no_guest:
221 /* We handle this much like a ceded vcpu */
222 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
223 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
224 /* HDEC value came from DEC in the first place, it will fit */
228 * Make sure the primary has finished the MMU switch.
229 * We should never get here on a secondary thread, but
230 * check it for robustness' sake.
232 ld r5, HSTATE_KVM_VCORE(r13)
233 65: lbz r0, VCORE_IN_GUEST(r5)
240 /* set our bit in napping_threads */
241 ld r5, HSTATE_KVM_VCORE(r13)
242 lbz r7, HSTATE_PTID(r13)
245 addi r6, r5, VCORE_NAPPING_THREADS
250 /* order napping_threads update vs testing entry_exit_map */
253 lwz r7, VCORE_ENTRY_EXIT(r5)
255 bge kvm_novcpu_exit /* another thread already exiting */
256 li r3, NAPPING_NOVCPU
257 stb r3, HSTATE_NAPPING(r13)
259 li r3, 0 /* Don't wake on privileged (OS) doorbell */
264 * Entered from kvm_start_guest if kvm_hstate.napping is set
270 ld r1, HSTATE_HOST_R1(r13)
271 ld r5, HSTATE_KVM_VCORE(r13)
273 stb r0, HSTATE_NAPPING(r13)
275 /* check the wake reason */
276 bl kvmppc_check_wake_reason
279 * Restore volatile registers since we could have called
280 * a C routine in kvmppc_check_wake_reason.
283 ld r5, HSTATE_KVM_VCORE(r13)
285 /* see if any other thread is already exiting */
286 lwz r0, VCORE_ENTRY_EXIT(r5)
290 /* clear our bit in napping_threads */
291 lbz r7, HSTATE_PTID(r13)
294 addi r6, r5, VCORE_NAPPING_THREADS
300 /* See if the wake reason means we need to exit */
304 /* See if our timeslice has expired (HDEC is negative) */
307 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
311 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
312 ld r4, HSTATE_KVM_VCPU(r13)
314 beq kvmppc_primary_no_guest
316 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
317 addi r3, r4, VCPU_TB_RMENTRY
318 bl kvmhv_start_timing
323 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
324 ld r4, HSTATE_KVM_VCPU(r13)
327 addi r3, r4, VCPU_TB_RMEXIT
328 bl kvmhv_accumulate_time
332 bl kvmhv_commence_exit
335 b kvmhv_switch_to_host
338 * We come in here when wakened from nap mode.
339 * Relocation is off and most register values are lost.
340 * r13 points to the PACA.
342 .globl kvm_start_guest
345 /* Set runlatch bit the minute you wake up from nap */
352 li r0,KVM_HWTHREAD_IN_KVM
353 stb r0,HSTATE_HWTHREAD_STATE(r13)
355 /* NV GPR values from power7_idle() will no longer be valid */
357 stb r0,PACA_NAPSTATELOST(r13)
359 /* were we napping due to cede? */
360 lbz r0,HSTATE_NAPPING(r13)
361 cmpwi r0,NAPPING_CEDE
363 cmpwi r0,NAPPING_NOVCPU
364 beq kvm_novcpu_wakeup
366 ld r1,PACAEMERGSP(r13)
367 subi r1,r1,STACK_FRAME_OVERHEAD
370 * We weren't napping due to cede, so this must be a secondary
371 * thread being woken up to run a guest, or being woken up due
372 * to a stray IPI. (Or due to some machine check or hypervisor
373 * maintenance interrupt while the core is in KVM.)
376 /* Check the wake reason in SRR1 to see why we got here */
377 bl kvmppc_check_wake_reason
379 * kvmppc_check_wake_reason could invoke a C routine, but we
380 * have no volatile registers to restore when we return.
386 /* get vcore pointer, NULL if we have nothing to run */
387 ld r5,HSTATE_KVM_VCORE(r13)
389 /* if we have no vcore to run, go back to sleep */
392 kvm_secondary_got_guest:
394 /* Set HSTATE_DSCR(r13) to something sensible */
395 ld r6, PACA_DSCR_DEFAULT(r13)
396 std r6, HSTATE_DSCR(r13)
398 /* On thread 0 of a subcore, set HDEC to max */
399 lbz r4, HSTATE_PTID(r13)
402 LOAD_REG_ADDR(r6, decrementer_max)
405 /* and set per-LPAR registers, if doing dynamic micro-threading */
406 ld r6, HSTATE_SPLIT_MODE(r13)
409 ld r0, KVM_SPLIT_RPR(r6)
411 ld r0, KVM_SPLIT_PMMAR(r6)
413 ld r0, KVM_SPLIT_LDBAR(r6)
417 /* Order load of vcpu after load of vcore */
419 ld r4, HSTATE_KVM_VCPU(r13)
422 /* Back from the guest, go back to nap */
423 /* Clear our vcpu and vcore pointers so we don't come back in early */
425 std r0, HSTATE_KVM_VCPU(r13)
427 * Once we clear HSTATE_KVM_VCORE(r13), the code in
428 * kvmppc_run_core() is going to assume that all our vcpu
429 * state is visible in memory. This lwsync makes sure
433 std r0, HSTATE_KVM_VCORE(r13)
436 * All secondaries exiting guest will fall through this path.
437 * Before proceeding, just check for HMI interrupt and
438 * invoke opal hmi handler. By now we are sure that the
439 * primary thread on this core/subcore has already made partition
440 * switch/TB resync and we are good to call opal hmi handler.
442 cmpwi r12, BOOK3S_INTERRUPT_HMI
445 li r3,0 /* NULL argument */
446 bl hmi_exception_realmode
448 * At this point we have finished executing in the guest.
449 * We need to wait for hwthread_req to become zero, since
450 * we may not turn on the MMU while hwthread_req is non-zero.
451 * While waiting we also need to check if we get given a vcpu to run.
454 lbz r3, HSTATE_HWTHREAD_REQ(r13)
458 li r0, KVM_HWTHREAD_IN_KERNEL
459 stb r0, HSTATE_HWTHREAD_STATE(r13)
460 /* need to recheck hwthread_req after a barrier, to avoid race */
462 lbz r3, HSTATE_HWTHREAD_REQ(r13)
466 * We jump to pnv_wakeup_loss, which will return to the caller
467 * of power7_nap in the powernv cpu offline loop. The value we
468 * put in r3 becomes the return value for power7_nap.
472 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
478 ld r5, HSTATE_KVM_VCORE(r13)
481 ld r3, HSTATE_SPLIT_MODE(r13)
484 lbz r0, KVM_SPLIT_DO_NAP(r3)
490 b kvm_secondary_got_guest
492 54: li r0, KVM_HWTHREAD_IN_KVM
493 stb r0, HSTATE_HWTHREAD_STATE(r13)
497 * Here the primary thread is trying to return the core to
498 * whole-core mode, so we need to nap.
502 * When secondaries are napping in kvm_unsplit_nap() with
503 * hwthread_req = 1, HMI goes ignored even though subcores are
504 * already exited the guest. Hence HMI keeps waking up secondaries
505 * from nap in a loop and secondaries always go back to nap since
506 * no vcore is assigned to them. This makes impossible for primary
507 * thread to get hold of secondary threads resulting into a soft
508 * lockup in KVM path.
510 * Let us check if HMI is pending and handle it before we go to nap.
512 cmpwi r12, BOOK3S_INTERRUPT_HMI
514 li r3, 0 /* NULL argument */
515 bl hmi_exception_realmode
518 * Ensure that secondary doesn't nap when it has
519 * its vcore pointer set.
521 sync /* matches smp_mb() before setting split_info.do_nap */
522 ld r0, HSTATE_KVM_VCORE(r13)
525 /* clear any pending message */
527 lis r6, (PPC_DBELL_SERVER << (63-36))@h
529 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
530 /* Set kvm_split_mode.napped[tid] = 1 */
531 ld r3, HSTATE_SPLIT_MODE(r13)
533 lhz r4, PACAPACAINDEX(r13)
534 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
535 addi r4, r4, KVM_SPLIT_NAPPED
537 /* Check the do_nap flag again after setting napped[] */
539 lbz r0, KVM_SPLIT_DO_NAP(r3)
542 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
544 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
551 /******************************************************************************
555 *****************************************************************************/
557 /* Stack frame offsets */
558 #define STACK_SLOT_TID (112-16)
559 #define STACK_SLOT_PSSCR (112-24)
560 #define STACK_SLOT_PID (112-32)
561 #define STACK_SLOT_IAMR (112-40)
563 .global kvmppc_hv_entry
568 * R4 = vcpu pointer (or NULL)
573 * all other volatile GPRS = free
574 * Does not preserve non-volatile GPRs or CR fields
577 std r0, PPC_LR_STKOFF(r1)
580 /* Save R1 in the PACA */
581 std r1, HSTATE_HOST_R1(r13)
583 li r6, KVM_GUEST_MODE_HOST_HV
584 stb r6, HSTATE_IN_GUEST(r13)
586 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
587 /* Store initial timestamp */
590 addi r3, r4, VCPU_TB_RMENTRY
591 bl kvmhv_start_timing
595 /* Use cr7 as an indication of radix mode */
596 ld r5, HSTATE_KVM_VCORE(r13)
597 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
598 lbz r0, KVM_RADIX(r9)
601 /* Clear out SLB if hash */
609 * POWER7/POWER8 host -> guest partition switch code.
610 * We don't have to lock against concurrent tlbies,
611 * but we do have to coordinate across hardware threads.
613 /* Set bit in entry map iff exit map is zero. */
615 lbz r6, HSTATE_PTID(r13)
617 addi r8, r5, VCORE_ENTRY_EXIT
619 cmpwi r3, 0x100 /* any threads starting to exit? */
620 bge secondary_too_late /* if so we're too late to the party */
625 /* Primary thread switches to guest partition. */
631 li r0,LPID_RSVD /* switch to reserved LPID */
634 mtspr SPRN_SDR1,r6 /* switch to partition page table */
635 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
639 /* See if we need to flush the TLB */
640 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
643 * On POWER9, individual threads can come in here, but the
644 * TLB is shared between the 4 threads in a core, hence
645 * invalidating on one thread invalidates for all.
646 * Thus we make all 4 threads use the same bit here.
649 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
650 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
651 srdi r6,r6,6 /* doubleword number */
652 sldi r6,r6,3 /* address offset */
654 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
660 /* Flush the TLB of any entries for this LPID */
661 lwz r0,KVM_TLB_SETS(r9)
663 li r7,0x800 /* IS field = 0b10 */
665 li r0,0 /* RS for P9 version of tlbiel */
667 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
671 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */
675 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
680 /* Add timebase offset onto timebase */
681 22: ld r8,VCORE_TB_OFFSET(r5)
684 mftb r6 /* current host timebase */
686 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
687 mftb r7 /* check if lower 24 bits overflowed */
692 addis r8,r8,0x100 /* if so, increment upper 40 bits */
695 /* Load guest PCR value to select appropriate compat mode */
696 37: ld r7, VCORE_PCR(r5)
703 /* DPDES and VTB are shared between threads */
704 ld r8, VCORE_DPDES(r5)
708 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
710 /* Mark the subcore state as inside guest */
711 bl kvmppc_subcore_enter_guest
713 ld r5, HSTATE_KVM_VCORE(r13)
714 ld r4, HSTATE_KVM_VCPU(r13)
716 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
718 /* Do we have a guest vcpu to run? */
720 beq kvmppc_primary_no_guest
723 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
724 lwz r5,VCPU_SLB_MAX(r4)
729 1: ld r8,VCPU_SLB_E(r6)
732 addi r6,r6,VCPU_SLB_SIZE
735 /* Increment yield count if they have a VPA */
739 li r6, LPPACA_YIELDCOUNT
744 stb r6, VCPU_VPA_DIRTY(r4)
747 /* Save purr/spurr */
750 std r5,HSTATE_PURR(r13)
751 std r6,HSTATE_SPURR(r13)
757 /* Save host values of some registers */
763 std r5, STACK_SLOT_TID(r1)
764 std r6, STACK_SLOT_PSSCR(r1)
765 std r7, STACK_SLOT_PID(r1)
766 std r8, STACK_SLOT_IAMR(r1)
767 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
770 /* Set partition DABR */
771 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
772 lwz r5,VCPU_DABRX(r4)
777 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
779 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
782 END_FTR_SECTION_IFSET(CPU_FTR_TM)
785 /* Load guest PMU registers */
786 /* R4 is live here (vcpu pointer) */
788 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
789 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
793 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
796 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
797 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
798 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
799 lwz r6, VCPU_PMC + 8(r4)
800 lwz r7, VCPU_PMC + 12(r4)
801 lwz r8, VCPU_PMC + 16(r4)
802 lwz r9, VCPU_PMC + 20(r4)
810 ld r5, VCPU_MMCR + 8(r4)
811 ld r6, VCPU_MMCR + 16(r4)
819 ld r5, VCPU_MMCR + 24(r4)
823 BEGIN_FTR_SECTION_NESTED(96)
824 lwz r7, VCPU_PMC + 24(r4)
825 lwz r8, VCPU_PMC + 28(r4)
826 ld r9, VCPU_MMCR + 32(r4)
830 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
831 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
835 /* Load up FP, VMX and VSX registers */
838 ld r14, VCPU_GPR(R14)(r4)
839 ld r15, VCPU_GPR(R15)(r4)
840 ld r16, VCPU_GPR(R16)(r4)
841 ld r17, VCPU_GPR(R17)(r4)
842 ld r18, VCPU_GPR(R18)(r4)
843 ld r19, VCPU_GPR(R19)(r4)
844 ld r20, VCPU_GPR(R20)(r4)
845 ld r21, VCPU_GPR(R21)(r4)
846 ld r22, VCPU_GPR(R22)(r4)
847 ld r23, VCPU_GPR(R23)(r4)
848 ld r24, VCPU_GPR(R24)(r4)
849 ld r25, VCPU_GPR(R25)(r4)
850 ld r26, VCPU_GPR(R26)(r4)
851 ld r27, VCPU_GPR(R27)(r4)
852 ld r28, VCPU_GPR(R28)(r4)
853 ld r29, VCPU_GPR(R29)(r4)
854 ld r30, VCPU_GPR(R30)(r4)
855 ld r31, VCPU_GPR(R31)(r4)
857 /* Switch DSCR to guest value */
862 /* Skip next section on POWER7 */
864 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
865 /* Load up POWER8-specific registers */
867 lwz r6, VCPU_PSPB(r4)
873 ld r6, VCPU_DAWRX(r4)
874 ld r7, VCPU_CIABR(r4)
881 ld r8, VCPU_EBBHR(r4)
884 ld r5, VCPU_EBBRR(r4)
885 ld r6, VCPU_BESCR(r4)
886 lwz r7, VCPU_GUEST_PID(r4)
894 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
896 /* POWER8-only registers */
897 ld r5, VCPU_TCSCR(r4)
899 ld r7, VCPU_CSIGR(r4)
906 /* POWER9-only registers */
908 ld r6, VCPU_PSSCR(r4)
909 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
912 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
916 * Set the decrementer to the guest decrementer.
918 ld r8,VCPU_DEC_EXPIRES(r4)
919 /* r8 is a host timebase value here, convert to guest TB */
920 ld r5,HSTATE_KVM_VCORE(r13)
921 ld r6,VCORE_TB_OFFSET(r5)
928 ld r5, VCPU_SPRG0(r4)
929 ld r6, VCPU_SPRG1(r4)
930 ld r7, VCPU_SPRG2(r4)
931 ld r8, VCPU_SPRG3(r4)
937 /* Load up DAR and DSISR */
939 lwz r6, VCPU_DSISR(r4)
943 /* Restore AMR and UAMOR, set AMOR to all 1s */
951 /* Restore state of CTRL run bit; assume 1 on entry */
959 /* Secondary threads wait for primary to have done partition switch */
960 ld r5, HSTATE_KVM_VCORE(r13)
961 lbz r6, HSTATE_PTID(r13)
964 lbz r0, VCORE_IN_GUEST(r5)
968 20: lwz r3, VCORE_ENTRY_EXIT(r5)
971 lbz r0, VCORE_IN_GUEST(r5)
981 /* Check if HDEC expires soon */
984 cmpdi r3, 512 /* 1 microsecond */
987 #ifdef CONFIG_KVM_XICS
988 /* We are entering the guest on that thread, push VCPU to XIVE */
989 ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
992 ld r11, VCPU_XIVE_SAVED_STATE(r4)
996 lwz r11, VCPU_XIVE_CAM_WORD(r4)
997 li r9, TM_QW1_OS + TM_WORD2
1000 stw r9, VCPU_XIVE_PUSHED(r4)
1002 #endif /* CONFIG_KVM_XICS */
1004 deliver_guest_interrupt:
1011 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
1013 ld r11, VCPU_MSR(r4)
1014 ld r6, VCPU_SRR0(r4)
1015 ld r7, VCPU_SRR1(r4)
1019 /* r11 = vcpu->arch.msr & ~MSR_HV */
1020 rldicl r11, r11, 63 - MSR_HV_LG, 1
1021 rotldi r11, r11, 1 + MSR_HV_LG
1022 ori r11, r11, MSR_ME
1024 /* Check if we can deliver an external or decrementer interrupt now */
1025 ld r0, VCPU_PENDING_EXC(r4)
1026 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1028 andi. r8, r11, MSR_EE
1030 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1031 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1035 li r0, BOOK3S_INTERRUPT_EXTERNAL
1039 li r0, BOOK3S_INTERRUPT_DECREMENTER
1042 12: mtspr SPRN_SRR0, r10
1044 mtspr SPRN_SRR1, r11
1046 bl kvmppc_msr_interrupt
1052 * R10: value for HSRR0
1053 * R11: value for HSRR1
1058 stb r0,VCPU_CEDED(r4) /* cancel cede */
1059 mtspr SPRN_HSRR0,r10
1060 mtspr SPRN_HSRR1,r11
1062 /* Activate guest mode, so faults get handled by KVM */
1063 li r9, KVM_GUEST_MODE_GUEST_HV
1064 stb r9, HSTATE_IN_GUEST(r13)
1066 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1067 /* Accumulate timing */
1068 addi r3, r4, VCPU_TB_GUEST
1069 bl kvmhv_accumulate_time
1075 ld r5, VCPU_CFAR(r4)
1077 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1080 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1087 ld r1, VCPU_GPR(R1)(r4)
1088 ld r2, VCPU_GPR(R2)(r4)
1089 ld r3, VCPU_GPR(R3)(r4)
1090 ld r5, VCPU_GPR(R5)(r4)
1091 ld r6, VCPU_GPR(R6)(r4)
1092 ld r7, VCPU_GPR(R7)(r4)
1093 ld r8, VCPU_GPR(R8)(r4)
1094 ld r9, VCPU_GPR(R9)(r4)
1095 ld r10, VCPU_GPR(R10)(r4)
1096 ld r11, VCPU_GPR(R11)(r4)
1097 ld r12, VCPU_GPR(R12)(r4)
1098 ld r13, VCPU_GPR(R13)(r4)
1102 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1103 ld r0, VCPU_GPR(R0)(r4)
1104 ld r4, VCPU_GPR(R4)(r4)
1113 stw r12, VCPU_TRAP(r4)
1114 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1115 addi r3, r4, VCPU_TB_RMEXIT
1116 bl kvmhv_accumulate_time
1118 11: b kvmhv_switch_to_host
1125 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1126 12: stw r12, VCPU_TRAP(r4)
1128 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1129 addi r3, r4, VCPU_TB_RMEXIT
1130 bl kvmhv_accumulate_time
1134 /******************************************************************************
1138 *****************************************************************************/
1141 * We come here from the first-level interrupt handlers.
1143 .globl kvmppc_interrupt_hv
1144 kvmppc_interrupt_hv:
1146 * Register contents:
1147 * R12 = (guest CR << 32) | interrupt vector
1149 * guest R12 saved in shadow VCPU SCRATCH0
1150 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1151 * guest R13 saved in SPRN_SCRATCH0
1153 std r9, HSTATE_SCRATCH2(r13)
1154 lbz r9, HSTATE_IN_GUEST(r13)
1155 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1156 beq kvmppc_bad_host_intr
1157 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1158 cmpwi r9, KVM_GUEST_MODE_GUEST
1159 ld r9, HSTATE_SCRATCH2(r13)
1160 beq kvmppc_interrupt_pr
1162 /* We're now back in the host but in guest MMU context */
1163 li r9, KVM_GUEST_MODE_HOST_HV
1164 stb r9, HSTATE_IN_GUEST(r13)
1166 ld r9, HSTATE_KVM_VCPU(r13)
1168 /* Save registers */
1170 std r0, VCPU_GPR(R0)(r9)
1171 std r1, VCPU_GPR(R1)(r9)
1172 std r2, VCPU_GPR(R2)(r9)
1173 std r3, VCPU_GPR(R3)(r9)
1174 std r4, VCPU_GPR(R4)(r9)
1175 std r5, VCPU_GPR(R5)(r9)
1176 std r6, VCPU_GPR(R6)(r9)
1177 std r7, VCPU_GPR(R7)(r9)
1178 std r8, VCPU_GPR(R8)(r9)
1179 ld r0, HSTATE_SCRATCH2(r13)
1180 std r0, VCPU_GPR(R9)(r9)
1181 std r10, VCPU_GPR(R10)(r9)
1182 std r11, VCPU_GPR(R11)(r9)
1183 ld r3, HSTATE_SCRATCH0(r13)
1184 std r3, VCPU_GPR(R12)(r9)
1185 /* CR is in the high half of r12 */
1189 ld r3, HSTATE_CFAR(r13)
1190 std r3, VCPU_CFAR(r9)
1191 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1193 ld r4, HSTATE_PPR(r13)
1194 std r4, VCPU_PPR(r9)
1195 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1197 /* Restore R1/R2 so we can handle faults */
1198 ld r1, HSTATE_HOST_R1(r13)
1201 mfspr r10, SPRN_SRR0
1202 mfspr r11, SPRN_SRR1
1203 std r10, VCPU_SRR0(r9)
1204 std r11, VCPU_SRR1(r9)
1205 /* trap is in the low half of r12, clear CR from the high half */
1207 andi. r0, r12, 2 /* need to read HSRR0/1? */
1209 mfspr r10, SPRN_HSRR0
1210 mfspr r11, SPRN_HSRR1
1212 1: std r10, VCPU_PC(r9)
1213 std r11, VCPU_MSR(r9)
1217 std r3, VCPU_GPR(R13)(r9)
1220 stw r12,VCPU_TRAP(r9)
1222 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1223 addi r3, r9, VCPU_TB_RMINTR
1225 bl kvmhv_accumulate_time
1226 ld r5, VCPU_GPR(R5)(r9)
1227 ld r6, VCPU_GPR(R6)(r9)
1228 ld r7, VCPU_GPR(R7)(r9)
1229 ld r8, VCPU_GPR(R8)(r9)
1232 /* Save HEIR (HV emulation assist reg) in emul_inst
1233 if this is an HEI (HV emulation interrupt, e40) */
1234 li r3,KVM_INST_FETCH_FAILED
1235 stw r3,VCPU_LAST_INST(r9)
1236 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1239 11: stw r3,VCPU_HEIR(r9)
1241 /* these are volatile across C function calls */
1242 #ifdef CONFIG_RELOCATABLE
1243 ld r3, HSTATE_SCRATCH1(r13)
1249 std r3, VCPU_CTR(r9)
1250 std r4, VCPU_XER(r9)
1252 /* If this is a page table miss then see if it's theirs or ours */
1253 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1255 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1258 /* See if this is a leftover HDEC interrupt */
1259 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1264 bge fast_guest_return
1266 /* See if this is an hcall we can handle in real mode */
1267 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1268 beq hcall_try_real_mode
1270 /* Hypervisor doorbell - exit only if host IPI flag set */
1271 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1273 lbz r0, HSTATE_HOST_IPI(r13)
1278 /* External interrupt ? */
1279 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1280 bne+ guest_exit_cont
1282 /* External interrupt, first check for host_ipi. If this is
1283 * set, we know the host wants us out so let's do it now
1288 * Restore the active volatile registers after returning from
1291 ld r9, HSTATE_KVM_VCPU(r13)
1292 li r12, BOOK3S_INTERRUPT_EXTERNAL
1295 * kvmppc_read_intr return codes:
1297 * Exit to host (r3 > 0)
1298 * 1 An interrupt is pending that needs to be handled by the host
1299 * Exit guest and return to host by branching to guest_exit_cont
1301 * 2 Passthrough that needs completion in the host
1302 * Exit guest and return to host by branching to guest_exit_cont
1303 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1304 * to indicate to the host to complete handling the interrupt
1306 * Before returning to guest, we check if any CPU is heading out
1307 * to the host and if so, we head out also. If no CPUs are heading
1308 * check return values <= 0.
1310 * Return to guest (r3 <= 0)
1311 * 0 No external interrupt is pending
1312 * -1 A guest wakeup IPI (which has now been cleared)
1313 * In either case, we return to guest to deliver any pending
1316 * -2 A PCI passthrough external interrupt was handled
1317 * (interrupt was delivered directly to guest)
1318 * Return to guest to deliver any pending guest interrupts.
1324 /* Return code = 2 */
1325 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1326 stw r12, VCPU_TRAP(r9)
1329 1: /* Return code <= 1 */
1333 /* Return code <= 0 */
1334 4: ld r5, HSTATE_KVM_VCORE(r13)
1335 lwz r0, VCORE_ENTRY_EXIT(r5)
1338 blt deliver_guest_interrupt
1340 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1341 #ifdef CONFIG_KVM_XICS
1342 /* We are exiting, pull the VP from the XIVE */
1343 lwz r0, VCPU_XIVE_PUSHED(r9)
1346 li r7, TM_SPC_PULL_OS_CTX
1349 andi. r0, r0, MSR_IR /* in real mode? */
1351 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1354 /* First load to pull the context, we ignore the value */
1357 /* Second load to recover the context state (Words 0 and 1) */
1360 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1363 /* First load to pull the context, we ignore the value */
1366 /* Second load to recover the context state (Words 0 and 1) */
1368 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1369 /* Fixup some of the state for the next load */
1372 stw r10, VCPU_XIVE_PUSHED(r9)
1373 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1374 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1376 #endif /* CONFIG_KVM_XICS */
1377 /* Save more register state */
1380 std r6, VCPU_DAR(r9)
1381 stw r7, VCPU_DSISR(r9)
1382 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1383 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1385 std r6, VCPU_FAULT_DAR(r9)
1386 stw r7, VCPU_FAULT_DSISR(r9)
1388 /* See if it is a machine check */
1389 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1390 beq machine_check_realmode
1392 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1393 addi r3, r9, VCPU_TB_RMEXIT
1395 bl kvmhv_accumulate_time
1399 /* Increment exit count, poke other threads to exit */
1400 bl kvmhv_commence_exit
1402 ld r9, HSTATE_KVM_VCPU(r13)
1403 lwz r12, VCPU_TRAP(r9)
1405 /* Stop others sending VCPU interrupts to this physical CPU */
1407 stw r0, VCPU_CPU(r9)
1408 stw r0, VCPU_THREAD_CPU(r9)
1410 /* Save guest CTRL register, set runlatch to 1 */
1412 stw r6,VCPU_CTRL(r9)
1418 /* Read the guest SLB and save it away */
1420 lbz r0, KVM_RADIX(r5)
1423 bne 3f /* for radix, save 0 entries */
1424 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1429 andis. r0,r8,SLB_ESID_V@h
1431 add r8,r8,r6 /* put index in */
1433 std r8,VCPU_SLB_E(r7)
1434 std r3,VCPU_SLB_V(r7)
1435 addi r7,r7,VCPU_SLB_SIZE
1439 3: stw r5,VCPU_SLB_MAX(r9)
1442 * Save the guest PURR/SPURR
1447 ld r8,VCPU_SPURR(r9)
1448 std r5,VCPU_PURR(r9)
1449 std r6,VCPU_SPURR(r9)
1454 * Restore host PURR/SPURR and add guest times
1455 * so that the time in the guest gets accounted.
1457 ld r3,HSTATE_PURR(r13)
1458 ld r4,HSTATE_SPURR(r13)
1469 /* r5 is a guest timebase value here, convert to host TB */
1470 ld r3,HSTATE_KVM_VCORE(r13)
1471 ld r4,VCORE_TB_OFFSET(r3)
1473 std r5,VCPU_DEC_EXPIRES(r9)
1477 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1478 /* Save POWER8-specific registers */
1482 std r5, VCPU_IAMR(r9)
1483 stw r6, VCPU_PSPB(r9)
1484 std r7, VCPU_FSCR(r9)
1488 std r7, VCPU_TAR(r9)
1489 mfspr r8, SPRN_EBBHR
1490 std r8, VCPU_EBBHR(r9)
1491 mfspr r5, SPRN_EBBRR
1492 mfspr r6, SPRN_BESCR
1495 std r5, VCPU_EBBRR(r9)
1496 std r6, VCPU_BESCR(r9)
1497 stw r7, VCPU_GUEST_PID(r9)
1498 std r8, VCPU_WORT(r9)
1500 mfspr r5, SPRN_TCSCR
1502 mfspr r7, SPRN_CSIGR
1504 std r5, VCPU_TCSCR(r9)
1505 std r6, VCPU_ACOP(r9)
1506 std r7, VCPU_CSIGR(r9)
1507 std r8, VCPU_TACR(r9)
1510 mfspr r6, SPRN_PSSCR
1511 std r5, VCPU_TID(r9)
1512 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1514 std r6, VCPU_PSSCR(r9)
1515 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1517 * Restore various registers to 0, where non-zero values
1518 * set by the guest could disrupt the host.
1521 mtspr SPRN_CIABR, r0
1522 mtspr SPRN_DAWRX, r0
1527 mtspr SPRN_TCSCR, r0
1528 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1531 mtspr SPRN_MMCRS, r0
1532 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1535 /* Save and reset AMR and UAMOR before turning on the MMU */
1539 std r6,VCPU_UAMOR(r9)
1542 mtspr SPRN_UAMOR, r6
1544 /* Switch DSCR back to host value */
1546 ld r7, HSTATE_DSCR(r13)
1547 std r8, VCPU_DSCR(r9)
1550 /* Save non-volatile GPRs */
1551 std r14, VCPU_GPR(R14)(r9)
1552 std r15, VCPU_GPR(R15)(r9)
1553 std r16, VCPU_GPR(R16)(r9)
1554 std r17, VCPU_GPR(R17)(r9)
1555 std r18, VCPU_GPR(R18)(r9)
1556 std r19, VCPU_GPR(R19)(r9)
1557 std r20, VCPU_GPR(R20)(r9)
1558 std r21, VCPU_GPR(R21)(r9)
1559 std r22, VCPU_GPR(R22)(r9)
1560 std r23, VCPU_GPR(R23)(r9)
1561 std r24, VCPU_GPR(R24)(r9)
1562 std r25, VCPU_GPR(R25)(r9)
1563 std r26, VCPU_GPR(R26)(r9)
1564 std r27, VCPU_GPR(R27)(r9)
1565 std r28, VCPU_GPR(R28)(r9)
1566 std r29, VCPU_GPR(R29)(r9)
1567 std r30, VCPU_GPR(R30)(r9)
1568 std r31, VCPU_GPR(R31)(r9)
1571 mfspr r3, SPRN_SPRG0
1572 mfspr r4, SPRN_SPRG1
1573 mfspr r5, SPRN_SPRG2
1574 mfspr r6, SPRN_SPRG3
1575 std r3, VCPU_SPRG0(r9)
1576 std r4, VCPU_SPRG1(r9)
1577 std r5, VCPU_SPRG2(r9)
1578 std r6, VCPU_SPRG3(r9)
1584 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1587 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1590 /* Increment yield count if they have a VPA */
1591 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1594 li r4, LPPACA_YIELDCOUNT
1599 stb r3, VCPU_VPA_DIRTY(r9)
1601 /* Save PMU registers if requested */
1602 /* r8 and cr0.eq are live here */
1605 * POWER8 seems to have a hardware bug where setting
1606 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1607 * when some counters are already negative doesn't seem
1608 * to cause a performance monitor alert (and hence interrupt).
1609 * The effect of this is that when saving the PMU state,
1610 * if there is no PMU alert pending when we read MMCR0
1611 * before freezing the counters, but one becomes pending
1612 * before we read the counters, we lose it.
1613 * To work around this, we need a way to freeze the counters
1614 * before reading MMCR0. Normally, freezing the counters
1615 * is done by writing MMCR0 (to set MMCR0[FC]) which
1616 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1617 * we can also freeze the counters using MMCR2, by writing
1618 * 1s to all the counter freeze condition bits (there are
1619 * 9 bits each for 6 counters).
1621 li r3, -1 /* set all freeze bits */
1623 mfspr r10, SPRN_MMCR2
1624 mtspr SPRN_MMCR2, r3
1626 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1628 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1629 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1630 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1631 mfspr r6, SPRN_MMCRA
1632 /* Clear MMCRA in order to disable SDAR updates */
1634 mtspr SPRN_MMCRA, r7
1636 beq 21f /* if no VPA, save PMU stuff anyway */
1637 lbz r7, LPPACA_PMCINUSE(r8)
1638 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1640 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1642 21: mfspr r5, SPRN_MMCR1
1645 std r4, VCPU_MMCR(r9)
1646 std r5, VCPU_MMCR + 8(r9)
1647 std r6, VCPU_MMCR + 16(r9)
1649 std r10, VCPU_MMCR + 24(r9)
1650 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1651 std r7, VCPU_SIAR(r9)
1652 std r8, VCPU_SDAR(r9)
1659 stw r3, VCPU_PMC(r9)
1660 stw r4, VCPU_PMC + 4(r9)
1661 stw r5, VCPU_PMC + 8(r9)
1662 stw r6, VCPU_PMC + 12(r9)
1663 stw r7, VCPU_PMC + 16(r9)
1664 stw r8, VCPU_PMC + 20(r9)
1667 std r5, VCPU_SIER(r9)
1668 BEGIN_FTR_SECTION_NESTED(96)
1669 mfspr r6, SPRN_SPMC1
1670 mfspr r7, SPRN_SPMC2
1671 mfspr r8, SPRN_MMCRS
1672 stw r6, VCPU_PMC + 24(r9)
1673 stw r7, VCPU_PMC + 28(r9)
1674 std r8, VCPU_MMCR + 32(r9)
1676 mtspr SPRN_MMCRS, r4
1677 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1678 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1686 /* Restore host values of some registers */
1688 ld r5, STACK_SLOT_TID(r1)
1689 ld r6, STACK_SLOT_PSSCR(r1)
1690 ld r7, STACK_SLOT_PID(r1)
1691 ld r8, STACK_SLOT_IAMR(r1)
1693 mtspr SPRN_PSSCR, r6
1696 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1699 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
1702 * POWER7/POWER8 guest -> host partition switch code.
1703 * We don't have to lock against tlbies but we do
1704 * have to coordinate the hardware threads.
1706 kvmhv_switch_to_host:
1707 /* Secondary threads wait for primary to do partition switch */
1708 ld r5,HSTATE_KVM_VCORE(r13)
1709 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1710 lbz r3,HSTATE_PTID(r13)
1714 13: lbz r3,VCORE_IN_GUEST(r5)
1720 /* Primary thread waits for all the secondaries to exit guest */
1721 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1722 rlwinm r0,r3,32-8,0xff
1728 /* Did we actually switch to the guest at all? */
1729 lbz r6, VCORE_IN_GUEST(r5)
1733 /* Primary thread switches back to host partition */
1734 lwz r7,KVM_HOST_LPID(r4)
1736 ld r6,KVM_HOST_SDR1(r4)
1737 li r8,LPID_RSVD /* switch to reserved LPID */
1740 mtspr SPRN_SDR1,r6 /* switch to host page table */
1741 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1746 /* DPDES and VTB are shared between threads */
1747 mfspr r7, SPRN_DPDES
1749 std r7, VCORE_DPDES(r5)
1750 std r8, VCORE_VTB(r5)
1751 /* clear DPDES so we don't get guest doorbells in the host */
1753 mtspr SPRN_DPDES, r8
1754 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1756 /* If HMI, call kvmppc_realmode_hmi_handler() */
1757 cmpwi r12, BOOK3S_INTERRUPT_HMI
1759 bl kvmppc_realmode_hmi_handler
1761 li r12, BOOK3S_INTERRUPT_HMI
1763 * At this point kvmppc_realmode_hmi_handler would have resync-ed
1764 * the TB. Hence it is not required to subtract guest timebase
1765 * offset from timebase. So, skip it.
1767 * Also, do not call kvmppc_subcore_exit_guest() because it has
1768 * been invoked as part of kvmppc_realmode_hmi_handler().
1773 /* Subtract timebase offset from timebase */
1774 ld r8,VCORE_TB_OFFSET(r5)
1777 mftb r6 /* current guest timebase */
1779 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1780 mftb r7 /* check if lower 24 bits overflowed */
1785 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1788 17: bl kvmppc_subcore_exit_guest
1790 30: ld r5,HSTATE_KVM_VCORE(r13)
1791 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1794 ld r0, VCORE_PCR(r5)
1800 /* Signal secondary CPUs to continue */
1801 stb r0,VCORE_IN_GUEST(r5)
1802 19: lis r8,0x7fff /* MAX_INT@h */
1805 16: ld r8,KVM_HOST_LPCR(r4)
1809 /* load host SLB entries */
1810 BEGIN_MMU_FTR_SECTION
1812 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1813 ld r8,PACA_SLBSHADOWPTR(r13)
1815 .rept SLB_NUM_BOLTED
1816 li r3, SLBSHADOW_SAVEAREA
1820 andis. r7,r5,SLB_ESID_V@h
1826 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1827 /* Finish timing, if we have a vcpu */
1828 ld r4, HSTATE_KVM_VCPU(r13)
1832 bl kvmhv_accumulate_time
1835 /* Unset guest mode */
1836 li r0, KVM_GUEST_MODE_NONE
1837 stb r0, HSTATE_IN_GUEST(r13)
1839 ld r0, 112+PPC_LR_STKOFF(r1)
1845 * Check whether an HDSI is an HPTE not found fault or something else.
1846 * If it is an HPTE not found fault that is due to the guest accessing
1847 * a page that they have mapped but which we have paged out, then
1848 * we continue on with the guest exit path. In all other cases,
1849 * reflect the HDSI to the guest as a DSI.
1853 lbz r0, KVM_RADIX(r3)
1856 mfspr r6, SPRN_HDSISR
1857 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
1858 /* HPTE not found fault or protection fault? */
1859 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1860 beq 1f /* if not, send it to the guest */
1861 andi. r0, r11, MSR_DR /* data relocation enabled? */
1864 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
1866 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1868 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1869 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1870 bne 7f /* if no SLB entry found */
1871 4: std r4, VCPU_FAULT_DAR(r9)
1872 stw r6, VCPU_FAULT_DSISR(r9)
1874 /* Search the hash table. */
1875 mr r3, r9 /* vcpu pointer */
1876 li r7, 1 /* data fault */
1877 bl kvmppc_hpte_hv_fault
1878 ld r9, HSTATE_KVM_VCPU(r13)
1880 ld r11, VCPU_MSR(r9)
1881 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1882 cmpdi r3, 0 /* retry the instruction */
1884 cmpdi r3, -1 /* handle in kernel mode */
1886 cmpdi r3, -2 /* MMIO emulation; need instr word */
1889 /* Synthesize a DSI (or DSegI) for the guest */
1890 ld r4, VCPU_FAULT_DAR(r9)
1892 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1893 mtspr SPRN_DSISR, r6
1894 7: mtspr SPRN_DAR, r4
1895 mtspr SPRN_SRR0, r10
1896 mtspr SPRN_SRR1, r11
1898 bl kvmppc_msr_interrupt
1899 fast_interrupt_c_return:
1900 6: ld r7, VCPU_CTR(r9)
1907 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1908 ld r5, KVM_VRMA_SLB_V(r5)
1911 /* If this is for emulated MMIO, load the instruction word */
1912 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1914 /* Set guest mode to 'jump over instruction' so if lwz faults
1915 * we'll just continue at the next IP. */
1916 li r0, KVM_GUEST_MODE_SKIP
1917 stb r0, HSTATE_IN_GUEST(r13)
1919 /* Do the access with MSR:DR enabled */
1921 ori r4, r3, MSR_DR /* Enable paging for data */
1926 /* Store the result */
1927 stw r8, VCPU_LAST_INST(r9)
1929 /* Unset guest mode. */
1930 li r0, KVM_GUEST_MODE_HOST_HV
1931 stb r0, HSTATE_IN_GUEST(r13)
1935 std r4, VCPU_FAULT_DAR(r9)
1936 stw r6, VCPU_FAULT_DSISR(r9)
1939 std r5, VCPU_FAULT_GPA(r9)
1943 * Similarly for an HISI, reflect it to the guest as an ISI unless
1944 * it is an HPTE not found fault for a page that we have paged out.
1948 lbz r0, KVM_RADIX(r3)
1950 bne .Lradix_hisi /* for radix, just save ASDR */
1951 andis. r0, r11, SRR1_ISI_NOPT@h
1953 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1956 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
1958 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1960 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1961 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
1962 bne 7f /* if no SLB entry found */
1964 /* Search the hash table. */
1965 mr r3, r9 /* vcpu pointer */
1968 li r7, 0 /* instruction fault */
1969 bl kvmppc_hpte_hv_fault
1970 ld r9, HSTATE_KVM_VCPU(r13)
1972 ld r11, VCPU_MSR(r9)
1973 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1974 cmpdi r3, 0 /* retry the instruction */
1975 beq fast_interrupt_c_return
1976 cmpdi r3, -1 /* handle in kernel mode */
1979 /* Synthesize an ISI (or ISegI) for the guest */
1981 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
1982 7: mtspr SPRN_SRR0, r10
1983 mtspr SPRN_SRR1, r11
1985 bl kvmppc_msr_interrupt
1986 b fast_interrupt_c_return
1988 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1989 ld r5, KVM_VRMA_SLB_V(r6)
1993 * Try to handle an hcall in real mode.
1994 * Returns to the guest if we handle it, or continues on up to
1995 * the kernel if we can't (i.e. if we don't have a handler for
1996 * it, or if the handler returns H_TOO_HARD).
1998 * r5 - r8 contain hcall args,
1999 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2001 hcall_try_real_mode:
2002 ld r3,VCPU_GPR(R3)(r9)
2004 /* sc 1 from userspace - reflect to guest syscall */
2005 bne sc_1_fast_return
2007 cmpldi r3,hcall_real_table_end - hcall_real_table
2009 /* See if this hcall is enabled for in-kernel handling */
2011 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2012 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2014 ld r0, KVM_ENABLED_HCALLS(r4)
2015 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2019 /* Get pointer to handler, if any, and call it */
2020 LOAD_REG_ADDR(r4, hcall_real_table)
2026 mr r3,r9 /* get vcpu pointer */
2027 ld r4,VCPU_GPR(R4)(r9)
2030 beq hcall_real_fallback
2031 ld r4,HSTATE_KVM_VCPU(r13)
2032 std r3,VCPU_GPR(R3)(r4)
2040 li r10, BOOK3S_INTERRUPT_SYSCALL
2041 bl kvmppc_msr_interrupt
2045 /* We've attempted a real mode hcall, but it's punted it back
2046 * to userspace. We need to restore some clobbered volatiles
2047 * before resuming the pass-it-to-qemu path */
2048 hcall_real_fallback:
2049 li r12,BOOK3S_INTERRUPT_SYSCALL
2050 ld r9, HSTATE_KVM_VCPU(r13)
2054 .globl hcall_real_table
2056 .long 0 /* 0 - unused */
2057 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2058 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2059 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2060 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2061 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2062 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2063 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2064 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2065 .long 0 /* 0x24 - H_SET_SPRG0 */
2066 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2081 #ifdef CONFIG_KVM_XICS
2082 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2083 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2084 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2085 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2086 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2088 .long 0 /* 0x64 - H_EOI */
2089 .long 0 /* 0x68 - H_CPPR */
2090 .long 0 /* 0x6c - H_IPI */
2091 .long 0 /* 0x70 - H_IPOLL */
2092 .long 0 /* 0x74 - H_XIRR */
2120 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2121 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2137 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2141 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2142 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2143 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2255 #ifdef CONFIG_KVM_XICS
2256 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2258 .long 0 /* 0x2fc - H_XIRR_X*/
2260 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2261 .globl hcall_real_table_end
2262 hcall_real_table_end:
2264 _GLOBAL(kvmppc_h_set_xdabr)
2265 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2267 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2270 6: li r3, H_PARAMETER
2273 _GLOBAL(kvmppc_h_set_dabr)
2274 li r5, DABRX_USER | DABRX_KERNEL
2278 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2279 std r4,VCPU_DABR(r3)
2280 stw r5, VCPU_DABRX(r3)
2281 mtspr SPRN_DABRX, r5
2282 /* Work around P7 bug where DABR can get corrupted on mtspr */
2283 1: mtspr SPRN_DABR,r4
2291 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2292 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2293 rlwimi r5, r4, 2, DAWRX_WT
2295 std r4, VCPU_DAWR(r3)
2296 std r5, VCPU_DAWRX(r3)
2298 mtspr SPRN_DAWRX, r5
2302 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2304 std r11,VCPU_MSR(r3)
2306 stb r0,VCPU_CEDED(r3)
2307 sync /* order setting ceded vs. testing prodded */
2308 lbz r5,VCPU_PRODDED(r3)
2310 bne kvm_cede_prodded
2311 li r12,0 /* set trap to 0 to say hcall is handled */
2312 stw r12,VCPU_TRAP(r3)
2314 std r0,VCPU_GPR(R3)(r3)
2317 * Set our bit in the bitmask of napping threads unless all the
2318 * other threads are already napping, in which case we send this
2321 ld r5,HSTATE_KVM_VCORE(r13)
2322 lbz r6,HSTATE_PTID(r13)
2323 lwz r8,VCORE_ENTRY_EXIT(r5)
2327 addi r6,r5,VCORE_NAPPING_THREADS
2334 /* order napping_threads update vs testing entry_exit_map */
2337 stb r0,HSTATE_NAPPING(r13)
2338 lwz r7,VCORE_ENTRY_EXIT(r5)
2340 bge 33f /* another thread already exiting */
2343 * Although not specifically required by the architecture, POWER7
2344 * preserves the following registers in nap mode, even if an SMT mode
2345 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2346 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2348 /* Save non-volatile GPRs */
2349 std r14, VCPU_GPR(R14)(r3)
2350 std r15, VCPU_GPR(R15)(r3)
2351 std r16, VCPU_GPR(R16)(r3)
2352 std r17, VCPU_GPR(R17)(r3)
2353 std r18, VCPU_GPR(R18)(r3)
2354 std r19, VCPU_GPR(R19)(r3)
2355 std r20, VCPU_GPR(R20)(r3)
2356 std r21, VCPU_GPR(R21)(r3)
2357 std r22, VCPU_GPR(R22)(r3)
2358 std r23, VCPU_GPR(R23)(r3)
2359 std r24, VCPU_GPR(R24)(r3)
2360 std r25, VCPU_GPR(R25)(r3)
2361 std r26, VCPU_GPR(R26)(r3)
2362 std r27, VCPU_GPR(R27)(r3)
2363 std r28, VCPU_GPR(R28)(r3)
2364 std r29, VCPU_GPR(R29)(r3)
2365 std r30, VCPU_GPR(R30)(r3)
2366 std r31, VCPU_GPR(R31)(r3)
2371 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2373 ld r9, HSTATE_KVM_VCPU(r13)
2375 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2379 * Set DEC to the smaller of DEC and HDEC, so that we wake
2380 * no later than the end of our timeslice (HDEC interrupts
2381 * don't wake us from nap).
2392 /* save expiry time of guest decrementer */
2394 ld r4, HSTATE_KVM_VCPU(r13)
2395 ld r5, HSTATE_KVM_VCORE(r13)
2396 ld r6, VCORE_TB_OFFSET(r5)
2397 subf r3, r6, r3 /* convert to host TB value */
2398 std r3, VCPU_DEC_EXPIRES(r4)
2400 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2401 ld r4, HSTATE_KVM_VCPU(r13)
2402 addi r3, r4, VCPU_TB_CEDE
2403 bl kvmhv_accumulate_time
2406 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2409 * Take a nap until a decrementer or external or doobell interrupt
2410 * occurs, with PECE1 and PECE0 set in LPCR.
2411 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2412 * Also clear the runlatch bit before napping.
2415 mfspr r0, SPRN_CTRLF
2417 mtspr SPRN_CTRLT, r0
2420 stb r0,HSTATE_HWTHREAD_REQ(r13)
2422 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2424 ori r5, r5, LPCR_PECEDH
2425 rlwimi r5, r3, 0, LPCR_PECEDP
2426 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2428 kvm_nap_sequence: /* desired LPCR value in r5 */
2431 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2432 * enable state loss = 1 (allow SMT mode switch)
2433 * requested level = 0 (just stop dispatching)
2435 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2436 mtspr SPRN_PSSCR, r3
2437 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2438 li r4, LPCR_PECE_HVEE@higher
2441 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2445 std r0, HSTATE_SCRATCH0(r13)
2447 ld r0, HSTATE_SCRATCH0(r13)
2454 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
2463 /* get vcpu pointer */
2464 ld r4, HSTATE_KVM_VCPU(r13)
2466 /* Woken by external or decrementer interrupt */
2467 ld r1, HSTATE_HOST_R1(r13)
2469 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2470 addi r3, r4, VCPU_TB_RMINTR
2471 bl kvmhv_accumulate_time
2474 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2476 bl kvmppc_restore_tm
2477 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2480 /* load up FP state */
2483 /* Restore guest decrementer */
2484 ld r3, VCPU_DEC_EXPIRES(r4)
2485 ld r5, HSTATE_KVM_VCORE(r13)
2486 ld r6, VCORE_TB_OFFSET(r5)
2487 add r3, r3, r6 /* convert host TB to guest TB value */
2493 ld r14, VCPU_GPR(R14)(r4)
2494 ld r15, VCPU_GPR(R15)(r4)
2495 ld r16, VCPU_GPR(R16)(r4)
2496 ld r17, VCPU_GPR(R17)(r4)
2497 ld r18, VCPU_GPR(R18)(r4)
2498 ld r19, VCPU_GPR(R19)(r4)
2499 ld r20, VCPU_GPR(R20)(r4)
2500 ld r21, VCPU_GPR(R21)(r4)
2501 ld r22, VCPU_GPR(R22)(r4)
2502 ld r23, VCPU_GPR(R23)(r4)
2503 ld r24, VCPU_GPR(R24)(r4)
2504 ld r25, VCPU_GPR(R25)(r4)
2505 ld r26, VCPU_GPR(R26)(r4)
2506 ld r27, VCPU_GPR(R27)(r4)
2507 ld r28, VCPU_GPR(R28)(r4)
2508 ld r29, VCPU_GPR(R29)(r4)
2509 ld r30, VCPU_GPR(R30)(r4)
2510 ld r31, VCPU_GPR(R31)(r4)
2512 /* Check the wake reason in SRR1 to see why we got here */
2513 bl kvmppc_check_wake_reason
2516 * Restore volatile registers since we could have called a
2517 * C routine in kvmppc_check_wake_reason
2519 * r3 tells us whether we need to return to host or not
2520 * WARNING: it gets checked further down:
2521 * should not modify r3 until this check is done.
2523 ld r4, HSTATE_KVM_VCPU(r13)
2525 /* clear our bit in vcore->napping_threads */
2526 34: ld r5,HSTATE_KVM_VCORE(r13)
2527 lbz r7,HSTATE_PTID(r13)
2530 addi r6,r5,VCORE_NAPPING_THREADS
2536 stb r0,HSTATE_NAPPING(r13)
2538 /* See if the wake reason saved in r3 means we need to exit */
2539 stw r12, VCPU_TRAP(r4)
2544 /* see if any other thread is already exiting */
2545 lwz r0,VCORE_ENTRY_EXIT(r5)
2549 b kvmppc_cede_reentry /* if not go back to guest */
2551 /* cede when already previously prodded case */
2554 stb r0,VCPU_PRODDED(r3)
2555 sync /* order testing prodded vs. clearing ceded */
2556 stb r0,VCPU_CEDED(r3)
2560 /* we've ceded but we want to give control to the host */
2562 ld r9, HSTATE_KVM_VCPU(r13)
2565 /* Try to handle a machine check in real mode */
2566 machine_check_realmode:
2567 mr r3, r9 /* get vcpu pointer */
2568 bl kvmppc_realmode_machine_check
2570 ld r9, HSTATE_KVM_VCPU(r13)
2571 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2573 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through
2574 * machine check interrupt (set HSRR0 to 0x200). And for handled
2575 * errors (no-fatal), just go back to guest execution with current
2576 * HSRR0 instead of exiting guest. This new approach will inject
2577 * machine check to guest for fatal error causing guest to crash.
2579 * The old code used to return to host for unhandled errors which
2580 * was causing guest to hang with soft lockups inside guest and
2581 * makes it difficult to recover guest instance.
2583 * if we receive machine check with MSR(RI=0) then deliver it to
2584 * guest as machine check causing guest to crash.
2586 ld r11, VCPU_MSR(r9)
2587 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2588 bne mc_cont /* if so, exit to host */
2589 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2590 beq 1f /* Deliver a machine check to guest */
2592 cmpdi r3, 0 /* Did we handle MCE ? */
2593 bne 2f /* Continue guest execution. */
2594 /* If not, deliver a machine check. SRR0/1 are already set */
2595 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2596 bl kvmppc_msr_interrupt
2597 2: b fast_interrupt_c_return
2600 * Check the reason we woke from nap, and take appropriate action.
2602 * 0 if nothing needs to be done
2603 * 1 if something happened that needs to be handled by the host
2604 * -1 if there was a guest wakeup (IPI or msgsnd)
2605 * -2 if we handled a PCI passthrough interrupt (returned by
2606 * kvmppc_read_intr only)
2608 * Also sets r12 to the interrupt vector for any interrupt that needs
2609 * to be handled now by the host (0x500 for external interrupt), or zero.
2610 * Modifies all volatile registers (since it may call a C function).
2611 * This routine calls kvmppc_read_intr, a C function, if an external
2612 * interrupt is pending.
2614 kvmppc_check_wake_reason:
2617 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2619 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2620 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2621 cmpwi r6, 8 /* was it an external interrupt? */
2622 beq 7f /* if so, see what it was */
2625 cmpwi r6, 6 /* was it the decrementer? */
2628 cmpwi r6, 5 /* privileged doorbell? */
2630 cmpwi r6, 3 /* hypervisor doorbell? */
2632 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2633 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2635 li r3, 1 /* anything else, return 1 */
2638 /* hypervisor doorbell */
2639 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2642 * Clear the doorbell as we will invoke the handler
2643 * explicitly in the guest exit path.
2645 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2647 /* see if it's a host IPI */
2649 lbz r0, HSTATE_HOST_IPI(r13)
2652 /* if not, return -1 */
2656 /* Woken up due to Hypervisor maintenance interrupt */
2657 4: li r12, BOOK3S_INTERRUPT_HMI
2661 /* external interrupt - create a stack frame so we can call C */
2663 std r0, PPC_LR_STKOFF(r1)
2664 stdu r1, -PPC_MIN_STKFRM(r1)
2667 li r12, BOOK3S_INTERRUPT_EXTERNAL
2672 * Return code of 2 means PCI passthrough interrupt, but
2673 * we need to return back to host to complete handling the
2674 * interrupt. Trap reason is expected in r12 by guest
2677 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2679 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2680 addi r1, r1, PPC_MIN_STKFRM
2685 * Save away FP, VMX and VSX registers.
2687 * N.B. r30 and r31 are volatile across this function,
2688 * thus it is not callable from C.
2695 #ifdef CONFIG_ALTIVEC
2697 oris r8,r8,MSR_VEC@h
2698 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2702 oris r8,r8,MSR_VSX@h
2703 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2706 addi r3,r3,VCPU_FPRS
2708 #ifdef CONFIG_ALTIVEC
2710 addi r3,r31,VCPU_VRS
2712 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2714 mfspr r6,SPRN_VRSAVE
2715 stw r6,VCPU_VRSAVE(r31)
2720 * Load up FP, VMX and VSX registers
2722 * N.B. r30 and r31 are volatile across this function,
2723 * thus it is not callable from C.
2730 #ifdef CONFIG_ALTIVEC
2732 oris r8,r8,MSR_VEC@h
2733 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2737 oris r8,r8,MSR_VSX@h
2738 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2741 addi r3,r4,VCPU_FPRS
2743 #ifdef CONFIG_ALTIVEC
2745 addi r3,r31,VCPU_VRS
2747 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2749 lwz r7,VCPU_VRSAVE(r31)
2750 mtspr SPRN_VRSAVE,r7
2755 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2757 * Save transactional state and TM-related registers.
2758 * Called with r9 pointing to the vcpu struct.
2759 * This can modify all checkpointed registers, but
2760 * restores r1, r2 and r9 (vcpu pointer) before exit.
2764 std r0, PPC_LR_STKOFF(r1)
2769 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2773 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2774 beq 1f /* TM not active in guest. */
2776 std r1, HSTATE_HOST_R1(r13)
2777 li r3, TM_CAUSE_KVM_RESCHED
2779 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2783 /* All GPRs are volatile at this point. */
2786 /* Temporarily store r13 and r9 so we have some regs to play with */
2789 std r9, PACATMSCRATCH(r13)
2790 ld r9, HSTATE_KVM_VCPU(r13)
2792 /* Get a few more GPRs free. */
2793 std r29, VCPU_GPRS_TM(29)(r9)
2794 std r30, VCPU_GPRS_TM(30)(r9)
2795 std r31, VCPU_GPRS_TM(31)(r9)
2797 /* Save away PPR and DSCR soon so don't run with user values. */
2800 mfspr r30, SPRN_DSCR
2801 ld r29, HSTATE_DSCR(r13)
2802 mtspr SPRN_DSCR, r29
2804 /* Save all but r9, r13 & r29-r31 */
2807 .if (reg != 9) && (reg != 13)
2808 std reg, VCPU_GPRS_TM(reg)(r9)
2812 /* ... now save r13 */
2814 std r4, VCPU_GPRS_TM(13)(r9)
2815 /* ... and save r9 */
2816 ld r4, PACATMSCRATCH(r13)
2817 std r4, VCPU_GPRS_TM(9)(r9)
2819 /* Reload stack pointer and TOC. */
2820 ld r1, HSTATE_HOST_R1(r13)
2823 /* Set MSR RI now we have r1 and r13 back. */
2827 /* Save away checkpinted SPRs. */
2828 std r31, VCPU_PPR_TM(r9)
2829 std r30, VCPU_DSCR_TM(r9)
2836 std r5, VCPU_LR_TM(r9)
2837 stw r6, VCPU_CR_TM(r9)
2838 std r7, VCPU_CTR_TM(r9)
2839 std r8, VCPU_AMR_TM(r9)
2840 std r10, VCPU_TAR_TM(r9)
2841 std r11, VCPU_XER_TM(r9)
2843 /* Restore r12 as trap number. */
2844 lwz r12, VCPU_TRAP(r9)
2847 addi r3, r9, VCPU_FPRS_TM
2849 addi r3, r9, VCPU_VRS_TM
2851 mfspr r6, SPRN_VRSAVE
2852 stw r6, VCPU_VRSAVE_TM(r9)
2855 * We need to save these SPRs after the treclaim so that the software
2856 * error code is recorded correctly in the TEXASR. Also the user may
2857 * change these outside of a transaction, so they must always be
2860 mfspr r5, SPRN_TFHAR
2861 mfspr r6, SPRN_TFIAR
2862 mfspr r7, SPRN_TEXASR
2863 std r5, VCPU_TFHAR(r9)
2864 std r6, VCPU_TFIAR(r9)
2865 std r7, VCPU_TEXASR(r9)
2867 ld r0, PPC_LR_STKOFF(r1)
2872 * Restore transactional state and TM-related registers.
2873 * Called with r4 pointing to the vcpu struct.
2874 * This potentially modifies all checkpointed registers.
2875 * It restores r1, r2, r4 from the PACA.
2879 std r0, PPC_LR_STKOFF(r1)
2881 /* Turn on TM/FP/VSX/VMX so we can restore them. */
2887 oris r5, r5, (MSR_VEC | MSR_VSX)@h
2891 * The user may change these outside of a transaction, so they must
2892 * always be context switched.
2894 ld r5, VCPU_TFHAR(r4)
2895 ld r6, VCPU_TFIAR(r4)
2896 ld r7, VCPU_TEXASR(r4)
2897 mtspr SPRN_TFHAR, r5
2898 mtspr SPRN_TFIAR, r6
2899 mtspr SPRN_TEXASR, r7
2902 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2903 beqlr /* TM not active in guest */
2904 std r1, HSTATE_HOST_R1(r13)
2906 /* Make sure the failure summary is set, otherwise we'll program check
2907 * when we trechkpt. It's possible that this might have been not set
2908 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
2911 oris r7, r7, (TEXASR_FS)@h
2912 mtspr SPRN_TEXASR, r7
2915 * We need to load up the checkpointed state for the guest.
2916 * We need to do this early as it will blow away any GPRs, VSRs and
2921 addi r3, r31, VCPU_FPRS_TM
2923 addi r3, r31, VCPU_VRS_TM
2926 lwz r7, VCPU_VRSAVE_TM(r4)
2927 mtspr SPRN_VRSAVE, r7
2929 ld r5, VCPU_LR_TM(r4)
2930 lwz r6, VCPU_CR_TM(r4)
2931 ld r7, VCPU_CTR_TM(r4)
2932 ld r8, VCPU_AMR_TM(r4)
2933 ld r9, VCPU_TAR_TM(r4)
2934 ld r10, VCPU_XER_TM(r4)
2943 * Load up PPR and DSCR values but don't put them in the actual SPRs
2944 * till the last moment to avoid running with userspace PPR and DSCR for
2947 ld r29, VCPU_DSCR_TM(r4)
2948 ld r30, VCPU_PPR_TM(r4)
2950 std r2, PACATMSCRATCH(r13) /* Save TOC */
2952 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2956 /* Load GPRs r0-r28 */
2959 ld reg, VCPU_GPRS_TM(reg)(r31)
2963 mtspr SPRN_DSCR, r29
2966 /* Load final GPRs */
2967 ld 29, VCPU_GPRS_TM(29)(r31)
2968 ld 30, VCPU_GPRS_TM(30)(r31)
2969 ld 31, VCPU_GPRS_TM(31)(r31)
2971 /* TM checkpointed state is now setup. All GPRs are now volatile. */
2974 /* Now let's get back the state we need. */
2977 ld r29, HSTATE_DSCR(r13)
2978 mtspr SPRN_DSCR, r29
2979 ld r4, HSTATE_KVM_VCPU(r13)
2980 ld r1, HSTATE_HOST_R1(r13)
2981 ld r2, PACATMSCRATCH(r13)
2983 /* Set the MSR RI since we have our registers back. */
2987 ld r0, PPC_LR_STKOFF(r1)
2993 * We come here if we get any exception or interrupt while we are
2994 * executing host real mode code while in guest MMU context.
2995 * For now just spin, but we should do something better.
2997 kvmppc_bad_host_intr:
3001 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3002 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3003 * r11 has the guest MSR value (in/out)
3004 * r9 has a vcpu pointer (in)
3005 * r0 is used as a scratch register
3007 kvmppc_msr_interrupt:
3008 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3009 cmpwi r0, 2 /* Check if we are in transactional state.. */
3010 ld r11, VCPU_INTR_MSR(r9)
3012 /* ... if transactional, change to suspended */
3014 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3018 * This works around a hardware bug on POWER8E processors, where
3019 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3020 * performance monitor interrupt. Instead, when we need to have
3021 * an interrupt pending, we have to arrange for a counter to overflow.
3025 mtspr SPRN_MMCR2, r3
3026 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3027 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3028 mtspr SPRN_MMCR0, r3
3035 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3037 * Start timing an activity
3038 * r3 = pointer to time accumulation struct, r4 = vcpu
3041 ld r5, HSTATE_KVM_VCORE(r13)
3042 lbz r6, VCORE_IN_GUEST(r5)
3044 beq 5f /* if in guest, need to */
3045 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3048 std r3, VCPU_CUR_ACTIVITY(r4)
3049 std r5, VCPU_ACTIVITY_START(r4)
3053 * Accumulate time to one activity and start another.
3054 * r3 = pointer to new time accumulation struct, r4 = vcpu
3056 kvmhv_accumulate_time:
3057 ld r5, HSTATE_KVM_VCORE(r13)
3058 lbz r8, VCORE_IN_GUEST(r5)
3060 beq 4f /* if in guest, need to */
3061 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3062 4: ld r5, VCPU_CUR_ACTIVITY(r4)
3063 ld r6, VCPU_ACTIVITY_START(r4)
3064 std r3, VCPU_CUR_ACTIVITY(r4)
3067 std r7, VCPU_ACTIVITY_START(r4)
3071 ld r8, TAS_SEQCOUNT(r5)
3074 std r8, TAS_SEQCOUNT(r5)
3076 ld r7, TAS_TOTAL(r5)
3078 std r7, TAS_TOTAL(r5)
3084 3: std r3, TAS_MIN(r5)
3090 std r8, TAS_SEQCOUNT(r5)
projects / mirror_ubuntu-bionic-kernel.git / blob