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1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
12 *
13 * Derived from book3s_rmhandlers.S and other files, which are:
14 *
15 * Copyright SUSE Linux Products GmbH 2009
16 *
17 * Authors: Alexander Graf <agraf@suse.de>
18 */
19
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/reg.h>
23 #include <asm/mmu.h>
24 #include <asm/page.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30
31 /*****************************************************************************
32 * *
33 * Real Mode handlers that need to be in the linear mapping *
34 * *
35 ****************************************************************************/
36
37 .globl kvmppc_skip_interrupt
38 kvmppc_skip_interrupt:
39 mfspr r13,SPRN_SRR0
40 addi r13,r13,4
41 mtspr SPRN_SRR0,r13
42 GET_SCRATCH0(r13)
43 rfid
44 b .
45
46 .globl kvmppc_skip_Hinterrupt
47 kvmppc_skip_Hinterrupt:
48 mfspr r13,SPRN_HSRR0
49 addi r13,r13,4
50 mtspr SPRN_HSRR0,r13
51 GET_SCRATCH0(r13)
52 hrfid
53 b .
54
55 /*
56 * Call kvmppc_hv_entry in real mode.
57 * Must be called with interrupts hard-disabled.
58 *
59 * Input Registers:
60 *
61 * LR = return address to continue at after eventually re-enabling MMU
62 */
63 _GLOBAL(kvmppc_hv_entry_trampoline)
64 mfmsr r10
65 LOAD_REG_ADDR(r5, kvmppc_hv_entry)
66 li r0,MSR_RI
67 andc r0,r10,r0
68 li r6,MSR_IR | MSR_DR
69 andc r6,r10,r6
70 mtmsrd r0,1 /* clear RI in MSR */
71 mtsrr0 r5
72 mtsrr1 r6
73 RFI
74
75 /******************************************************************************
76 * *
77 * Entry code *
78 * *
79 *****************************************************************************/
80
81 #define XICS_XIRR 4
82 #define XICS_QIRR 0xc
83 #define XICS_IPI 2 /* interrupt source # for IPIs */
84
85 /*
86 * We come in here when wakened from nap mode on a secondary hw thread.
87 * Relocation is off and most register values are lost.
88 * r13 points to the PACA.
89 */
90 .globl kvm_start_guest
91 kvm_start_guest:
92 ld r1,PACAEMERGSP(r13)
93 subi r1,r1,STACK_FRAME_OVERHEAD
94 ld r2,PACATOC(r13)
95
96 li r0,KVM_HWTHREAD_IN_KVM
97 stb r0,HSTATE_HWTHREAD_STATE(r13)
98
99 /* NV GPR values from power7_idle() will no longer be valid */
100 li r0,1
101 stb r0,PACA_NAPSTATELOST(r13)
102
103 /* get vcpu pointer, NULL if we have no vcpu to run */
104 ld r4,HSTATE_KVM_VCPU(r13)
105 cmpdi cr1,r4,0
106
107 /* Check the wake reason in SRR1 to see why we got here */
108 mfspr r3,SPRN_SRR1
109 rlwinm r3,r3,44-31,0x7 /* extract wake reason field */
110 cmpwi r3,4 /* was it an external interrupt? */
111 bne 27f
112
113 /*
114 * External interrupt - for now assume it is an IPI, since we
115 * should never get any other interrupts sent to offline threads.
116 * Only do this for secondary threads.
117 */
118 beq cr1,25f
119 lwz r3,VCPU_PTID(r4)
120 cmpwi r3,0
121 beq 27f
122 25: ld r5,HSTATE_XICS_PHYS(r13)
123 li r0,0xff
124 li r6,XICS_QIRR
125 li r7,XICS_XIRR
126 lwzcix r8,r5,r7 /* get and ack the interrupt */
127 sync
128 clrldi. r9,r8,40 /* get interrupt source ID. */
129 beq 27f /* none there? */
130 cmpwi r9,XICS_IPI
131 bne 26f
132 stbcix r0,r5,r6 /* clear IPI */
133 26: stwcix r8,r5,r7 /* EOI the interrupt */
134
135 27: /* XXX should handle hypervisor maintenance interrupts etc. here */
136
137 /* reload vcpu pointer after clearing the IPI */
138 ld r4,HSTATE_KVM_VCPU(r13)
139 cmpdi r4,0
140 /* if we have no vcpu to run, go back to sleep */
141 beq kvm_no_guest
142
143 /* were we napping due to cede? */
144 lbz r0,HSTATE_NAPPING(r13)
145 cmpwi r0,0
146 bne kvm_end_cede
147
148 .global kvmppc_hv_entry
149 kvmppc_hv_entry:
150
151 /* Required state:
152 *
153 * R4 = vcpu pointer
154 * MSR = ~IR|DR
155 * R13 = PACA
156 * R1 = host R1
157 * all other volatile GPRS = free
158 */
159 mflr r0
160 std r0, HSTATE_VMHANDLER(r13)
161
162 /* Set partition DABR */
163 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
164 li r5,3
165 ld r6,VCPU_DABR(r4)
166 mtspr SPRN_DABRX,r5
167 mtspr SPRN_DABR,r6
168 BEGIN_FTR_SECTION
169 isync
170 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
171
172 /* Load guest PMU registers */
173 /* R4 is live here (vcpu pointer) */
174 li r3, 1
175 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
176 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
177 isync
178 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
179 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
180 lwz r6, VCPU_PMC + 8(r4)
181 lwz r7, VCPU_PMC + 12(r4)
182 lwz r8, VCPU_PMC + 16(r4)
183 lwz r9, VCPU_PMC + 20(r4)
184 BEGIN_FTR_SECTION
185 lwz r10, VCPU_PMC + 24(r4)
186 lwz r11, VCPU_PMC + 28(r4)
187 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
188 mtspr SPRN_PMC1, r3
189 mtspr SPRN_PMC2, r5
190 mtspr SPRN_PMC3, r6
191 mtspr SPRN_PMC4, r7
192 mtspr SPRN_PMC5, r8
193 mtspr SPRN_PMC6, r9
194 BEGIN_FTR_SECTION
195 mtspr SPRN_PMC7, r10
196 mtspr SPRN_PMC8, r11
197 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
198 ld r3, VCPU_MMCR(r4)
199 ld r5, VCPU_MMCR + 8(r4)
200 ld r6, VCPU_MMCR + 16(r4)
201 mtspr SPRN_MMCR1, r5
202 mtspr SPRN_MMCRA, r6
203 mtspr SPRN_MMCR0, r3
204 isync
205
206 /* Load up FP, VMX and VSX registers */
207 bl kvmppc_load_fp
208
209 ld r14, VCPU_GPR(R14)(r4)
210 ld r15, VCPU_GPR(R15)(r4)
211 ld r16, VCPU_GPR(R16)(r4)
212 ld r17, VCPU_GPR(R17)(r4)
213 ld r18, VCPU_GPR(R18)(r4)
214 ld r19, VCPU_GPR(R19)(r4)
215 ld r20, VCPU_GPR(R20)(r4)
216 ld r21, VCPU_GPR(R21)(r4)
217 ld r22, VCPU_GPR(R22)(r4)
218 ld r23, VCPU_GPR(R23)(r4)
219 ld r24, VCPU_GPR(R24)(r4)
220 ld r25, VCPU_GPR(R25)(r4)
221 ld r26, VCPU_GPR(R26)(r4)
222 ld r27, VCPU_GPR(R27)(r4)
223 ld r28, VCPU_GPR(R28)(r4)
224 ld r29, VCPU_GPR(R29)(r4)
225 ld r30, VCPU_GPR(R30)(r4)
226 ld r31, VCPU_GPR(R31)(r4)
227
228 BEGIN_FTR_SECTION
229 /* Switch DSCR to guest value */
230 ld r5, VCPU_DSCR(r4)
231 mtspr SPRN_DSCR, r5
232 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
233
234 /*
235 * Set the decrementer to the guest decrementer.
236 */
237 ld r8,VCPU_DEC_EXPIRES(r4)
238 mftb r7
239 subf r3,r7,r8
240 mtspr SPRN_DEC,r3
241 stw r3,VCPU_DEC(r4)
242
243 ld r5, VCPU_SPRG0(r4)
244 ld r6, VCPU_SPRG1(r4)
245 ld r7, VCPU_SPRG2(r4)
246 ld r8, VCPU_SPRG3(r4)
247 mtspr SPRN_SPRG0, r5
248 mtspr SPRN_SPRG1, r6
249 mtspr SPRN_SPRG2, r7
250 mtspr SPRN_SPRG3, r8
251
252 /* Save R1 in the PACA */
253 std r1, HSTATE_HOST_R1(r13)
254
255 /* Increment yield count if they have a VPA */
256 ld r3, VCPU_VPA(r4)
257 cmpdi r3, 0
258 beq 25f
259 lwz r5, LPPACA_YIELDCOUNT(r3)
260 addi r5, r5, 1
261 stw r5, LPPACA_YIELDCOUNT(r3)
262 25:
263 /* Load up DAR and DSISR */
264 ld r5, VCPU_DAR(r4)
265 lwz r6, VCPU_DSISR(r4)
266 mtspr SPRN_DAR, r5
267 mtspr SPRN_DSISR, r6
268
269 BEGIN_FTR_SECTION
270 /* Restore AMR and UAMOR, set AMOR to all 1s */
271 ld r5,VCPU_AMR(r4)
272 ld r6,VCPU_UAMOR(r4)
273 li r7,-1
274 mtspr SPRN_AMR,r5
275 mtspr SPRN_UAMOR,r6
276 mtspr SPRN_AMOR,r7
277 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
278
279 /* Clear out SLB */
280 li r6,0
281 slbmte r6,r6
282 slbia
283 ptesync
284
285 BEGIN_FTR_SECTION
286 b 30f
287 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
288 /*
289 * POWER7 host -> guest partition switch code.
290 * We don't have to lock against concurrent tlbies,
291 * but we do have to coordinate across hardware threads.
292 */
293 /* Increment entry count iff exit count is zero. */
294 ld r5,HSTATE_KVM_VCORE(r13)
295 addi r9,r5,VCORE_ENTRY_EXIT
296 21: lwarx r3,0,r9
297 cmpwi r3,0x100 /* any threads starting to exit? */
298 bge secondary_too_late /* if so we're too late to the party */
299 addi r3,r3,1
300 stwcx. r3,0,r9
301 bne 21b
302
303 /* Primary thread switches to guest partition. */
304 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
305 lwz r6,VCPU_PTID(r4)
306 cmpwi r6,0
307 bne 20f
308 ld r6,KVM_SDR1(r9)
309 lwz r7,KVM_LPID(r9)
310 li r0,LPID_RSVD /* switch to reserved LPID */
311 mtspr SPRN_LPID,r0
312 ptesync
313 mtspr SPRN_SDR1,r6 /* switch to partition page table */
314 mtspr SPRN_LPID,r7
315 isync
316 li r0,1
317 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
318 b 10f
319
320 /* Secondary threads wait for primary to have done partition switch */
321 20: lbz r0,VCORE_IN_GUEST(r5)
322 cmpwi r0,0
323 beq 20b
324
325 /* Set LPCR and RMOR. */
326 10: ld r8,KVM_LPCR(r9)
327 mtspr SPRN_LPCR,r8
328 ld r8,KVM_RMOR(r9)
329 mtspr SPRN_RMOR,r8
330 isync
331
332 /* Check if HDEC expires soon */
333 mfspr r3,SPRN_HDEC
334 cmpwi r3,10
335 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
336 mr r9,r4
337 blt hdec_soon
338
339 /*
340 * Invalidate the TLB if we could possibly have stale TLB
341 * entries for this partition on this core due to the use
342 * of tlbiel.
343 * XXX maybe only need this on primary thread?
344 */
345 ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
346 lwz r5,VCPU_VCPUID(r4)
347 lhz r6,PACAPACAINDEX(r13)
348 rldimi r6,r5,0,62 /* XXX map as if threads 1:1 p:v */
349 lhz r8,VCPU_LAST_CPU(r4)
350 sldi r7,r6,1 /* see if this is the same vcpu */
351 add r7,r7,r9 /* as last ran on this pcpu */
352 lhz r0,KVM_LAST_VCPU(r7)
353 cmpw r6,r8 /* on the same cpu core as last time? */
354 bne 3f
355 cmpw r0,r5 /* same vcpu as this core last ran? */
356 beq 1f
357 3: sth r6,VCPU_LAST_CPU(r4) /* if not, invalidate partition TLB */
358 sth r5,KVM_LAST_VCPU(r7)
359 li r6,128
360 mtctr r6
361 li r7,0x800 /* IS field = 0b10 */
362 ptesync
363 2: tlbiel r7
364 addi r7,r7,0x1000
365 bdnz 2b
366 ptesync
367 1:
368
369 /* Save purr/spurr */
370 mfspr r5,SPRN_PURR
371 mfspr r6,SPRN_SPURR
372 std r5,HSTATE_PURR(r13)
373 std r6,HSTATE_SPURR(r13)
374 ld r7,VCPU_PURR(r4)
375 ld r8,VCPU_SPURR(r4)
376 mtspr SPRN_PURR,r7
377 mtspr SPRN_SPURR,r8
378 b 31f
379
380 /*
381 * PPC970 host -> guest partition switch code.
382 * We have to lock against concurrent tlbies,
383 * using native_tlbie_lock to lock against host tlbies
384 * and kvm->arch.tlbie_lock to lock against guest tlbies.
385 * We also have to invalidate the TLB since its
386 * entries aren't tagged with the LPID.
387 */
388 30: ld r9,VCPU_KVM(r4) /* pointer to struct kvm */
389
390 /* first take native_tlbie_lock */
391 .section ".toc","aw"
392 toc_tlbie_lock:
393 .tc native_tlbie_lock[TC],native_tlbie_lock
394 .previous
395 ld r3,toc_tlbie_lock@toc(2)
396 lwz r8,PACA_LOCK_TOKEN(r13)
397 24: lwarx r0,0,r3
398 cmpwi r0,0
399 bne 24b
400 stwcx. r8,0,r3
401 bne 24b
402 isync
403
404 ld r7,KVM_LPCR(r9) /* use kvm->arch.lpcr to store HID4 */
405 li r0,0x18f
406 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
407 or r0,r7,r0
408 ptesync
409 sync
410 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
411 isync
412 li r0,0
413 stw r0,0(r3) /* drop native_tlbie_lock */
414
415 /* invalidate the whole TLB */
416 li r0,256
417 mtctr r0
418 li r6,0
419 25: tlbiel r6
420 addi r6,r6,0x1000
421 bdnz 25b
422 ptesync
423
424 /* Take the guest's tlbie_lock */
425 addi r3,r9,KVM_TLBIE_LOCK
426 24: lwarx r0,0,r3
427 cmpwi r0,0
428 bne 24b
429 stwcx. r8,0,r3
430 bne 24b
431 isync
432 ld r6,KVM_SDR1(r9)
433 mtspr SPRN_SDR1,r6 /* switch to partition page table */
434
435 /* Set up HID4 with the guest's LPID etc. */
436 sync
437 mtspr SPRN_HID4,r7
438 isync
439
440 /* drop the guest's tlbie_lock */
441 li r0,0
442 stw r0,0(r3)
443
444 /* Check if HDEC expires soon */
445 mfspr r3,SPRN_HDEC
446 cmpwi r3,10
447 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
448 mr r9,r4
449 blt hdec_soon
450
451 /* Enable HDEC interrupts */
452 mfspr r0,SPRN_HID0
453 li r3,1
454 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
455 sync
456 mtspr SPRN_HID0,r0
457 mfspr r0,SPRN_HID0
458 mfspr r0,SPRN_HID0
459 mfspr r0,SPRN_HID0
460 mfspr r0,SPRN_HID0
461 mfspr r0,SPRN_HID0
462 mfspr r0,SPRN_HID0
463
464 /* Load up guest SLB entries */
465 31: lwz r5,VCPU_SLB_MAX(r4)
466 cmpwi r5,0
467 beq 9f
468 mtctr r5
469 addi r6,r4,VCPU_SLB
470 1: ld r8,VCPU_SLB_E(r6)
471 ld r9,VCPU_SLB_V(r6)
472 slbmte r9,r8
473 addi r6,r6,VCPU_SLB_SIZE
474 bdnz 1b
475 9:
476
477 /* Restore state of CTRL run bit; assume 1 on entry */
478 lwz r5,VCPU_CTRL(r4)
479 andi. r5,r5,1
480 bne 4f
481 mfspr r6,SPRN_CTRLF
482 clrrdi r6,r6,1
483 mtspr SPRN_CTRLT,r6
484 4:
485 ld r6, VCPU_CTR(r4)
486 lwz r7, VCPU_XER(r4)
487
488 mtctr r6
489 mtxer r7
490
491 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
492 ld r6, VCPU_SRR0(r4)
493 ld r7, VCPU_SRR1(r4)
494 ld r10, VCPU_PC(r4)
495 ld r11, VCPU_MSR(r4) /* r11 = vcpu->arch.msr & ~MSR_HV */
496
497 rldicl r11, r11, 63 - MSR_HV_LG, 1
498 rotldi r11, r11, 1 + MSR_HV_LG
499 ori r11, r11, MSR_ME
500
501 /* Check if we can deliver an external or decrementer interrupt now */
502 ld r0,VCPU_PENDING_EXC(r4)
503 li r8,(1 << BOOK3S_IRQPRIO_EXTERNAL)
504 oris r8,r8,(1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
505 and r0,r0,r8
506 cmpdi cr1,r0,0
507 andi. r0,r11,MSR_EE
508 beq cr1,11f
509 BEGIN_FTR_SECTION
510 mfspr r8,SPRN_LPCR
511 ori r8,r8,LPCR_MER
512 mtspr SPRN_LPCR,r8
513 isync
514 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
515 beq 5f
516 li r0,BOOK3S_INTERRUPT_EXTERNAL
517 12: mr r6,r10
518 mr r10,r0
519 mr r7,r11
520 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
521 rotldi r11,r11,63
522 b 5f
523 11: beq 5f
524 mfspr r0,SPRN_DEC
525 cmpwi r0,0
526 li r0,BOOK3S_INTERRUPT_DECREMENTER
527 blt 12b
528
529 /* Move SRR0 and SRR1 into the respective regs */
530 5: mtspr SPRN_SRR0, r6
531 mtspr SPRN_SRR1, r7
532 li r0,0
533 stb r0,VCPU_CEDED(r4) /* cancel cede */
534
535 fast_guest_return:
536 mtspr SPRN_HSRR0,r10
537 mtspr SPRN_HSRR1,r11
538
539 /* Activate guest mode, so faults get handled by KVM */
540 li r9, KVM_GUEST_MODE_GUEST
541 stb r9, HSTATE_IN_GUEST(r13)
542
543 /* Enter guest */
544
545 ld r5, VCPU_LR(r4)
546 lwz r6, VCPU_CR(r4)
547 mtlr r5
548 mtcr r6
549
550 ld r0, VCPU_GPR(R0)(r4)
551 ld r1, VCPU_GPR(R1)(r4)
552 ld r2, VCPU_GPR(R2)(r4)
553 ld r3, VCPU_GPR(R3)(r4)
554 ld r5, VCPU_GPR(R5)(r4)
555 ld r6, VCPU_GPR(R6)(r4)
556 ld r7, VCPU_GPR(R7)(r4)
557 ld r8, VCPU_GPR(R8)(r4)
558 ld r9, VCPU_GPR(R9)(r4)
559 ld r10, VCPU_GPR(R10)(r4)
560 ld r11, VCPU_GPR(R11)(r4)
561 ld r12, VCPU_GPR(R12)(r4)
562 ld r13, VCPU_GPR(R13)(r4)
563
564 ld r4, VCPU_GPR(R4)(r4)
565
566 hrfid
567 b .
568
569 /******************************************************************************
570 * *
571 * Exit code *
572 * *
573 *****************************************************************************/
574
575 /*
576 * We come here from the first-level interrupt handlers.
577 */
578 .globl kvmppc_interrupt
579 kvmppc_interrupt:
580 /*
581 * Register contents:
582 * R12 = interrupt vector
583 * R13 = PACA
584 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
585 * guest R13 saved in SPRN_SCRATCH0
586 */
587 /* abuse host_r2 as third scratch area; we get r2 from PACATOC(r13) */
588 std r9, HSTATE_HOST_R2(r13)
589 ld r9, HSTATE_KVM_VCPU(r13)
590
591 /* Save registers */
592
593 std r0, VCPU_GPR(R0)(r9)
594 std r1, VCPU_GPR(R1)(r9)
595 std r2, VCPU_GPR(R2)(r9)
596 std r3, VCPU_GPR(R3)(r9)
597 std r4, VCPU_GPR(R4)(r9)
598 std r5, VCPU_GPR(R5)(r9)
599 std r6, VCPU_GPR(R6)(r9)
600 std r7, VCPU_GPR(R7)(r9)
601 std r8, VCPU_GPR(R8)(r9)
602 ld r0, HSTATE_HOST_R2(r13)
603 std r0, VCPU_GPR(R9)(r9)
604 std r10, VCPU_GPR(R10)(r9)
605 std r11, VCPU_GPR(R11)(r9)
606 ld r3, HSTATE_SCRATCH0(r13)
607 lwz r4, HSTATE_SCRATCH1(r13)
608 std r3, VCPU_GPR(R12)(r9)
609 stw r4, VCPU_CR(r9)
610
611 /* Restore R1/R2 so we can handle faults */
612 ld r1, HSTATE_HOST_R1(r13)
613 ld r2, PACATOC(r13)
614
615 mfspr r10, SPRN_SRR0
616 mfspr r11, SPRN_SRR1
617 std r10, VCPU_SRR0(r9)
618 std r11, VCPU_SRR1(r9)
619 andi. r0, r12, 2 /* need to read HSRR0/1? */
620 beq 1f
621 mfspr r10, SPRN_HSRR0
622 mfspr r11, SPRN_HSRR1
623 clrrdi r12, r12, 2
624 1: std r10, VCPU_PC(r9)
625 std r11, VCPU_MSR(r9)
626
627 GET_SCRATCH0(r3)
628 mflr r4
629 std r3, VCPU_GPR(R13)(r9)
630 std r4, VCPU_LR(r9)
631
632 /* Unset guest mode */
633 li r0, KVM_GUEST_MODE_NONE
634 stb r0, HSTATE_IN_GUEST(r13)
635
636 stw r12,VCPU_TRAP(r9)
637
638 /* Save HEIR (HV emulation assist reg) in last_inst
639 if this is an HEI (HV emulation interrupt, e40) */
640 li r3,KVM_INST_FETCH_FAILED
641 BEGIN_FTR_SECTION
642 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
643 bne 11f
644 mfspr r3,SPRN_HEIR
645 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
646 11: stw r3,VCPU_LAST_INST(r9)
647
648 /* these are volatile across C function calls */
649 mfctr r3
650 mfxer r4
651 std r3, VCPU_CTR(r9)
652 stw r4, VCPU_XER(r9)
653
654 BEGIN_FTR_SECTION
655 /* If this is a page table miss then see if it's theirs or ours */
656 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
657 beq kvmppc_hdsi
658 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
659 beq kvmppc_hisi
660 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
661
662 /* See if this is a leftover HDEC interrupt */
663 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
664 bne 2f
665 mfspr r3,SPRN_HDEC
666 cmpwi r3,0
667 bge ignore_hdec
668 2:
669 /* See if this is an hcall we can handle in real mode */
670 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
671 beq hcall_try_real_mode
672
673 /* Check for mediated interrupts (could be done earlier really ...) */
674 BEGIN_FTR_SECTION
675 cmpwi r12,BOOK3S_INTERRUPT_EXTERNAL
676 bne+ 1f
677 andi. r0,r11,MSR_EE
678 beq 1f
679 mfspr r5,SPRN_LPCR
680 andi. r0,r5,LPCR_MER
681 bne bounce_ext_interrupt
682 1:
683 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
684
685 nohpte_cont:
686 hcall_real_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
687 /* Save DEC */
688 mfspr r5,SPRN_DEC
689 mftb r6
690 extsw r5,r5
691 add r5,r5,r6
692 std r5,VCPU_DEC_EXPIRES(r9)
693
694 /* Save more register state */
695 mfdar r6
696 mfdsisr r7
697 std r6, VCPU_DAR(r9)
698 stw r7, VCPU_DSISR(r9)
699 BEGIN_FTR_SECTION
700 /* don't overwrite fault_dar/fault_dsisr if HDSI */
701 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
702 beq 6f
703 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
704 std r6, VCPU_FAULT_DAR(r9)
705 stw r7, VCPU_FAULT_DSISR(r9)
706
707 /* Save guest CTRL register, set runlatch to 1 */
708 6: mfspr r6,SPRN_CTRLF
709 stw r6,VCPU_CTRL(r9)
710 andi. r0,r6,1
711 bne 4f
712 ori r6,r6,1
713 mtspr SPRN_CTRLT,r6
714 4:
715 /* Read the guest SLB and save it away */
716 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
717 mtctr r0
718 li r6,0
719 addi r7,r9,VCPU_SLB
720 li r5,0
721 1: slbmfee r8,r6
722 andis. r0,r8,SLB_ESID_V@h
723 beq 2f
724 add r8,r8,r6 /* put index in */
725 slbmfev r3,r6
726 std r8,VCPU_SLB_E(r7)
727 std r3,VCPU_SLB_V(r7)
728 addi r7,r7,VCPU_SLB_SIZE
729 addi r5,r5,1
730 2: addi r6,r6,1
731 bdnz 1b
732 stw r5,VCPU_SLB_MAX(r9)
733
734 /*
735 * Save the guest PURR/SPURR
736 */
737 BEGIN_FTR_SECTION
738 mfspr r5,SPRN_PURR
739 mfspr r6,SPRN_SPURR
740 ld r7,VCPU_PURR(r9)
741 ld r8,VCPU_SPURR(r9)
742 std r5,VCPU_PURR(r9)
743 std r6,VCPU_SPURR(r9)
744 subf r5,r7,r5
745 subf r6,r8,r6
746
747 /*
748 * Restore host PURR/SPURR and add guest times
749 * so that the time in the guest gets accounted.
750 */
751 ld r3,HSTATE_PURR(r13)
752 ld r4,HSTATE_SPURR(r13)
753 add r3,r3,r5
754 add r4,r4,r6
755 mtspr SPRN_PURR,r3
756 mtspr SPRN_SPURR,r4
757 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
758
759 /* Clear out SLB */
760 li r5,0
761 slbmte r5,r5
762 slbia
763 ptesync
764
765 hdec_soon: /* r9 = vcpu, r12 = trap, r13 = paca */
766 BEGIN_FTR_SECTION
767 b 32f
768 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
769 /*
770 * POWER7 guest -> host partition switch code.
771 * We don't have to lock against tlbies but we do
772 * have to coordinate the hardware threads.
773 */
774 /* Increment the threads-exiting-guest count in the 0xff00
775 bits of vcore->entry_exit_count */
776 lwsync
777 ld r5,HSTATE_KVM_VCORE(r13)
778 addi r6,r5,VCORE_ENTRY_EXIT
779 41: lwarx r3,0,r6
780 addi r0,r3,0x100
781 stwcx. r0,0,r6
782 bne 41b
783 lwsync
784
785 /*
786 * At this point we have an interrupt that we have to pass
787 * up to the kernel or qemu; we can't handle it in real mode.
788 * Thus we have to do a partition switch, so we have to
789 * collect the other threads, if we are the first thread
790 * to take an interrupt. To do this, we set the HDEC to 0,
791 * which causes an HDEC interrupt in all threads within 2ns
792 * because the HDEC register is shared between all 4 threads.
793 * However, we don't need to bother if this is an HDEC
794 * interrupt, since the other threads will already be on their
795 * way here in that case.
796 */
797 cmpwi r3,0x100 /* Are we the first here? */
798 bge 43f
799 cmpwi r3,1 /* Are any other threads in the guest? */
800 ble 43f
801 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
802 beq 40f
803 li r0,0
804 mtspr SPRN_HDEC,r0
805 40:
806 /*
807 * Send an IPI to any napping threads, since an HDEC interrupt
808 * doesn't wake CPUs up from nap.
809 */
810 lwz r3,VCORE_NAPPING_THREADS(r5)
811 lwz r4,VCPU_PTID(r9)
812 li r0,1
813 sld r0,r0,r4
814 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
815 beq 43f
816 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
817 subf r6,r4,r13
818 42: andi. r0,r3,1
819 beq 44f
820 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
821 li r0,IPI_PRIORITY
822 li r7,XICS_QIRR
823 stbcix r0,r7,r8 /* trigger the IPI */
824 44: srdi. r3,r3,1
825 addi r6,r6,PACA_SIZE
826 bne 42b
827
828 /* Secondary threads wait for primary to do partition switch */
829 43: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
830 ld r5,HSTATE_KVM_VCORE(r13)
831 lwz r3,VCPU_PTID(r9)
832 cmpwi r3,0
833 beq 15f
834 HMT_LOW
835 13: lbz r3,VCORE_IN_GUEST(r5)
836 cmpwi r3,0
837 bne 13b
838 HMT_MEDIUM
839 b 16f
840
841 /* Primary thread waits for all the secondaries to exit guest */
842 15: lwz r3,VCORE_ENTRY_EXIT(r5)
843 srwi r0,r3,8
844 clrldi r3,r3,56
845 cmpw r3,r0
846 bne 15b
847 isync
848
849 /* Primary thread switches back to host partition */
850 ld r6,KVM_HOST_SDR1(r4)
851 lwz r7,KVM_HOST_LPID(r4)
852 li r8,LPID_RSVD /* switch to reserved LPID */
853 mtspr SPRN_LPID,r8
854 ptesync
855 mtspr SPRN_SDR1,r6 /* switch to partition page table */
856 mtspr SPRN_LPID,r7
857 isync
858 li r0,0
859 stb r0,VCORE_IN_GUEST(r5)
860 lis r8,0x7fff /* MAX_INT@h */
861 mtspr SPRN_HDEC,r8
862
863 16: ld r8,KVM_HOST_LPCR(r4)
864 mtspr SPRN_LPCR,r8
865 isync
866 b 33f
867
868 /*
869 * PPC970 guest -> host partition switch code.
870 * We have to lock against concurrent tlbies, and
871 * we have to flush the whole TLB.
872 */
873 32: ld r4,VCPU_KVM(r9) /* pointer to struct kvm */
874
875 /* Take the guest's tlbie_lock */
876 lwz r8,PACA_LOCK_TOKEN(r13)
877 addi r3,r4,KVM_TLBIE_LOCK
878 24: lwarx r0,0,r3
879 cmpwi r0,0
880 bne 24b
881 stwcx. r8,0,r3
882 bne 24b
883 isync
884
885 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
886 li r0,0x18f
887 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
888 or r0,r7,r0
889 ptesync
890 sync
891 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
892 isync
893 li r0,0
894 stw r0,0(r3) /* drop guest tlbie_lock */
895
896 /* invalidate the whole TLB */
897 li r0,256
898 mtctr r0
899 li r6,0
900 25: tlbiel r6
901 addi r6,r6,0x1000
902 bdnz 25b
903 ptesync
904
905 /* take native_tlbie_lock */
906 ld r3,toc_tlbie_lock@toc(2)
907 24: lwarx r0,0,r3
908 cmpwi r0,0
909 bne 24b
910 stwcx. r8,0,r3
911 bne 24b
912 isync
913
914 ld r6,KVM_HOST_SDR1(r4)
915 mtspr SPRN_SDR1,r6 /* switch to host page table */
916
917 /* Set up host HID4 value */
918 sync
919 mtspr SPRN_HID4,r7
920 isync
921 li r0,0
922 stw r0,0(r3) /* drop native_tlbie_lock */
923
924 lis r8,0x7fff /* MAX_INT@h */
925 mtspr SPRN_HDEC,r8
926
927 /* Disable HDEC interrupts */
928 mfspr r0,SPRN_HID0
929 li r3,0
930 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
931 sync
932 mtspr SPRN_HID0,r0
933 mfspr r0,SPRN_HID0
934 mfspr r0,SPRN_HID0
935 mfspr r0,SPRN_HID0
936 mfspr r0,SPRN_HID0
937 mfspr r0,SPRN_HID0
938 mfspr r0,SPRN_HID0
939
940 /* load host SLB entries */
941 33: ld r8,PACA_SLBSHADOWPTR(r13)
942
943 .rept SLB_NUM_BOLTED
944 ld r5,SLBSHADOW_SAVEAREA(r8)
945 ld r6,SLBSHADOW_SAVEAREA+8(r8)
946 andis. r7,r5,SLB_ESID_V@h
947 beq 1f
948 slbmte r6,r5
949 1: addi r8,r8,16
950 .endr
951
952 /* Save and reset AMR and UAMOR before turning on the MMU */
953 BEGIN_FTR_SECTION
954 mfspr r5,SPRN_AMR
955 mfspr r6,SPRN_UAMOR
956 std r5,VCPU_AMR(r9)
957 std r6,VCPU_UAMOR(r9)
958 li r6,0
959 mtspr SPRN_AMR,r6
960 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
961
962 /* Switch DSCR back to host value */
963 BEGIN_FTR_SECTION
964 mfspr r8, SPRN_DSCR
965 ld r7, HSTATE_DSCR(r13)
966 std r8, VCPU_DSCR(r7)
967 mtspr SPRN_DSCR, r7
968 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
969
970 /* Save non-volatile GPRs */
971 std r14, VCPU_GPR(R14)(r9)
972 std r15, VCPU_GPR(R15)(r9)
973 std r16, VCPU_GPR(R16)(r9)
974 std r17, VCPU_GPR(R17)(r9)
975 std r18, VCPU_GPR(R18)(r9)
976 std r19, VCPU_GPR(R19)(r9)
977 std r20, VCPU_GPR(R20)(r9)
978 std r21, VCPU_GPR(R21)(r9)
979 std r22, VCPU_GPR(R22)(r9)
980 std r23, VCPU_GPR(R23)(r9)
981 std r24, VCPU_GPR(R24)(r9)
982 std r25, VCPU_GPR(R25)(r9)
983 std r26, VCPU_GPR(R26)(r9)
984 std r27, VCPU_GPR(R27)(r9)
985 std r28, VCPU_GPR(R28)(r9)
986 std r29, VCPU_GPR(R29)(r9)
987 std r30, VCPU_GPR(R30)(r9)
988 std r31, VCPU_GPR(R31)(r9)
989
990 /* Save SPRGs */
991 mfspr r3, SPRN_SPRG0
992 mfspr r4, SPRN_SPRG1
993 mfspr r5, SPRN_SPRG2
994 mfspr r6, SPRN_SPRG3
995 std r3, VCPU_SPRG0(r9)
996 std r4, VCPU_SPRG1(r9)
997 std r5, VCPU_SPRG2(r9)
998 std r6, VCPU_SPRG3(r9)
999
1000 /* save FP state */
1001 mr r3, r9
1002 bl .kvmppc_save_fp
1003
1004 /* Increment yield count if they have a VPA */
1005 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1006 cmpdi r8, 0
1007 beq 25f
1008 lwz r3, LPPACA_YIELDCOUNT(r8)
1009 addi r3, r3, 1
1010 stw r3, LPPACA_YIELDCOUNT(r8)
1011 25:
1012 /* Save PMU registers if requested */
1013 /* r8 and cr0.eq are live here */
1014 li r3, 1
1015 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1016 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1017 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1018 mfspr r6, SPRN_MMCRA
1019 BEGIN_FTR_SECTION
1020 /* On P7, clear MMCRA in order to disable SDAR updates */
1021 li r7, 0
1022 mtspr SPRN_MMCRA, r7
1023 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1024 isync
1025 beq 21f /* if no VPA, save PMU stuff anyway */
1026 lbz r7, LPPACA_PMCINUSE(r8)
1027 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1028 bne 21f
1029 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1030 b 22f
1031 21: mfspr r5, SPRN_MMCR1
1032 std r4, VCPU_MMCR(r9)
1033 std r5, VCPU_MMCR + 8(r9)
1034 std r6, VCPU_MMCR + 16(r9)
1035 mfspr r3, SPRN_PMC1
1036 mfspr r4, SPRN_PMC2
1037 mfspr r5, SPRN_PMC3
1038 mfspr r6, SPRN_PMC4
1039 mfspr r7, SPRN_PMC5
1040 mfspr r8, SPRN_PMC6
1041 BEGIN_FTR_SECTION
1042 mfspr r10, SPRN_PMC7
1043 mfspr r11, SPRN_PMC8
1044 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1045 stw r3, VCPU_PMC(r9)
1046 stw r4, VCPU_PMC + 4(r9)
1047 stw r5, VCPU_PMC + 8(r9)
1048 stw r6, VCPU_PMC + 12(r9)
1049 stw r7, VCPU_PMC + 16(r9)
1050 stw r8, VCPU_PMC + 20(r9)
1051 BEGIN_FTR_SECTION
1052 stw r10, VCPU_PMC + 24(r9)
1053 stw r11, VCPU_PMC + 28(r9)
1054 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1055 22:
1056
1057 /* Secondary threads go off to take a nap on POWER7 */
1058 BEGIN_FTR_SECTION
1059 lwz r0,VCPU_PTID(r9)
1060 cmpwi r0,0
1061 bne secondary_nap
1062 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1063
1064 /* Restore host DABR and DABRX */
1065 ld r5,HSTATE_DABR(r13)
1066 li r6,7
1067 mtspr SPRN_DABR,r5
1068 mtspr SPRN_DABRX,r6
1069
1070 /* Restore SPRG3 */
1071 ld r3,PACA_SPRG3(r13)
1072 mtspr SPRN_SPRG3,r3
1073
1074 /*
1075 * Reload DEC. HDEC interrupts were disabled when
1076 * we reloaded the host's LPCR value.
1077 */
1078 ld r3, HSTATE_DECEXP(r13)
1079 mftb r4
1080 subf r4, r4, r3
1081 mtspr SPRN_DEC, r4
1082
1083 /* Reload the host's PMU registers */
1084 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
1085 lbz r4, LPPACA_PMCINUSE(r3)
1086 cmpwi r4, 0
1087 beq 23f /* skip if not */
1088 lwz r3, HSTATE_PMC(r13)
1089 lwz r4, HSTATE_PMC + 4(r13)
1090 lwz r5, HSTATE_PMC + 8(r13)
1091 lwz r6, HSTATE_PMC + 12(r13)
1092 lwz r8, HSTATE_PMC + 16(r13)
1093 lwz r9, HSTATE_PMC + 20(r13)
1094 BEGIN_FTR_SECTION
1095 lwz r10, HSTATE_PMC + 24(r13)
1096 lwz r11, HSTATE_PMC + 28(r13)
1097 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1098 mtspr SPRN_PMC1, r3
1099 mtspr SPRN_PMC2, r4
1100 mtspr SPRN_PMC3, r5
1101 mtspr SPRN_PMC4, r6
1102 mtspr SPRN_PMC5, r8
1103 mtspr SPRN_PMC6, r9
1104 BEGIN_FTR_SECTION
1105 mtspr SPRN_PMC7, r10
1106 mtspr SPRN_PMC8, r11
1107 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1108 ld r3, HSTATE_MMCR(r13)
1109 ld r4, HSTATE_MMCR + 8(r13)
1110 ld r5, HSTATE_MMCR + 16(r13)
1111 mtspr SPRN_MMCR1, r4
1112 mtspr SPRN_MMCRA, r5
1113 mtspr SPRN_MMCR0, r3
1114 isync
1115 23:
1116 /*
1117 * For external and machine check interrupts, we need
1118 * to call the Linux handler to process the interrupt.
1119 * We do that by jumping to the interrupt vector address
1120 * which we have in r12. The [h]rfid at the end of the
1121 * handler will return to the book3s_hv_interrupts.S code.
1122 * For other interrupts we do the rfid to get back
1123 * to the book3s_interrupts.S code here.
1124 */
1125 ld r8, HSTATE_VMHANDLER(r13)
1126 ld r7, HSTATE_HOST_MSR(r13)
1127
1128 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1129 beq 11f
1130 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1131
1132 /* RFI into the highmem handler, or branch to interrupt handler */
1133 12: mfmsr r6
1134 mtctr r12
1135 li r0, MSR_RI
1136 andc r6, r6, r0
1137 mtmsrd r6, 1 /* Clear RI in MSR */
1138 mtsrr0 r8
1139 mtsrr1 r7
1140 beqctr
1141 RFI
1142
1143 11:
1144 BEGIN_FTR_SECTION
1145 b 12b
1146 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1147 mtspr SPRN_HSRR0, r8
1148 mtspr SPRN_HSRR1, r7
1149 ba 0x500
1150
1151 /*
1152 * Check whether an HDSI is an HPTE not found fault or something else.
1153 * If it is an HPTE not found fault that is due to the guest accessing
1154 * a page that they have mapped but which we have paged out, then
1155 * we continue on with the guest exit path. In all other cases,
1156 * reflect the HDSI to the guest as a DSI.
1157 */
1158 kvmppc_hdsi:
1159 mfspr r4, SPRN_HDAR
1160 mfspr r6, SPRN_HDSISR
1161 /* HPTE not found fault or protection fault? */
1162 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1163 beq 1f /* if not, send it to the guest */
1164 andi. r0, r11, MSR_DR /* data relocation enabled? */
1165 beq 3f
1166 clrrdi r0, r4, 28
1167 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1168 bne 1f /* if no SLB entry found */
1169 4: std r4, VCPU_FAULT_DAR(r9)
1170 stw r6, VCPU_FAULT_DSISR(r9)
1171
1172 /* Search the hash table. */
1173 mr r3, r9 /* vcpu pointer */
1174 li r7, 1 /* data fault */
1175 bl .kvmppc_hpte_hv_fault
1176 ld r9, HSTATE_KVM_VCPU(r13)
1177 ld r10, VCPU_PC(r9)
1178 ld r11, VCPU_MSR(r9)
1179 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1180 cmpdi r3, 0 /* retry the instruction */
1181 beq 6f
1182 cmpdi r3, -1 /* handle in kernel mode */
1183 beq nohpte_cont
1184 cmpdi r3, -2 /* MMIO emulation; need instr word */
1185 beq 2f
1186
1187 /* Synthesize a DSI for the guest */
1188 ld r4, VCPU_FAULT_DAR(r9)
1189 mr r6, r3
1190 1: mtspr SPRN_DAR, r4
1191 mtspr SPRN_DSISR, r6
1192 mtspr SPRN_SRR0, r10
1193 mtspr SPRN_SRR1, r11
1194 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1195 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1196 rotldi r11, r11, 63
1197 6: ld r7, VCPU_CTR(r9)
1198 lwz r8, VCPU_XER(r9)
1199 mtctr r7
1200 mtxer r8
1201 mr r4, r9
1202 b fast_guest_return
1203
1204 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1205 ld r5, KVM_VRMA_SLB_V(r5)
1206 b 4b
1207
1208 /* If this is for emulated MMIO, load the instruction word */
1209 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1210
1211 /* Set guest mode to 'jump over instruction' so if lwz faults
1212 * we'll just continue at the next IP. */
1213 li r0, KVM_GUEST_MODE_SKIP
1214 stb r0, HSTATE_IN_GUEST(r13)
1215
1216 /* Do the access with MSR:DR enabled */
1217 mfmsr r3
1218 ori r4, r3, MSR_DR /* Enable paging for data */
1219 mtmsrd r4
1220 lwz r8, 0(r10)
1221 mtmsrd r3
1222
1223 /* Store the result */
1224 stw r8, VCPU_LAST_INST(r9)
1225
1226 /* Unset guest mode. */
1227 li r0, KVM_GUEST_MODE_NONE
1228 stb r0, HSTATE_IN_GUEST(r13)
1229 b nohpte_cont
1230
1231 /*
1232 * Similarly for an HISI, reflect it to the guest as an ISI unless
1233 * it is an HPTE not found fault for a page that we have paged out.
1234 */
1235 kvmppc_hisi:
1236 andis. r0, r11, SRR1_ISI_NOPT@h
1237 beq 1f
1238 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1239 beq 3f
1240 clrrdi r0, r10, 28
1241 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1242 bne 1f /* if no SLB entry found */
1243 4:
1244 /* Search the hash table. */
1245 mr r3, r9 /* vcpu pointer */
1246 mr r4, r10
1247 mr r6, r11
1248 li r7, 0 /* instruction fault */
1249 bl .kvmppc_hpte_hv_fault
1250 ld r9, HSTATE_KVM_VCPU(r13)
1251 ld r10, VCPU_PC(r9)
1252 ld r11, VCPU_MSR(r9)
1253 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1254 cmpdi r3, 0 /* retry the instruction */
1255 beq 6f
1256 cmpdi r3, -1 /* handle in kernel mode */
1257 beq nohpte_cont
1258
1259 /* Synthesize an ISI for the guest */
1260 mr r11, r3
1261 1: mtspr SPRN_SRR0, r10
1262 mtspr SPRN_SRR1, r11
1263 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1264 li r11, (MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1265 rotldi r11, r11, 63
1266 6: ld r7, VCPU_CTR(r9)
1267 lwz r8, VCPU_XER(r9)
1268 mtctr r7
1269 mtxer r8
1270 mr r4, r9
1271 b fast_guest_return
1272
1273 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1274 ld r5, KVM_VRMA_SLB_V(r6)
1275 b 4b
1276
1277 /*
1278 * Try to handle an hcall in real mode.
1279 * Returns to the guest if we handle it, or continues on up to
1280 * the kernel if we can't (i.e. if we don't have a handler for
1281 * it, or if the handler returns H_TOO_HARD).
1282 */
1283 .globl hcall_try_real_mode
1284 hcall_try_real_mode:
1285 ld r3,VCPU_GPR(R3)(r9)
1286 andi. r0,r11,MSR_PR
1287 bne hcall_real_cont
1288 clrrdi r3,r3,2
1289 cmpldi r3,hcall_real_table_end - hcall_real_table
1290 bge hcall_real_cont
1291 LOAD_REG_ADDR(r4, hcall_real_table)
1292 lwzx r3,r3,r4
1293 cmpwi r3,0
1294 beq hcall_real_cont
1295 add r3,r3,r4
1296 mtctr r3
1297 mr r3,r9 /* get vcpu pointer */
1298 ld r4,VCPU_GPR(R4)(r9)
1299 bctrl
1300 cmpdi r3,H_TOO_HARD
1301 beq hcall_real_fallback
1302 ld r4,HSTATE_KVM_VCPU(r13)
1303 std r3,VCPU_GPR(R3)(r4)
1304 ld r10,VCPU_PC(r4)
1305 ld r11,VCPU_MSR(r4)
1306 b fast_guest_return
1307
1308 /* We've attempted a real mode hcall, but it's punted it back
1309 * to userspace. We need to restore some clobbered volatiles
1310 * before resuming the pass-it-to-qemu path */
1311 hcall_real_fallback:
1312 li r12,BOOK3S_INTERRUPT_SYSCALL
1313 ld r9, HSTATE_KVM_VCPU(r13)
1314
1315 b hcall_real_cont
1316
1317 .globl hcall_real_table
1318 hcall_real_table:
1319 .long 0 /* 0 - unused */
1320 .long .kvmppc_h_remove - hcall_real_table
1321 .long .kvmppc_h_enter - hcall_real_table
1322 .long .kvmppc_h_read - hcall_real_table
1323 .long 0 /* 0x10 - H_CLEAR_MOD */
1324 .long 0 /* 0x14 - H_CLEAR_REF */
1325 .long .kvmppc_h_protect - hcall_real_table
1326 .long 0 /* 0x1c - H_GET_TCE */
1327 .long .kvmppc_h_put_tce - hcall_real_table
1328 .long 0 /* 0x24 - H_SET_SPRG0 */
1329 .long .kvmppc_h_set_dabr - hcall_real_table
1330 .long 0 /* 0x2c */
1331 .long 0 /* 0x30 */
1332 .long 0 /* 0x34 */
1333 .long 0 /* 0x38 */
1334 .long 0 /* 0x3c */
1335 .long 0 /* 0x40 */
1336 .long 0 /* 0x44 */
1337 .long 0 /* 0x48 */
1338 .long 0 /* 0x4c */
1339 .long 0 /* 0x50 */
1340 .long 0 /* 0x54 */
1341 .long 0 /* 0x58 */
1342 .long 0 /* 0x5c */
1343 .long 0 /* 0x60 */
1344 .long 0 /* 0x64 */
1345 .long 0 /* 0x68 */
1346 .long 0 /* 0x6c */
1347 .long 0 /* 0x70 */
1348 .long 0 /* 0x74 */
1349 .long 0 /* 0x78 */
1350 .long 0 /* 0x7c */
1351 .long 0 /* 0x80 */
1352 .long 0 /* 0x84 */
1353 .long 0 /* 0x88 */
1354 .long 0 /* 0x8c */
1355 .long 0 /* 0x90 */
1356 .long 0 /* 0x94 */
1357 .long 0 /* 0x98 */
1358 .long 0 /* 0x9c */
1359 .long 0 /* 0xa0 */
1360 .long 0 /* 0xa4 */
1361 .long 0 /* 0xa8 */
1362 .long 0 /* 0xac */
1363 .long 0 /* 0xb0 */
1364 .long 0 /* 0xb4 */
1365 .long 0 /* 0xb8 */
1366 .long 0 /* 0xbc */
1367 .long 0 /* 0xc0 */
1368 .long 0 /* 0xc4 */
1369 .long 0 /* 0xc8 */
1370 .long 0 /* 0xcc */
1371 .long 0 /* 0xd0 */
1372 .long 0 /* 0xd4 */
1373 .long 0 /* 0xd8 */
1374 .long 0 /* 0xdc */
1375 .long .kvmppc_h_cede - hcall_real_table
1376 .long 0 /* 0xe4 */
1377 .long 0 /* 0xe8 */
1378 .long 0 /* 0xec */
1379 .long 0 /* 0xf0 */
1380 .long 0 /* 0xf4 */
1381 .long 0 /* 0xf8 */
1382 .long 0 /* 0xfc */
1383 .long 0 /* 0x100 */
1384 .long 0 /* 0x104 */
1385 .long 0 /* 0x108 */
1386 .long 0 /* 0x10c */
1387 .long 0 /* 0x110 */
1388 .long 0 /* 0x114 */
1389 .long 0 /* 0x118 */
1390 .long 0 /* 0x11c */
1391 .long 0 /* 0x120 */
1392 .long .kvmppc_h_bulk_remove - hcall_real_table
1393 hcall_real_table_end:
1394
1395 ignore_hdec:
1396 mr r4,r9
1397 b fast_guest_return
1398
1399 bounce_ext_interrupt:
1400 mr r4,r9
1401 mtspr SPRN_SRR0,r10
1402 mtspr SPRN_SRR1,r11
1403 li r10,BOOK3S_INTERRUPT_EXTERNAL
1404 li r11,(MSR_ME << 1) | 1 /* synthesize MSR_SF | MSR_ME */
1405 rotldi r11,r11,63
1406 b fast_guest_return
1407
1408 _GLOBAL(kvmppc_h_set_dabr)
1409 std r4,VCPU_DABR(r3)
1410 /* Work around P7 bug where DABR can get corrupted on mtspr */
1411 1: mtspr SPRN_DABR,r4
1412 mfspr r5, SPRN_DABR
1413 cmpd r4, r5
1414 bne 1b
1415 isync
1416 li r3,0
1417 blr
1418
1419 _GLOBAL(kvmppc_h_cede)
1420 ori r11,r11,MSR_EE
1421 std r11,VCPU_MSR(r3)
1422 li r0,1
1423 stb r0,VCPU_CEDED(r3)
1424 sync /* order setting ceded vs. testing prodded */
1425 lbz r5,VCPU_PRODDED(r3)
1426 cmpwi r5,0
1427 bne kvm_cede_prodded
1428 li r0,0 /* set trap to 0 to say hcall is handled */
1429 stw r0,VCPU_TRAP(r3)
1430 li r0,H_SUCCESS
1431 std r0,VCPU_GPR(R3)(r3)
1432 BEGIN_FTR_SECTION
1433 b kvm_cede_exit /* just send it up to host on 970 */
1434 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1435
1436 /*
1437 * Set our bit in the bitmask of napping threads unless all the
1438 * other threads are already napping, in which case we send this
1439 * up to the host.
1440 */
1441 ld r5,HSTATE_KVM_VCORE(r13)
1442 lwz r6,VCPU_PTID(r3)
1443 lwz r8,VCORE_ENTRY_EXIT(r5)
1444 clrldi r8,r8,56
1445 li r0,1
1446 sld r0,r0,r6
1447 addi r6,r5,VCORE_NAPPING_THREADS
1448 31: lwarx r4,0,r6
1449 or r4,r4,r0
1450 PPC_POPCNTW(R7,R4)
1451 cmpw r7,r8
1452 bge kvm_cede_exit
1453 stwcx. r4,0,r6
1454 bne 31b
1455 li r0,1
1456 stb r0,HSTATE_NAPPING(r13)
1457 /* order napping_threads update vs testing entry_exit_count */
1458 lwsync
1459 mr r4,r3
1460 lwz r7,VCORE_ENTRY_EXIT(r5)
1461 cmpwi r7,0x100
1462 bge 33f /* another thread already exiting */
1463
1464 /*
1465 * Although not specifically required by the architecture, POWER7
1466 * preserves the following registers in nap mode, even if an SMT mode
1467 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1468 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1469 */
1470 /* Save non-volatile GPRs */
1471 std r14, VCPU_GPR(R14)(r3)
1472 std r15, VCPU_GPR(R15)(r3)
1473 std r16, VCPU_GPR(R16)(r3)
1474 std r17, VCPU_GPR(R17)(r3)
1475 std r18, VCPU_GPR(R18)(r3)
1476 std r19, VCPU_GPR(R19)(r3)
1477 std r20, VCPU_GPR(R20)(r3)
1478 std r21, VCPU_GPR(R21)(r3)
1479 std r22, VCPU_GPR(R22)(r3)
1480 std r23, VCPU_GPR(R23)(r3)
1481 std r24, VCPU_GPR(R24)(r3)
1482 std r25, VCPU_GPR(R25)(r3)
1483 std r26, VCPU_GPR(R26)(r3)
1484 std r27, VCPU_GPR(R27)(r3)
1485 std r28, VCPU_GPR(R28)(r3)
1486 std r29, VCPU_GPR(R29)(r3)
1487 std r30, VCPU_GPR(R30)(r3)
1488 std r31, VCPU_GPR(R31)(r3)
1489
1490 /* save FP state */
1491 bl .kvmppc_save_fp
1492
1493 /*
1494 * Take a nap until a decrementer or external interrupt occurs,
1495 * with PECE1 (wake on decr) and PECE0 (wake on external) set in LPCR
1496 */
1497 li r0,1
1498 stb r0,HSTATE_HWTHREAD_REQ(r13)
1499 mfspr r5,SPRN_LPCR
1500 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
1501 mtspr SPRN_LPCR,r5
1502 isync
1503 li r0, 0
1504 std r0, HSTATE_SCRATCH0(r13)
1505 ptesync
1506 ld r0, HSTATE_SCRATCH0(r13)
1507 1: cmpd r0, r0
1508 bne 1b
1509 nap
1510 b .
1511
1512 kvm_end_cede:
1513 /* Woken by external or decrementer interrupt */
1514 ld r1, HSTATE_HOST_R1(r13)
1515
1516 /* load up FP state */
1517 bl kvmppc_load_fp
1518
1519 /* Load NV GPRS */
1520 ld r14, VCPU_GPR(R14)(r4)
1521 ld r15, VCPU_GPR(R15)(r4)
1522 ld r16, VCPU_GPR(R16)(r4)
1523 ld r17, VCPU_GPR(R17)(r4)
1524 ld r18, VCPU_GPR(R18)(r4)
1525 ld r19, VCPU_GPR(R19)(r4)
1526 ld r20, VCPU_GPR(R20)(r4)
1527 ld r21, VCPU_GPR(R21)(r4)
1528 ld r22, VCPU_GPR(R22)(r4)
1529 ld r23, VCPU_GPR(R23)(r4)
1530 ld r24, VCPU_GPR(R24)(r4)
1531 ld r25, VCPU_GPR(R25)(r4)
1532 ld r26, VCPU_GPR(R26)(r4)
1533 ld r27, VCPU_GPR(R27)(r4)
1534 ld r28, VCPU_GPR(R28)(r4)
1535 ld r29, VCPU_GPR(R29)(r4)
1536 ld r30, VCPU_GPR(R30)(r4)
1537 ld r31, VCPU_GPR(R31)(r4)
1538
1539 /* clear our bit in vcore->napping_threads */
1540 33: ld r5,HSTATE_KVM_VCORE(r13)
1541 lwz r3,VCPU_PTID(r4)
1542 li r0,1
1543 sld r0,r0,r3
1544 addi r6,r5,VCORE_NAPPING_THREADS
1545 32: lwarx r7,0,r6
1546 andc r7,r7,r0
1547 stwcx. r7,0,r6
1548 bne 32b
1549 li r0,0
1550 stb r0,HSTATE_NAPPING(r13)
1551
1552 /* see if any other thread is already exiting */
1553 lwz r0,VCORE_ENTRY_EXIT(r5)
1554 cmpwi r0,0x100
1555 blt kvmppc_cede_reentry /* if not go back to guest */
1556
1557 /* some threads are exiting, so go to the guest exit path */
1558 b hcall_real_fallback
1559
1560 /* cede when already previously prodded case */
1561 kvm_cede_prodded:
1562 li r0,0
1563 stb r0,VCPU_PRODDED(r3)
1564 sync /* order testing prodded vs. clearing ceded */
1565 stb r0,VCPU_CEDED(r3)
1566 li r3,H_SUCCESS
1567 blr
1568
1569 /* we've ceded but we want to give control to the host */
1570 kvm_cede_exit:
1571 li r3,H_TOO_HARD
1572 blr
1573
1574 secondary_too_late:
1575 ld r5,HSTATE_KVM_VCORE(r13)
1576 HMT_LOW
1577 13: lbz r3,VCORE_IN_GUEST(r5)
1578 cmpwi r3,0
1579 bne 13b
1580 HMT_MEDIUM
1581 ld r11,PACA_SLBSHADOWPTR(r13)
1582
1583 .rept SLB_NUM_BOLTED
1584 ld r5,SLBSHADOW_SAVEAREA(r11)
1585 ld r6,SLBSHADOW_SAVEAREA+8(r11)
1586 andis. r7,r5,SLB_ESID_V@h
1587 beq 1f
1588 slbmte r6,r5
1589 1: addi r11,r11,16
1590 .endr
1591
1592 secondary_nap:
1593 /* Clear our vcpu pointer so we don't come back in early */
1594 li r0, 0
1595 std r0, HSTATE_KVM_VCPU(r13)
1596 lwsync
1597 /* Clear any pending IPI - assume we're a secondary thread */
1598 ld r5, HSTATE_XICS_PHYS(r13)
1599 li r7, XICS_XIRR
1600 lwzcix r3, r5, r7 /* ack any pending interrupt */
1601 rlwinm. r0, r3, 0, 0xffffff /* any pending? */
1602 beq 37f
1603 sync
1604 li r0, 0xff
1605 li r6, XICS_QIRR
1606 stbcix r0, r5, r6 /* clear the IPI */
1607 stwcix r3, r5, r7 /* EOI it */
1608 37: sync
1609
1610 /* increment the nap count and then go to nap mode */
1611 ld r4, HSTATE_KVM_VCORE(r13)
1612 addi r4, r4, VCORE_NAP_COUNT
1613 lwsync /* make previous updates visible */
1614 51: lwarx r3, 0, r4
1615 addi r3, r3, 1
1616 stwcx. r3, 0, r4
1617 bne 51b
1618
1619 kvm_no_guest:
1620 li r0, KVM_HWTHREAD_IN_NAP
1621 stb r0, HSTATE_HWTHREAD_STATE(r13)
1622
1623 li r3, LPCR_PECE0
1624 mfspr r4, SPRN_LPCR
1625 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
1626 mtspr SPRN_LPCR, r4
1627 isync
1628 std r0, HSTATE_SCRATCH0(r13)
1629 ptesync
1630 ld r0, HSTATE_SCRATCH0(r13)
1631 1: cmpd r0, r0
1632 bne 1b
1633 nap
1634 b .
1635
1636 /*
1637 * Save away FP, VMX and VSX registers.
1638 * r3 = vcpu pointer
1639 */
1640 _GLOBAL(kvmppc_save_fp)
1641 mfmsr r5
1642 ori r8,r5,MSR_FP
1643 #ifdef CONFIG_ALTIVEC
1644 BEGIN_FTR_SECTION
1645 oris r8,r8,MSR_VEC@h
1646 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1647 #endif
1648 #ifdef CONFIG_VSX
1649 BEGIN_FTR_SECTION
1650 oris r8,r8,MSR_VSX@h
1651 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1652 #endif
1653 mtmsrd r8
1654 isync
1655 #ifdef CONFIG_VSX
1656 BEGIN_FTR_SECTION
1657 reg = 0
1658 .rept 32
1659 li r6,reg*16+VCPU_VSRS
1660 STXVD2X(reg,R6,R3)
1661 reg = reg + 1
1662 .endr
1663 FTR_SECTION_ELSE
1664 #endif
1665 reg = 0
1666 .rept 32
1667 stfd reg,reg*8+VCPU_FPRS(r3)
1668 reg = reg + 1
1669 .endr
1670 #ifdef CONFIG_VSX
1671 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1672 #endif
1673 mffs fr0
1674 stfd fr0,VCPU_FPSCR(r3)
1675
1676 #ifdef CONFIG_ALTIVEC
1677 BEGIN_FTR_SECTION
1678 reg = 0
1679 .rept 32
1680 li r6,reg*16+VCPU_VRS
1681 stvx reg,r6,r3
1682 reg = reg + 1
1683 .endr
1684 mfvscr vr0
1685 li r6,VCPU_VSCR
1686 stvx vr0,r6,r3
1687 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1688 #endif
1689 mfspr r6,SPRN_VRSAVE
1690 stw r6,VCPU_VRSAVE(r3)
1691 mtmsrd r5
1692 isync
1693 blr
1694
1695 /*
1696 * Load up FP, VMX and VSX registers
1697 * r4 = vcpu pointer
1698 */
1699 .globl kvmppc_load_fp
1700 kvmppc_load_fp:
1701 mfmsr r9
1702 ori r8,r9,MSR_FP
1703 #ifdef CONFIG_ALTIVEC
1704 BEGIN_FTR_SECTION
1705 oris r8,r8,MSR_VEC@h
1706 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1707 #endif
1708 #ifdef CONFIG_VSX
1709 BEGIN_FTR_SECTION
1710 oris r8,r8,MSR_VSX@h
1711 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1712 #endif
1713 mtmsrd r8
1714 isync
1715 lfd fr0,VCPU_FPSCR(r4)
1716 MTFSF_L(fr0)
1717 #ifdef CONFIG_VSX
1718 BEGIN_FTR_SECTION
1719 reg = 0
1720 .rept 32
1721 li r7,reg*16+VCPU_VSRS
1722 LXVD2X(reg,R7,R4)
1723 reg = reg + 1
1724 .endr
1725 FTR_SECTION_ELSE
1726 #endif
1727 reg = 0
1728 .rept 32
1729 lfd reg,reg*8+VCPU_FPRS(r4)
1730 reg = reg + 1
1731 .endr
1732 #ifdef CONFIG_VSX
1733 ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
1734 #endif
1735
1736 #ifdef CONFIG_ALTIVEC
1737 BEGIN_FTR_SECTION
1738 li r7,VCPU_VSCR
1739 lvx vr0,r7,r4
1740 mtvscr vr0
1741 reg = 0
1742 .rept 32
1743 li r7,reg*16+VCPU_VRS
1744 lvx reg,r7,r4
1745 reg = reg + 1
1746 .endr
1747 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1748 #endif
1749 lwz r7,VCPU_VRSAVE(r4)
1750 mtspr SPRN_VRSAVE,r7
1751 blr
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