2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
33 #include <asm/xive-regs.h>
35 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
37 /* Values in HSTATE_NAPPING(r13) */
38 #define NAPPING_CEDE 1
39 #define NAPPING_NOVCPU 2
42 * Call kvmppc_hv_entry in real mode.
43 * Must be called with interrupts hard-disabled.
47 * LR = return address to continue at after eventually re-enabling MMU
49 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
51 std r0, PPC_LR_STKOFF(r1)
54 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
59 mtmsrd r0,1 /* clear RI in MSR */
65 ld r4, HSTATE_KVM_VCPU(r13)
68 /* Back from guest - restore host state and return to caller */
71 /* Restore host DABR and DABRX */
72 ld r5,HSTATE_DABR(r13)
76 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
79 ld r3,PACA_SPRG_VDSO(r13)
80 mtspr SPRN_SPRG_VDSO_WRITE,r3
82 /* Reload the host's PMU registers */
83 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
84 lbz r4, LPPACA_PMCINUSE(r3)
86 beq 23f /* skip if not */
88 ld r3, HSTATE_MMCR0(r13)
89 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
92 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
93 lwz r3, HSTATE_PMC1(r13)
94 lwz r4, HSTATE_PMC2(r13)
95 lwz r5, HSTATE_PMC3(r13)
96 lwz r6, HSTATE_PMC4(r13)
97 lwz r8, HSTATE_PMC5(r13)
98 lwz r9, HSTATE_PMC6(r13)
105 ld r3, HSTATE_MMCR0(r13)
106 ld r4, HSTATE_MMCR1(r13)
107 ld r5, HSTATE_MMCRA(r13)
108 ld r6, HSTATE_SIAR(r13)
109 ld r7, HSTATE_SDAR(r13)
115 ld r8, HSTATE_MMCR2(r13)
116 ld r9, HSTATE_SIER(r13)
119 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
125 * Reload DEC. HDEC interrupts were disabled when
126 * we reloaded the host's LPCR value.
128 ld r3, HSTATE_DECEXP(r13)
133 /* hwthread_req may have got set by cede or no vcpu, so clear it */
135 stb r0, HSTATE_HWTHREAD_REQ(r13)
138 * For external and machine check interrupts, we need
139 * to call the Linux handler to process the interrupt.
140 * We do that by jumping to absolute address 0x500 for
141 * external interrupts, or the machine_check_fwnmi label
142 * for machine checks (since firmware might have patched
143 * the vector area at 0x200). The [h]rfid at the end of the
144 * handler will return to the book3s_hv_interrupts.S code.
145 * For other interrupts we do the rfid to get back
146 * to the book3s_hv_interrupts.S code here.
148 ld r8, 112+PPC_LR_STKOFF(r1)
150 ld r7, HSTATE_HOST_MSR(r13)
153 * If we came back from the guest via a relocation-on interrupt,
154 * we will be in virtual mode at this point, which makes it a
155 * little easier to get back to the caller.
158 andi. r0, r0, MSR_IR /* in real mode? */
161 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
162 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
164 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
165 beq 15f /* Invoke the H_DOORBELL handler */
166 cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI
167 beq cr2, 14f /* HMI check */
169 /* RFI into the highmem handler, or branch to interrupt handler */
173 mtmsrd r6, 1 /* Clear RI in MSR */
176 beq cr1, 13f /* machine check */
179 /* On POWER7, we have external interrupts set to use HSRR0/1 */
180 11: mtspr SPRN_HSRR0, r8
184 13: b machine_check_fwnmi
186 14: mtspr SPRN_HSRR0, r8
188 b hmi_exception_after_realmode
190 15: mtspr SPRN_HSRR0, r8
194 /* Virtual-mode return - can't get here for HMI or machine check */
196 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
198 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
200 andi. r0, r7, MSR_EE /* were interrupts hard-enabled? */
202 mtmsrd r7, 1 /* if so then re-enable them */
206 16: mtspr SPRN_HSRR0, r8 /* jump to reloc-on external vector */
208 b exc_virt_0x4500_hardware_interrupt
210 17: mtspr SPRN_HSRR0, r8
212 b exc_virt_0x4e80_h_doorbell
214 kvmppc_primary_no_guest:
215 /* We handle this much like a ceded vcpu */
216 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
220 * Make sure the primary has finished the MMU switch.
221 * We should never get here on a secondary thread, but
222 * check it for robustness' sake.
224 ld r5, HSTATE_KVM_VCORE(r13)
225 65: lbz r0, VCORE_IN_GUEST(r5)
232 /* set our bit in napping_threads */
233 ld r5, HSTATE_KVM_VCORE(r13)
234 lbz r7, HSTATE_PTID(r13)
237 addi r6, r5, VCORE_NAPPING_THREADS
242 /* order napping_threads update vs testing entry_exit_map */
245 lwz r7, VCORE_ENTRY_EXIT(r5)
247 bge kvm_novcpu_exit /* another thread already exiting */
248 li r3, NAPPING_NOVCPU
249 stb r3, HSTATE_NAPPING(r13)
251 li r3, 0 /* Don't wake on privileged (OS) doorbell */
256 * Entered from kvm_start_guest if kvm_hstate.napping is set
262 ld r1, HSTATE_HOST_R1(r13)
263 ld r5, HSTATE_KVM_VCORE(r13)
265 stb r0, HSTATE_NAPPING(r13)
267 /* check the wake reason */
268 bl kvmppc_check_wake_reason
271 * Restore volatile registers since we could have called
272 * a C routine in kvmppc_check_wake_reason.
275 ld r5, HSTATE_KVM_VCORE(r13)
277 /* see if any other thread is already exiting */
278 lwz r0, VCORE_ENTRY_EXIT(r5)
282 /* clear our bit in napping_threads */
283 lbz r7, HSTATE_PTID(r13)
286 addi r6, r5, VCORE_NAPPING_THREADS
292 /* See if the wake reason means we need to exit */
296 /* See if our timeslice has expired (HDEC is negative) */
298 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
302 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
303 ld r4, HSTATE_KVM_VCPU(r13)
305 beq kvmppc_primary_no_guest
307 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
308 addi r3, r4, VCPU_TB_RMENTRY
309 bl kvmhv_start_timing
314 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
315 ld r4, HSTATE_KVM_VCPU(r13)
318 addi r3, r4, VCPU_TB_RMEXIT
319 bl kvmhv_accumulate_time
323 bl kvmhv_commence_exit
326 b kvmhv_switch_to_host
329 * We come in here when wakened from nap mode.
330 * Relocation is off and most register values are lost.
331 * r13 points to the PACA.
333 .globl kvm_start_guest
336 /* Set runlatch bit the minute you wake up from nap */
343 li r0,KVM_HWTHREAD_IN_KVM
344 stb r0,HSTATE_HWTHREAD_STATE(r13)
346 /* NV GPR values from power7_idle() will no longer be valid */
348 stb r0,PACA_NAPSTATELOST(r13)
350 /* were we napping due to cede? */
351 lbz r0,HSTATE_NAPPING(r13)
352 cmpwi r0,NAPPING_CEDE
354 cmpwi r0,NAPPING_NOVCPU
355 beq kvm_novcpu_wakeup
357 ld r1,PACAEMERGSP(r13)
358 subi r1,r1,STACK_FRAME_OVERHEAD
361 * We weren't napping due to cede, so this must be a secondary
362 * thread being woken up to run a guest, or being woken up due
363 * to a stray IPI. (Or due to some machine check or hypervisor
364 * maintenance interrupt while the core is in KVM.)
367 /* Check the wake reason in SRR1 to see why we got here */
368 bl kvmppc_check_wake_reason
370 * kvmppc_check_wake_reason could invoke a C routine, but we
371 * have no volatile registers to restore when we return.
377 /* get vcore pointer, NULL if we have nothing to run */
378 ld r5,HSTATE_KVM_VCORE(r13)
380 /* if we have no vcore to run, go back to sleep */
383 kvm_secondary_got_guest:
385 /* Set HSTATE_DSCR(r13) to something sensible */
386 ld r6, PACA_DSCR_DEFAULT(r13)
387 std r6, HSTATE_DSCR(r13)
389 /* On thread 0 of a subcore, set HDEC to max */
390 lbz r4, HSTATE_PTID(r13)
396 /* and set per-LPAR registers, if doing dynamic micro-threading */
397 ld r6, HSTATE_SPLIT_MODE(r13)
400 ld r0, KVM_SPLIT_RPR(r6)
402 ld r0, KVM_SPLIT_PMMAR(r6)
404 ld r0, KVM_SPLIT_LDBAR(r6)
408 /* Order load of vcpu after load of vcore */
410 ld r4, HSTATE_KVM_VCPU(r13)
413 /* Back from the guest, go back to nap */
414 /* Clear our vcpu and vcore pointers so we don't come back in early */
416 std r0, HSTATE_KVM_VCPU(r13)
418 * Once we clear HSTATE_KVM_VCORE(r13), the code in
419 * kvmppc_run_core() is going to assume that all our vcpu
420 * state is visible in memory. This lwsync makes sure
424 std r0, HSTATE_KVM_VCORE(r13)
427 * All secondaries exiting guest will fall through this path.
428 * Before proceeding, just check for HMI interrupt and
429 * invoke opal hmi handler. By now we are sure that the
430 * primary thread on this core/subcore has already made partition
431 * switch/TB resync and we are good to call opal hmi handler.
433 cmpwi r12, BOOK3S_INTERRUPT_HMI
436 li r3,0 /* NULL argument */
437 bl hmi_exception_realmode
439 * At this point we have finished executing in the guest.
440 * We need to wait for hwthread_req to become zero, since
441 * we may not turn on the MMU while hwthread_req is non-zero.
442 * While waiting we also need to check if we get given a vcpu to run.
445 lbz r3, HSTATE_HWTHREAD_REQ(r13)
449 li r0, KVM_HWTHREAD_IN_KERNEL
450 stb r0, HSTATE_HWTHREAD_STATE(r13)
451 /* need to recheck hwthread_req after a barrier, to avoid race */
453 lbz r3, HSTATE_HWTHREAD_REQ(r13)
457 * We jump to pnv_wakeup_loss, which will return to the caller
458 * of power7_nap in the powernv cpu offline loop. The value we
459 * put in r3 becomes the return value for power7_nap.
463 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
469 ld r5, HSTATE_KVM_VCORE(r13)
472 ld r3, HSTATE_SPLIT_MODE(r13)
475 lbz r0, KVM_SPLIT_DO_NAP(r3)
481 b kvm_secondary_got_guest
483 54: li r0, KVM_HWTHREAD_IN_KVM
484 stb r0, HSTATE_HWTHREAD_STATE(r13)
488 * Here the primary thread is trying to return the core to
489 * whole-core mode, so we need to nap.
493 * When secondaries are napping in kvm_unsplit_nap() with
494 * hwthread_req = 1, HMI goes ignored even though subcores are
495 * already exited the guest. Hence HMI keeps waking up secondaries
496 * from nap in a loop and secondaries always go back to nap since
497 * no vcore is assigned to them. This makes impossible for primary
498 * thread to get hold of secondary threads resulting into a soft
499 * lockup in KVM path.
501 * Let us check if HMI is pending and handle it before we go to nap.
503 cmpwi r12, BOOK3S_INTERRUPT_HMI
505 li r3, 0 /* NULL argument */
506 bl hmi_exception_realmode
509 * Ensure that secondary doesn't nap when it has
510 * its vcore pointer set.
512 sync /* matches smp_mb() before setting split_info.do_nap */
513 ld r0, HSTATE_KVM_VCORE(r13)
516 /* clear any pending message */
518 lis r6, (PPC_DBELL_SERVER << (63-36))@h
520 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
521 /* Set kvm_split_mode.napped[tid] = 1 */
522 ld r3, HSTATE_SPLIT_MODE(r13)
524 lhz r4, PACAPACAINDEX(r13)
525 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
526 addi r4, r4, KVM_SPLIT_NAPPED
528 /* Check the do_nap flag again after setting napped[] */
530 lbz r0, KVM_SPLIT_DO_NAP(r3)
533 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
535 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
542 /******************************************************************************
546 *****************************************************************************/
548 /* Stack frame offsets */
549 #define STACK_SLOT_TID (112-16)
550 #define STACK_SLOT_PSSCR (112-24)
551 #define STACK_SLOT_PID (112-32)
553 .global kvmppc_hv_entry
558 * R4 = vcpu pointer (or NULL)
563 * all other volatile GPRS = free
564 * Does not preserve non-volatile GPRs or CR fields
567 std r0, PPC_LR_STKOFF(r1)
570 /* Save R1 in the PACA */
571 std r1, HSTATE_HOST_R1(r13)
573 li r6, KVM_GUEST_MODE_HOST_HV
574 stb r6, HSTATE_IN_GUEST(r13)
576 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
577 /* Store initial timestamp */
580 addi r3, r4, VCPU_TB_RMENTRY
581 bl kvmhv_start_timing
585 /* Use cr7 as an indication of radix mode */
586 ld r5, HSTATE_KVM_VCORE(r13)
587 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
588 lbz r0, KVM_RADIX(r9)
591 /* Clear out SLB if hash */
599 * POWER7/POWER8 host -> guest partition switch code.
600 * We don't have to lock against concurrent tlbies,
601 * but we do have to coordinate across hardware threads.
603 /* Set bit in entry map iff exit map is zero. */
605 lbz r6, HSTATE_PTID(r13)
607 addi r8, r5, VCORE_ENTRY_EXIT
609 cmpwi r3, 0x100 /* any threads starting to exit? */
610 bge secondary_too_late /* if so we're too late to the party */
615 /* Primary thread switches to guest partition. */
621 li r0,LPID_RSVD /* switch to reserved LPID */
624 mtspr SPRN_SDR1,r6 /* switch to partition page table */
625 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
629 /* See if we need to flush the TLB */
630 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
633 * On POWER9, individual threads can come in here, but the
634 * TLB is shared between the 4 threads in a core, hence
635 * invalidating on one thread invalidates for all.
636 * Thus we make all 4 threads use the same bit here.
639 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
640 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
641 srdi r6,r6,6 /* doubleword number */
642 sldi r6,r6,3 /* address offset */
644 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
650 /* Flush the TLB of any entries for this LPID */
651 lwz r0,KVM_TLB_SETS(r9)
653 li r7,0x800 /* IS field = 0b10 */
655 li r0,0 /* RS for P9 version of tlbiel */
657 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
661 29: PPC_TLBIEL(7,0,2,1,1) /* for radix, RIC=2, PRS=1, R=1 */
665 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
670 /* Add timebase offset onto timebase */
671 22: ld r8,VCORE_TB_OFFSET(r5)
674 mftb r6 /* current host timebase */
676 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
677 mftb r7 /* check if lower 24 bits overflowed */
682 addis r8,r8,0x100 /* if so, increment upper 40 bits */
685 /* Load guest PCR value to select appropriate compat mode */
686 37: ld r7, VCORE_PCR(r5)
693 /* DPDES and VTB are shared between threads */
694 ld r8, VCORE_DPDES(r5)
698 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
700 /* Mark the subcore state as inside guest */
701 bl kvmppc_subcore_enter_guest
703 ld r5, HSTATE_KVM_VCORE(r13)
704 ld r4, HSTATE_KVM_VCPU(r13)
706 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
708 /* Do we have a guest vcpu to run? */
710 beq kvmppc_primary_no_guest
713 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
714 lwz r5,VCPU_SLB_MAX(r4)
719 1: ld r8,VCPU_SLB_E(r6)
722 addi r6,r6,VCPU_SLB_SIZE
725 /* Increment yield count if they have a VPA */
729 li r6, LPPACA_YIELDCOUNT
734 stb r6, VCPU_VPA_DIRTY(r4)
737 /* Save purr/spurr */
740 std r5,HSTATE_PURR(r13)
741 std r6,HSTATE_SPURR(r13)
747 /* Save host values of some registers */
752 std r5, STACK_SLOT_TID(r1)
753 std r6, STACK_SLOT_PSSCR(r1)
754 std r7, STACK_SLOT_PID(r1)
755 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
758 /* Set partition DABR */
759 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
760 lwz r5,VCPU_DABRX(r4)
765 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
767 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
770 END_FTR_SECTION_IFSET(CPU_FTR_TM)
773 /* Load guest PMU registers */
774 /* R4 is live here (vcpu pointer) */
776 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
777 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
781 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
784 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
785 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
786 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
787 lwz r6, VCPU_PMC + 8(r4)
788 lwz r7, VCPU_PMC + 12(r4)
789 lwz r8, VCPU_PMC + 16(r4)
790 lwz r9, VCPU_PMC + 20(r4)
798 ld r5, VCPU_MMCR + 8(r4)
799 ld r6, VCPU_MMCR + 16(r4)
807 ld r5, VCPU_MMCR + 24(r4)
811 BEGIN_FTR_SECTION_NESTED(96)
812 lwz r7, VCPU_PMC + 24(r4)
813 lwz r8, VCPU_PMC + 28(r4)
814 ld r9, VCPU_MMCR + 32(r4)
818 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
819 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
823 /* Load up FP, VMX and VSX registers */
826 ld r14, VCPU_GPR(R14)(r4)
827 ld r15, VCPU_GPR(R15)(r4)
828 ld r16, VCPU_GPR(R16)(r4)
829 ld r17, VCPU_GPR(R17)(r4)
830 ld r18, VCPU_GPR(R18)(r4)
831 ld r19, VCPU_GPR(R19)(r4)
832 ld r20, VCPU_GPR(R20)(r4)
833 ld r21, VCPU_GPR(R21)(r4)
834 ld r22, VCPU_GPR(R22)(r4)
835 ld r23, VCPU_GPR(R23)(r4)
836 ld r24, VCPU_GPR(R24)(r4)
837 ld r25, VCPU_GPR(R25)(r4)
838 ld r26, VCPU_GPR(R26)(r4)
839 ld r27, VCPU_GPR(R27)(r4)
840 ld r28, VCPU_GPR(R28)(r4)
841 ld r29, VCPU_GPR(R29)(r4)
842 ld r30, VCPU_GPR(R30)(r4)
843 ld r31, VCPU_GPR(R31)(r4)
845 /* Switch DSCR to guest value */
850 /* Skip next section on POWER7 */
852 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
853 /* Load up POWER8-specific registers */
855 lwz r6, VCPU_PSPB(r4)
861 ld r6, VCPU_DAWRX(r4)
862 ld r7, VCPU_CIABR(r4)
869 ld r8, VCPU_EBBHR(r4)
872 ld r5, VCPU_EBBRR(r4)
873 ld r6, VCPU_BESCR(r4)
874 lwz r7, VCPU_GUEST_PID(r4)
882 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
884 /* POWER8-only registers */
885 ld r5, VCPU_TCSCR(r4)
887 ld r7, VCPU_CSIGR(r4)
894 /* POWER9-only registers */
896 ld r6, VCPU_PSSCR(r4)
897 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
900 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
904 * Set the decrementer to the guest decrementer.
906 ld r8,VCPU_DEC_EXPIRES(r4)
907 /* r8 is a host timebase value here, convert to guest TB */
908 ld r5,HSTATE_KVM_VCORE(r13)
909 ld r6,VCORE_TB_OFFSET(r5)
916 ld r5, VCPU_SPRG0(r4)
917 ld r6, VCPU_SPRG1(r4)
918 ld r7, VCPU_SPRG2(r4)
919 ld r8, VCPU_SPRG3(r4)
925 /* Load up DAR and DSISR */
927 lwz r6, VCPU_DSISR(r4)
931 /* Restore AMR and UAMOR, set AMOR to all 1s */
939 /* Restore state of CTRL run bit; assume 1 on entry */
947 /* Secondary threads wait for primary to have done partition switch */
948 ld r5, HSTATE_KVM_VCORE(r13)
949 lbz r6, HSTATE_PTID(r13)
952 lbz r0, VCORE_IN_GUEST(r5)
956 20: lwz r3, VCORE_ENTRY_EXIT(r5)
959 lbz r0, VCORE_IN_GUEST(r5)
969 /* Check if HDEC expires soon */
971 cmpwi r3, 512 /* 1 microsecond */
974 #ifdef CONFIG_KVM_XICS
975 /* We are entering the guest on that thread, push VCPU to XIVE */
976 ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
979 ld r11, VCPU_XIVE_SAVED_STATE(r4)
983 lwz r11, VCPU_XIVE_CAM_WORD(r4)
984 li r9, TM_QW1_OS + TM_WORD2
987 stw r9, VCPU_XIVE_PUSHED(r4)
989 #endif /* CONFIG_KVM_XICS */
991 deliver_guest_interrupt:
998 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
1000 ld r11, VCPU_MSR(r4)
1001 ld r6, VCPU_SRR0(r4)
1002 ld r7, VCPU_SRR1(r4)
1006 /* r11 = vcpu->arch.msr & ~MSR_HV */
1007 rldicl r11, r11, 63 - MSR_HV_LG, 1
1008 rotldi r11, r11, 1 + MSR_HV_LG
1009 ori r11, r11, MSR_ME
1011 /* Check if we can deliver an external or decrementer interrupt now */
1012 ld r0, VCPU_PENDING_EXC(r4)
1013 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
1015 andi. r8, r11, MSR_EE
1017 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
1018 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
1022 li r0, BOOK3S_INTERRUPT_EXTERNAL
1026 li r0, BOOK3S_INTERRUPT_DECREMENTER
1029 12: mtspr SPRN_SRR0, r10
1031 mtspr SPRN_SRR1, r11
1033 bl kvmppc_msr_interrupt
1039 * R10: value for HSRR0
1040 * R11: value for HSRR1
1045 stb r0,VCPU_CEDED(r4) /* cancel cede */
1046 mtspr SPRN_HSRR0,r10
1047 mtspr SPRN_HSRR1,r11
1049 /* Activate guest mode, so faults get handled by KVM */
1050 li r9, KVM_GUEST_MODE_GUEST_HV
1051 stb r9, HSTATE_IN_GUEST(r13)
1053 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1054 /* Accumulate timing */
1055 addi r3, r4, VCPU_TB_GUEST
1056 bl kvmhv_accumulate_time
1062 ld r5, VCPU_CFAR(r4)
1064 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1067 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1074 ld r1, VCPU_GPR(R1)(r4)
1075 ld r2, VCPU_GPR(R2)(r4)
1076 ld r3, VCPU_GPR(R3)(r4)
1077 ld r5, VCPU_GPR(R5)(r4)
1078 ld r6, VCPU_GPR(R6)(r4)
1079 ld r7, VCPU_GPR(R7)(r4)
1080 ld r8, VCPU_GPR(R8)(r4)
1081 ld r9, VCPU_GPR(R9)(r4)
1082 ld r10, VCPU_GPR(R10)(r4)
1083 ld r11, VCPU_GPR(R11)(r4)
1084 ld r12, VCPU_GPR(R12)(r4)
1085 ld r13, VCPU_GPR(R13)(r4)
1089 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1090 ld r0, VCPU_GPR(R0)(r4)
1091 ld r4, VCPU_GPR(R4)(r4)
1100 stw r12, VCPU_TRAP(r4)
1101 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1102 addi r3, r4, VCPU_TB_RMEXIT
1103 bl kvmhv_accumulate_time
1105 11: b kvmhv_switch_to_host
1112 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1113 12: stw r12, VCPU_TRAP(r4)
1115 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1116 addi r3, r4, VCPU_TB_RMEXIT
1117 bl kvmhv_accumulate_time
1121 /******************************************************************************
1125 *****************************************************************************/
1128 * We come here from the first-level interrupt handlers.
1130 .globl kvmppc_interrupt_hv
1131 kvmppc_interrupt_hv:
1133 * Register contents:
1134 * R12 = (guest CR << 32) | interrupt vector
1136 * guest R12 saved in shadow VCPU SCRATCH0
1137 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1138 * guest R13 saved in SPRN_SCRATCH0
1140 std r9, HSTATE_SCRATCH2(r13)
1141 lbz r9, HSTATE_IN_GUEST(r13)
1142 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1143 beq kvmppc_bad_host_intr
1144 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1145 cmpwi r9, KVM_GUEST_MODE_GUEST
1146 ld r9, HSTATE_SCRATCH2(r13)
1147 beq kvmppc_interrupt_pr
1149 /* We're now back in the host but in guest MMU context */
1150 li r9, KVM_GUEST_MODE_HOST_HV
1151 stb r9, HSTATE_IN_GUEST(r13)
1153 ld r9, HSTATE_KVM_VCPU(r13)
1155 /* Save registers */
1157 std r0, VCPU_GPR(R0)(r9)
1158 std r1, VCPU_GPR(R1)(r9)
1159 std r2, VCPU_GPR(R2)(r9)
1160 std r3, VCPU_GPR(R3)(r9)
1161 std r4, VCPU_GPR(R4)(r9)
1162 std r5, VCPU_GPR(R5)(r9)
1163 std r6, VCPU_GPR(R6)(r9)
1164 std r7, VCPU_GPR(R7)(r9)
1165 std r8, VCPU_GPR(R8)(r9)
1166 ld r0, HSTATE_SCRATCH2(r13)
1167 std r0, VCPU_GPR(R9)(r9)
1168 std r10, VCPU_GPR(R10)(r9)
1169 std r11, VCPU_GPR(R11)(r9)
1170 ld r3, HSTATE_SCRATCH0(r13)
1171 std r3, VCPU_GPR(R12)(r9)
1172 /* CR is in the high half of r12 */
1176 ld r3, HSTATE_CFAR(r13)
1177 std r3, VCPU_CFAR(r9)
1178 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1180 ld r4, HSTATE_PPR(r13)
1181 std r4, VCPU_PPR(r9)
1182 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1184 /* Restore R1/R2 so we can handle faults */
1185 ld r1, HSTATE_HOST_R1(r13)
1188 mfspr r10, SPRN_SRR0
1189 mfspr r11, SPRN_SRR1
1190 std r10, VCPU_SRR0(r9)
1191 std r11, VCPU_SRR1(r9)
1192 /* trap is in the low half of r12, clear CR from the high half */
1194 andi. r0, r12, 2 /* need to read HSRR0/1? */
1196 mfspr r10, SPRN_HSRR0
1197 mfspr r11, SPRN_HSRR1
1199 1: std r10, VCPU_PC(r9)
1200 std r11, VCPU_MSR(r9)
1204 std r3, VCPU_GPR(R13)(r9)
1207 stw r12,VCPU_TRAP(r9)
1209 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1210 addi r3, r9, VCPU_TB_RMINTR
1212 bl kvmhv_accumulate_time
1213 ld r5, VCPU_GPR(R5)(r9)
1214 ld r6, VCPU_GPR(R6)(r9)
1215 ld r7, VCPU_GPR(R7)(r9)
1216 ld r8, VCPU_GPR(R8)(r9)
1219 /* Save HEIR (HV emulation assist reg) in emul_inst
1220 if this is an HEI (HV emulation interrupt, e40) */
1221 li r3,KVM_INST_FETCH_FAILED
1222 stw r3,VCPU_LAST_INST(r9)
1223 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1226 11: stw r3,VCPU_HEIR(r9)
1228 /* these are volatile across C function calls */
1229 #ifdef CONFIG_RELOCATABLE
1230 ld r3, HSTATE_SCRATCH1(r13)
1236 std r3, VCPU_CTR(r9)
1237 std r4, VCPU_XER(r9)
1239 /* If this is a page table miss then see if it's theirs or ours */
1240 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1242 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1245 /* See if this is a leftover HDEC interrupt */
1246 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1251 bge fast_guest_return
1253 /* See if this is an hcall we can handle in real mode */
1254 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1255 beq hcall_try_real_mode
1257 /* Hypervisor doorbell - exit only if host IPI flag set */
1258 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1260 lbz r0, HSTATE_HOST_IPI(r13)
1265 /* External interrupt ? */
1266 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1267 bne+ guest_exit_cont
1269 /* External interrupt, first check for host_ipi. If this is
1270 * set, we know the host wants us out so let's do it now
1275 * Restore the active volatile registers after returning from
1278 ld r9, HSTATE_KVM_VCPU(r13)
1279 li r12, BOOK3S_INTERRUPT_EXTERNAL
1282 * kvmppc_read_intr return codes:
1284 * Exit to host (r3 > 0)
1285 * 1 An interrupt is pending that needs to be handled by the host
1286 * Exit guest and return to host by branching to guest_exit_cont
1288 * 2 Passthrough that needs completion in the host
1289 * Exit guest and return to host by branching to guest_exit_cont
1290 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1291 * to indicate to the host to complete handling the interrupt
1293 * Before returning to guest, we check if any CPU is heading out
1294 * to the host and if so, we head out also. If no CPUs are heading
1295 * check return values <= 0.
1297 * Return to guest (r3 <= 0)
1298 * 0 No external interrupt is pending
1299 * -1 A guest wakeup IPI (which has now been cleared)
1300 * In either case, we return to guest to deliver any pending
1303 * -2 A PCI passthrough external interrupt was handled
1304 * (interrupt was delivered directly to guest)
1305 * Return to guest to deliver any pending guest interrupts.
1311 /* Return code = 2 */
1312 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1313 stw r12, VCPU_TRAP(r9)
1316 1: /* Return code <= 1 */
1320 /* Return code <= 0 */
1321 4: ld r5, HSTATE_KVM_VCORE(r13)
1322 lwz r0, VCORE_ENTRY_EXIT(r5)
1325 blt deliver_guest_interrupt
1327 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1328 #ifdef CONFIG_KVM_XICS
1329 /* We are exiting, pull the VP from the XIVE */
1330 lwz r0, VCPU_XIVE_PUSHED(r9)
1333 li r7, TM_SPC_PULL_OS_CTX
1336 andi. r0, r0, MSR_IR /* in real mode? */
1338 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1341 /* First load to pull the context, we ignore the value */
1344 /* Second load to recover the context state (Words 0 and 1) */
1347 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1350 /* First load to pull the context, we ignore the value */
1353 /* Second load to recover the context state (Words 0 and 1) */
1355 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1356 /* Fixup some of the state for the next load */
1359 stw r10, VCPU_XIVE_PUSHED(r9)
1360 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1361 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1363 #endif /* CONFIG_KVM_XICS */
1364 /* Save more register state */
1367 std r6, VCPU_DAR(r9)
1368 stw r7, VCPU_DSISR(r9)
1369 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1370 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1372 std r6, VCPU_FAULT_DAR(r9)
1373 stw r7, VCPU_FAULT_DSISR(r9)
1375 /* See if it is a machine check */
1376 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1377 beq machine_check_realmode
1379 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1380 addi r3, r9, VCPU_TB_RMEXIT
1382 bl kvmhv_accumulate_time
1386 /* Increment exit count, poke other threads to exit */
1387 bl kvmhv_commence_exit
1389 ld r9, HSTATE_KVM_VCPU(r13)
1390 lwz r12, VCPU_TRAP(r9)
1392 /* Stop others sending VCPU interrupts to this physical CPU */
1394 stw r0, VCPU_CPU(r9)
1395 stw r0, VCPU_THREAD_CPU(r9)
1397 /* Save guest CTRL register, set runlatch to 1 */
1399 stw r6,VCPU_CTRL(r9)
1405 /* Read the guest SLB and save it away */
1407 lbz r0, KVM_RADIX(r5)
1410 bne 3f /* for radix, save 0 entries */
1411 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1416 andis. r0,r8,SLB_ESID_V@h
1418 add r8,r8,r6 /* put index in */
1420 std r8,VCPU_SLB_E(r7)
1421 std r3,VCPU_SLB_V(r7)
1422 addi r7,r7,VCPU_SLB_SIZE
1426 3: stw r5,VCPU_SLB_MAX(r9)
1429 * Save the guest PURR/SPURR
1434 ld r8,VCPU_SPURR(r9)
1435 std r5,VCPU_PURR(r9)
1436 std r6,VCPU_SPURR(r9)
1441 * Restore host PURR/SPURR and add guest times
1442 * so that the time in the guest gets accounted.
1444 ld r3,HSTATE_PURR(r13)
1445 ld r4,HSTATE_SPURR(r13)
1456 /* r5 is a guest timebase value here, convert to host TB */
1457 ld r3,HSTATE_KVM_VCORE(r13)
1458 ld r4,VCORE_TB_OFFSET(r3)
1460 std r5,VCPU_DEC_EXPIRES(r9)
1464 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1465 /* Save POWER8-specific registers */
1469 std r5, VCPU_IAMR(r9)
1470 stw r6, VCPU_PSPB(r9)
1471 std r7, VCPU_FSCR(r9)
1475 std r7, VCPU_TAR(r9)
1476 mfspr r8, SPRN_EBBHR
1477 std r8, VCPU_EBBHR(r9)
1478 mfspr r5, SPRN_EBBRR
1479 mfspr r6, SPRN_BESCR
1482 std r5, VCPU_EBBRR(r9)
1483 std r6, VCPU_BESCR(r9)
1484 stw r7, VCPU_GUEST_PID(r9)
1485 std r8, VCPU_WORT(r9)
1487 mfspr r5, SPRN_TCSCR
1489 mfspr r7, SPRN_CSIGR
1491 std r5, VCPU_TCSCR(r9)
1492 std r6, VCPU_ACOP(r9)
1493 std r7, VCPU_CSIGR(r9)
1494 std r8, VCPU_TACR(r9)
1497 mfspr r6, SPRN_PSSCR
1498 std r5, VCPU_TID(r9)
1499 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1501 std r6, VCPU_PSSCR(r9)
1502 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1504 * Restore various registers to 0, where non-zero values
1505 * set by the guest could disrupt the host.
1509 mtspr SPRN_CIABR, r0
1510 mtspr SPRN_DAWRX, r0
1513 mtspr SPRN_TCSCR, r0
1514 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1517 mtspr SPRN_MMCRS, r0
1518 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1521 /* Save and reset AMR and UAMOR before turning on the MMU */
1525 std r6,VCPU_UAMOR(r9)
1529 /* Switch DSCR back to host value */
1531 ld r7, HSTATE_DSCR(r13)
1532 std r8, VCPU_DSCR(r9)
1535 /* Save non-volatile GPRs */
1536 std r14, VCPU_GPR(R14)(r9)
1537 std r15, VCPU_GPR(R15)(r9)
1538 std r16, VCPU_GPR(R16)(r9)
1539 std r17, VCPU_GPR(R17)(r9)
1540 std r18, VCPU_GPR(R18)(r9)
1541 std r19, VCPU_GPR(R19)(r9)
1542 std r20, VCPU_GPR(R20)(r9)
1543 std r21, VCPU_GPR(R21)(r9)
1544 std r22, VCPU_GPR(R22)(r9)
1545 std r23, VCPU_GPR(R23)(r9)
1546 std r24, VCPU_GPR(R24)(r9)
1547 std r25, VCPU_GPR(R25)(r9)
1548 std r26, VCPU_GPR(R26)(r9)
1549 std r27, VCPU_GPR(R27)(r9)
1550 std r28, VCPU_GPR(R28)(r9)
1551 std r29, VCPU_GPR(R29)(r9)
1552 std r30, VCPU_GPR(R30)(r9)
1553 std r31, VCPU_GPR(R31)(r9)
1556 mfspr r3, SPRN_SPRG0
1557 mfspr r4, SPRN_SPRG1
1558 mfspr r5, SPRN_SPRG2
1559 mfspr r6, SPRN_SPRG3
1560 std r3, VCPU_SPRG0(r9)
1561 std r4, VCPU_SPRG1(r9)
1562 std r5, VCPU_SPRG2(r9)
1563 std r6, VCPU_SPRG3(r9)
1569 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1572 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1575 /* Increment yield count if they have a VPA */
1576 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1579 li r4, LPPACA_YIELDCOUNT
1584 stb r3, VCPU_VPA_DIRTY(r9)
1586 /* Save PMU registers if requested */
1587 /* r8 and cr0.eq are live here */
1590 * POWER8 seems to have a hardware bug where setting
1591 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1592 * when some counters are already negative doesn't seem
1593 * to cause a performance monitor alert (and hence interrupt).
1594 * The effect of this is that when saving the PMU state,
1595 * if there is no PMU alert pending when we read MMCR0
1596 * before freezing the counters, but one becomes pending
1597 * before we read the counters, we lose it.
1598 * To work around this, we need a way to freeze the counters
1599 * before reading MMCR0. Normally, freezing the counters
1600 * is done by writing MMCR0 (to set MMCR0[FC]) which
1601 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1602 * we can also freeze the counters using MMCR2, by writing
1603 * 1s to all the counter freeze condition bits (there are
1604 * 9 bits each for 6 counters).
1606 li r3, -1 /* set all freeze bits */
1608 mfspr r10, SPRN_MMCR2
1609 mtspr SPRN_MMCR2, r3
1611 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1613 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1614 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1615 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1616 mfspr r6, SPRN_MMCRA
1617 /* Clear MMCRA in order to disable SDAR updates */
1619 mtspr SPRN_MMCRA, r7
1621 beq 21f /* if no VPA, save PMU stuff anyway */
1622 lbz r7, LPPACA_PMCINUSE(r8)
1623 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1625 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1627 21: mfspr r5, SPRN_MMCR1
1630 std r4, VCPU_MMCR(r9)
1631 std r5, VCPU_MMCR + 8(r9)
1632 std r6, VCPU_MMCR + 16(r9)
1634 std r10, VCPU_MMCR + 24(r9)
1635 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1636 std r7, VCPU_SIAR(r9)
1637 std r8, VCPU_SDAR(r9)
1644 stw r3, VCPU_PMC(r9)
1645 stw r4, VCPU_PMC + 4(r9)
1646 stw r5, VCPU_PMC + 8(r9)
1647 stw r6, VCPU_PMC + 12(r9)
1648 stw r7, VCPU_PMC + 16(r9)
1649 stw r8, VCPU_PMC + 20(r9)
1652 std r5, VCPU_SIER(r9)
1653 BEGIN_FTR_SECTION_NESTED(96)
1654 mfspr r6, SPRN_SPMC1
1655 mfspr r7, SPRN_SPMC2
1656 mfspr r8, SPRN_MMCRS
1657 stw r6, VCPU_PMC + 24(r9)
1658 stw r7, VCPU_PMC + 28(r9)
1659 std r8, VCPU_MMCR + 32(r9)
1661 mtspr SPRN_MMCRS, r4
1662 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
1663 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1671 /* Restore host values of some registers */
1673 ld r5, STACK_SLOT_TID(r1)
1674 ld r6, STACK_SLOT_PSSCR(r1)
1675 ld r7, STACK_SLOT_PID(r1)
1677 mtspr SPRN_PSSCR, r6
1679 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1682 END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
1685 * POWER7/POWER8 guest -> host partition switch code.
1686 * We don't have to lock against tlbies but we do
1687 * have to coordinate the hardware threads.
1689 kvmhv_switch_to_host:
1690 /* Secondary threads wait for primary to do partition switch */
1691 ld r5,HSTATE_KVM_VCORE(r13)
1692 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1693 lbz r3,HSTATE_PTID(r13)
1697 13: lbz r3,VCORE_IN_GUEST(r5)
1703 /* Primary thread waits for all the secondaries to exit guest */
1704 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1705 rlwinm r0,r3,32-8,0xff
1711 /* Did we actually switch to the guest at all? */
1712 lbz r6, VCORE_IN_GUEST(r5)
1716 /* Primary thread switches back to host partition */
1717 lwz r7,KVM_HOST_LPID(r4)
1719 ld r6,KVM_HOST_SDR1(r4)
1720 li r8,LPID_RSVD /* switch to reserved LPID */
1723 mtspr SPRN_SDR1,r6 /* switch to host page table */
1724 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1729 /* DPDES and VTB are shared between threads */
1730 mfspr r7, SPRN_DPDES
1732 std r7, VCORE_DPDES(r5)
1733 std r8, VCORE_VTB(r5)
1734 /* clear DPDES so we don't get guest doorbells in the host */
1736 mtspr SPRN_DPDES, r8
1737 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1739 /* If HMI, call kvmppc_realmode_hmi_handler() */
1740 cmpwi r12, BOOK3S_INTERRUPT_HMI
1742 bl kvmppc_realmode_hmi_handler
1744 li r12, BOOK3S_INTERRUPT_HMI
1746 * At this point kvmppc_realmode_hmi_handler would have resync-ed
1747 * the TB. Hence it is not required to subtract guest timebase
1748 * offset from timebase. So, skip it.
1750 * Also, do not call kvmppc_subcore_exit_guest() because it has
1751 * been invoked as part of kvmppc_realmode_hmi_handler().
1756 /* Subtract timebase offset from timebase */
1757 ld r8,VCORE_TB_OFFSET(r5)
1760 mftb r6 /* current guest timebase */
1762 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1763 mftb r7 /* check if lower 24 bits overflowed */
1768 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1771 17: bl kvmppc_subcore_exit_guest
1773 30: ld r5,HSTATE_KVM_VCORE(r13)
1774 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1777 ld r0, VCORE_PCR(r5)
1783 /* Signal secondary CPUs to continue */
1784 stb r0,VCORE_IN_GUEST(r5)
1785 19: lis r8,0x7fff /* MAX_INT@h */
1788 16: ld r8,KVM_HOST_LPCR(r4)
1792 /* load host SLB entries */
1793 BEGIN_MMU_FTR_SECTION
1795 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1796 ld r8,PACA_SLBSHADOWPTR(r13)
1798 .rept SLB_NUM_BOLTED
1799 li r3, SLBSHADOW_SAVEAREA
1803 andis. r7,r5,SLB_ESID_V@h
1809 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1810 /* Finish timing, if we have a vcpu */
1811 ld r4, HSTATE_KVM_VCPU(r13)
1815 bl kvmhv_accumulate_time
1818 /* Unset guest mode */
1819 li r0, KVM_GUEST_MODE_NONE
1820 stb r0, HSTATE_IN_GUEST(r13)
1822 ld r0, 112+PPC_LR_STKOFF(r1)
1828 * Check whether an HDSI is an HPTE not found fault or something else.
1829 * If it is an HPTE not found fault that is due to the guest accessing
1830 * a page that they have mapped but which we have paged out, then
1831 * we continue on with the guest exit path. In all other cases,
1832 * reflect the HDSI to the guest as a DSI.
1836 lbz r0, KVM_RADIX(r3)
1839 mfspr r6, SPRN_HDSISR
1840 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
1841 /* HPTE not found fault or protection fault? */
1842 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1843 beq 1f /* if not, send it to the guest */
1844 andi. r0, r11, MSR_DR /* data relocation enabled? */
1847 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
1849 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1851 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1852 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1853 bne 7f /* if no SLB entry found */
1854 4: std r4, VCPU_FAULT_DAR(r9)
1855 stw r6, VCPU_FAULT_DSISR(r9)
1857 /* Search the hash table. */
1858 mr r3, r9 /* vcpu pointer */
1859 li r7, 1 /* data fault */
1860 bl kvmppc_hpte_hv_fault
1861 ld r9, HSTATE_KVM_VCPU(r13)
1863 ld r11, VCPU_MSR(r9)
1864 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1865 cmpdi r3, 0 /* retry the instruction */
1867 cmpdi r3, -1 /* handle in kernel mode */
1869 cmpdi r3, -2 /* MMIO emulation; need instr word */
1872 /* Synthesize a DSI (or DSegI) for the guest */
1873 ld r4, VCPU_FAULT_DAR(r9)
1875 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1876 mtspr SPRN_DSISR, r6
1877 7: mtspr SPRN_DAR, r4
1878 mtspr SPRN_SRR0, r10
1879 mtspr SPRN_SRR1, r11
1881 bl kvmppc_msr_interrupt
1882 fast_interrupt_c_return:
1883 6: ld r7, VCPU_CTR(r9)
1890 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1891 ld r5, KVM_VRMA_SLB_V(r5)
1894 /* If this is for emulated MMIO, load the instruction word */
1895 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1897 /* Set guest mode to 'jump over instruction' so if lwz faults
1898 * we'll just continue at the next IP. */
1899 li r0, KVM_GUEST_MODE_SKIP
1900 stb r0, HSTATE_IN_GUEST(r13)
1902 /* Do the access with MSR:DR enabled */
1904 ori r4, r3, MSR_DR /* Enable paging for data */
1909 /* Store the result */
1910 stw r8, VCPU_LAST_INST(r9)
1912 /* Unset guest mode. */
1913 li r0, KVM_GUEST_MODE_HOST_HV
1914 stb r0, HSTATE_IN_GUEST(r13)
1918 std r4, VCPU_FAULT_DAR(r9)
1919 stw r6, VCPU_FAULT_DSISR(r9)
1922 std r5, VCPU_FAULT_GPA(r9)
1926 * Similarly for an HISI, reflect it to the guest as an ISI unless
1927 * it is an HPTE not found fault for a page that we have paged out.
1931 lbz r0, KVM_RADIX(r3)
1933 bne .Lradix_hisi /* for radix, just save ASDR */
1934 andis. r0, r11, SRR1_ISI_NOPT@h
1936 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1939 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
1941 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1943 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1944 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
1945 bne 7f /* if no SLB entry found */
1947 /* Search the hash table. */
1948 mr r3, r9 /* vcpu pointer */
1951 li r7, 0 /* instruction fault */
1952 bl kvmppc_hpte_hv_fault
1953 ld r9, HSTATE_KVM_VCPU(r13)
1955 ld r11, VCPU_MSR(r9)
1956 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1957 cmpdi r3, 0 /* retry the instruction */
1958 beq fast_interrupt_c_return
1959 cmpdi r3, -1 /* handle in kernel mode */
1962 /* Synthesize an ISI (or ISegI) for the guest */
1964 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
1965 7: mtspr SPRN_SRR0, r10
1966 mtspr SPRN_SRR1, r11
1968 bl kvmppc_msr_interrupt
1969 b fast_interrupt_c_return
1971 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1972 ld r5, KVM_VRMA_SLB_V(r6)
1976 * Try to handle an hcall in real mode.
1977 * Returns to the guest if we handle it, or continues on up to
1978 * the kernel if we can't (i.e. if we don't have a handler for
1979 * it, or if the handler returns H_TOO_HARD).
1981 * r5 - r8 contain hcall args,
1982 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
1984 hcall_try_real_mode:
1985 ld r3,VCPU_GPR(R3)(r9)
1987 /* sc 1 from userspace - reflect to guest syscall */
1988 bne sc_1_fast_return
1990 cmpldi r3,hcall_real_table_end - hcall_real_table
1992 /* See if this hcall is enabled for in-kernel handling */
1994 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1995 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1997 ld r0, KVM_ENABLED_HCALLS(r4)
1998 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2002 /* Get pointer to handler, if any, and call it */
2003 LOAD_REG_ADDR(r4, hcall_real_table)
2009 mr r3,r9 /* get vcpu pointer */
2010 ld r4,VCPU_GPR(R4)(r9)
2013 beq hcall_real_fallback
2014 ld r4,HSTATE_KVM_VCPU(r13)
2015 std r3,VCPU_GPR(R3)(r4)
2023 li r10, BOOK3S_INTERRUPT_SYSCALL
2024 bl kvmppc_msr_interrupt
2028 /* We've attempted a real mode hcall, but it's punted it back
2029 * to userspace. We need to restore some clobbered volatiles
2030 * before resuming the pass-it-to-qemu path */
2031 hcall_real_fallback:
2032 li r12,BOOK3S_INTERRUPT_SYSCALL
2033 ld r9, HSTATE_KVM_VCPU(r13)
2037 .globl hcall_real_table
2039 .long 0 /* 0 - unused */
2040 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2041 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2042 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2043 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2044 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2045 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2046 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2047 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2048 .long 0 /* 0x24 - H_SET_SPRG0 */
2049 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2064 #ifdef CONFIG_KVM_XICS
2065 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2066 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2067 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2068 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2069 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2071 .long 0 /* 0x64 - H_EOI */
2072 .long 0 /* 0x68 - H_CPPR */
2073 .long 0 /* 0x6c - H_IPI */
2074 .long 0 /* 0x70 - H_IPOLL */
2075 .long 0 /* 0x74 - H_XIRR */
2103 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2104 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2120 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2124 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2125 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2126 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2238 #ifdef CONFIG_KVM_XICS
2239 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2241 .long 0 /* 0x2fc - H_XIRR_X*/
2243 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2244 .globl hcall_real_table_end
2245 hcall_real_table_end:
2247 _GLOBAL(kvmppc_h_set_xdabr)
2248 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2250 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2253 6: li r3, H_PARAMETER
2256 _GLOBAL(kvmppc_h_set_dabr)
2257 li r5, DABRX_USER | DABRX_KERNEL
2261 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2262 std r4,VCPU_DABR(r3)
2263 stw r5, VCPU_DABRX(r3)
2264 mtspr SPRN_DABRX, r5
2265 /* Work around P7 bug where DABR can get corrupted on mtspr */
2266 1: mtspr SPRN_DABR,r4
2274 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2275 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2276 rlwimi r5, r4, 2, DAWRX_WT
2278 std r4, VCPU_DAWR(r3)
2279 std r5, VCPU_DAWRX(r3)
2281 mtspr SPRN_DAWRX, r5
2285 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2287 std r11,VCPU_MSR(r3)
2289 stb r0,VCPU_CEDED(r3)
2290 sync /* order setting ceded vs. testing prodded */
2291 lbz r5,VCPU_PRODDED(r3)
2293 bne kvm_cede_prodded
2294 li r12,0 /* set trap to 0 to say hcall is handled */
2295 stw r12,VCPU_TRAP(r3)
2297 std r0,VCPU_GPR(R3)(r3)
2300 * Set our bit in the bitmask of napping threads unless all the
2301 * other threads are already napping, in which case we send this
2304 ld r5,HSTATE_KVM_VCORE(r13)
2305 lbz r6,HSTATE_PTID(r13)
2306 lwz r8,VCORE_ENTRY_EXIT(r5)
2310 addi r6,r5,VCORE_NAPPING_THREADS
2317 /* order napping_threads update vs testing entry_exit_map */
2320 stb r0,HSTATE_NAPPING(r13)
2321 lwz r7,VCORE_ENTRY_EXIT(r5)
2323 bge 33f /* another thread already exiting */
2326 * Although not specifically required by the architecture, POWER7
2327 * preserves the following registers in nap mode, even if an SMT mode
2328 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2329 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2331 /* Save non-volatile GPRs */
2332 std r14, VCPU_GPR(R14)(r3)
2333 std r15, VCPU_GPR(R15)(r3)
2334 std r16, VCPU_GPR(R16)(r3)
2335 std r17, VCPU_GPR(R17)(r3)
2336 std r18, VCPU_GPR(R18)(r3)
2337 std r19, VCPU_GPR(R19)(r3)
2338 std r20, VCPU_GPR(R20)(r3)
2339 std r21, VCPU_GPR(R21)(r3)
2340 std r22, VCPU_GPR(R22)(r3)
2341 std r23, VCPU_GPR(R23)(r3)
2342 std r24, VCPU_GPR(R24)(r3)
2343 std r25, VCPU_GPR(R25)(r3)
2344 std r26, VCPU_GPR(R26)(r3)
2345 std r27, VCPU_GPR(R27)(r3)
2346 std r28, VCPU_GPR(R28)(r3)
2347 std r29, VCPU_GPR(R29)(r3)
2348 std r30, VCPU_GPR(R30)(r3)
2349 std r31, VCPU_GPR(R31)(r3)
2354 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2356 ld r9, HSTATE_KVM_VCPU(r13)
2358 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2362 * Set DEC to the smaller of DEC and HDEC, so that we wake
2363 * no later than the end of our timeslice (HDEC interrupts
2364 * don't wake us from nap).
2373 /* save expiry time of guest decrementer */
2376 ld r4, HSTATE_KVM_VCPU(r13)
2377 ld r5, HSTATE_KVM_VCORE(r13)
2378 ld r6, VCORE_TB_OFFSET(r5)
2379 subf r3, r6, r3 /* convert to host TB value */
2380 std r3, VCPU_DEC_EXPIRES(r4)
2382 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2383 ld r4, HSTATE_KVM_VCPU(r13)
2384 addi r3, r4, VCPU_TB_CEDE
2385 bl kvmhv_accumulate_time
2388 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2391 * Take a nap until a decrementer or external or doobell interrupt
2392 * occurs, with PECE1 and PECE0 set in LPCR.
2393 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2394 * Also clear the runlatch bit before napping.
2397 mfspr r0, SPRN_CTRLF
2399 mtspr SPRN_CTRLT, r0
2402 stb r0,HSTATE_HWTHREAD_REQ(r13)
2404 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2406 ori r5, r5, LPCR_PECEDH
2407 rlwimi r5, r3, 0, LPCR_PECEDP
2408 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2410 kvm_nap_sequence: /* desired LPCR value in r5 */
2413 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2414 * enable state loss = 1 (allow SMT mode switch)
2415 * requested level = 0 (just stop dispatching)
2417 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2418 mtspr SPRN_PSSCR, r3
2419 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2420 li r4, LPCR_PECE_HVEE@higher
2423 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2427 std r0, HSTATE_SCRATCH0(r13)
2429 ld r0, HSTATE_SCRATCH0(r13)
2436 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
2445 /* get vcpu pointer */
2446 ld r4, HSTATE_KVM_VCPU(r13)
2448 /* Woken by external or decrementer interrupt */
2449 ld r1, HSTATE_HOST_R1(r13)
2451 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2452 addi r3, r4, VCPU_TB_RMINTR
2453 bl kvmhv_accumulate_time
2456 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2458 bl kvmppc_restore_tm
2459 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2462 /* load up FP state */
2465 /* Restore guest decrementer */
2466 ld r3, VCPU_DEC_EXPIRES(r4)
2467 ld r5, HSTATE_KVM_VCORE(r13)
2468 ld r6, VCORE_TB_OFFSET(r5)
2469 add r3, r3, r6 /* convert host TB to guest TB value */
2475 ld r14, VCPU_GPR(R14)(r4)
2476 ld r15, VCPU_GPR(R15)(r4)
2477 ld r16, VCPU_GPR(R16)(r4)
2478 ld r17, VCPU_GPR(R17)(r4)
2479 ld r18, VCPU_GPR(R18)(r4)
2480 ld r19, VCPU_GPR(R19)(r4)
2481 ld r20, VCPU_GPR(R20)(r4)
2482 ld r21, VCPU_GPR(R21)(r4)
2483 ld r22, VCPU_GPR(R22)(r4)
2484 ld r23, VCPU_GPR(R23)(r4)
2485 ld r24, VCPU_GPR(R24)(r4)
2486 ld r25, VCPU_GPR(R25)(r4)
2487 ld r26, VCPU_GPR(R26)(r4)
2488 ld r27, VCPU_GPR(R27)(r4)
2489 ld r28, VCPU_GPR(R28)(r4)
2490 ld r29, VCPU_GPR(R29)(r4)
2491 ld r30, VCPU_GPR(R30)(r4)
2492 ld r31, VCPU_GPR(R31)(r4)
2494 /* Check the wake reason in SRR1 to see why we got here */
2495 bl kvmppc_check_wake_reason
2498 * Restore volatile registers since we could have called a
2499 * C routine in kvmppc_check_wake_reason
2501 * r3 tells us whether we need to return to host or not
2502 * WARNING: it gets checked further down:
2503 * should not modify r3 until this check is done.
2505 ld r4, HSTATE_KVM_VCPU(r13)
2507 /* clear our bit in vcore->napping_threads */
2508 34: ld r5,HSTATE_KVM_VCORE(r13)
2509 lbz r7,HSTATE_PTID(r13)
2512 addi r6,r5,VCORE_NAPPING_THREADS
2518 stb r0,HSTATE_NAPPING(r13)
2520 /* See if the wake reason saved in r3 means we need to exit */
2521 stw r12, VCPU_TRAP(r4)
2526 /* see if any other thread is already exiting */
2527 lwz r0,VCORE_ENTRY_EXIT(r5)
2531 b kvmppc_cede_reentry /* if not go back to guest */
2533 /* cede when already previously prodded case */
2536 stb r0,VCPU_PRODDED(r3)
2537 sync /* order testing prodded vs. clearing ceded */
2538 stb r0,VCPU_CEDED(r3)
2542 /* we've ceded but we want to give control to the host */
2544 ld r9, HSTATE_KVM_VCPU(r13)
2547 /* Try to handle a machine check in real mode */
2548 machine_check_realmode:
2549 mr r3, r9 /* get vcpu pointer */
2550 bl kvmppc_realmode_machine_check
2552 ld r9, HSTATE_KVM_VCPU(r13)
2553 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2555 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through
2556 * machine check interrupt (set HSRR0 to 0x200). And for handled
2557 * errors (no-fatal), just go back to guest execution with current
2558 * HSRR0 instead of exiting guest. This new approach will inject
2559 * machine check to guest for fatal error causing guest to crash.
2561 * The old code used to return to host for unhandled errors which
2562 * was causing guest to hang with soft lockups inside guest and
2563 * makes it difficult to recover guest instance.
2565 * if we receive machine check with MSR(RI=0) then deliver it to
2566 * guest as machine check causing guest to crash.
2568 ld r11, VCPU_MSR(r9)
2569 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2570 bne mc_cont /* if so, exit to host */
2571 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2572 beq 1f /* Deliver a machine check to guest */
2574 cmpdi r3, 0 /* Did we handle MCE ? */
2575 bne 2f /* Continue guest execution. */
2576 /* If not, deliver a machine check. SRR0/1 are already set */
2577 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2578 bl kvmppc_msr_interrupt
2579 2: b fast_interrupt_c_return
2582 * Check the reason we woke from nap, and take appropriate action.
2584 * 0 if nothing needs to be done
2585 * 1 if something happened that needs to be handled by the host
2586 * -1 if there was a guest wakeup (IPI or msgsnd)
2587 * -2 if we handled a PCI passthrough interrupt (returned by
2588 * kvmppc_read_intr only)
2590 * Also sets r12 to the interrupt vector for any interrupt that needs
2591 * to be handled now by the host (0x500 for external interrupt), or zero.
2592 * Modifies all volatile registers (since it may call a C function).
2593 * This routine calls kvmppc_read_intr, a C function, if an external
2594 * interrupt is pending.
2596 kvmppc_check_wake_reason:
2599 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2601 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2602 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2603 cmpwi r6, 8 /* was it an external interrupt? */
2604 beq 7f /* if so, see what it was */
2607 cmpwi r6, 6 /* was it the decrementer? */
2610 cmpwi r6, 5 /* privileged doorbell? */
2612 cmpwi r6, 3 /* hypervisor doorbell? */
2614 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2615 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2617 li r3, 1 /* anything else, return 1 */
2620 /* hypervisor doorbell */
2621 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2624 * Clear the doorbell as we will invoke the handler
2625 * explicitly in the guest exit path.
2627 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2629 /* see if it's a host IPI */
2631 lbz r0, HSTATE_HOST_IPI(r13)
2634 /* if not, return -1 */
2638 /* Woken up due to Hypervisor maintenance interrupt */
2639 4: li r12, BOOK3S_INTERRUPT_HMI
2643 /* external interrupt - create a stack frame so we can call C */
2645 std r0, PPC_LR_STKOFF(r1)
2646 stdu r1, -PPC_MIN_STKFRM(r1)
2649 li r12, BOOK3S_INTERRUPT_EXTERNAL
2654 * Return code of 2 means PCI passthrough interrupt, but
2655 * we need to return back to host to complete handling the
2656 * interrupt. Trap reason is expected in r12 by guest
2659 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2661 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2662 addi r1, r1, PPC_MIN_STKFRM
2667 * Save away FP, VMX and VSX registers.
2669 * N.B. r30 and r31 are volatile across this function,
2670 * thus it is not callable from C.
2677 #ifdef CONFIG_ALTIVEC
2679 oris r8,r8,MSR_VEC@h
2680 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2684 oris r8,r8,MSR_VSX@h
2685 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2688 addi r3,r3,VCPU_FPRS
2690 #ifdef CONFIG_ALTIVEC
2692 addi r3,r31,VCPU_VRS
2694 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2696 mfspr r6,SPRN_VRSAVE
2697 stw r6,VCPU_VRSAVE(r31)
2702 * Load up FP, VMX and VSX registers
2704 * N.B. r30 and r31 are volatile across this function,
2705 * thus it is not callable from C.
2712 #ifdef CONFIG_ALTIVEC
2714 oris r8,r8,MSR_VEC@h
2715 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2719 oris r8,r8,MSR_VSX@h
2720 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2723 addi r3,r4,VCPU_FPRS
2725 #ifdef CONFIG_ALTIVEC
2727 addi r3,r31,VCPU_VRS
2729 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2731 lwz r7,VCPU_VRSAVE(r31)
2732 mtspr SPRN_VRSAVE,r7
2737 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2739 * Save transactional state and TM-related registers.
2740 * Called with r9 pointing to the vcpu struct.
2741 * This can modify all checkpointed registers, but
2742 * restores r1, r2 and r9 (vcpu pointer) before exit.
2746 std r0, PPC_LR_STKOFF(r1)
2751 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2755 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2756 beq 1f /* TM not active in guest. */
2758 std r1, HSTATE_HOST_R1(r13)
2759 li r3, TM_CAUSE_KVM_RESCHED
2761 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2765 /* All GPRs are volatile at this point. */
2768 /* Temporarily store r13 and r9 so we have some regs to play with */
2771 std r9, PACATMSCRATCH(r13)
2772 ld r9, HSTATE_KVM_VCPU(r13)
2774 /* Get a few more GPRs free. */
2775 std r29, VCPU_GPRS_TM(29)(r9)
2776 std r30, VCPU_GPRS_TM(30)(r9)
2777 std r31, VCPU_GPRS_TM(31)(r9)
2779 /* Save away PPR and DSCR soon so don't run with user values. */
2782 mfspr r30, SPRN_DSCR
2783 ld r29, HSTATE_DSCR(r13)
2784 mtspr SPRN_DSCR, r29
2786 /* Save all but r9, r13 & r29-r31 */
2789 .if (reg != 9) && (reg != 13)
2790 std reg, VCPU_GPRS_TM(reg)(r9)
2794 /* ... now save r13 */
2796 std r4, VCPU_GPRS_TM(13)(r9)
2797 /* ... and save r9 */
2798 ld r4, PACATMSCRATCH(r13)
2799 std r4, VCPU_GPRS_TM(9)(r9)
2801 /* Reload stack pointer and TOC. */
2802 ld r1, HSTATE_HOST_R1(r13)
2805 /* Set MSR RI now we have r1 and r13 back. */
2809 /* Save away checkpinted SPRs. */
2810 std r31, VCPU_PPR_TM(r9)
2811 std r30, VCPU_DSCR_TM(r9)
2818 std r5, VCPU_LR_TM(r9)
2819 stw r6, VCPU_CR_TM(r9)
2820 std r7, VCPU_CTR_TM(r9)
2821 std r8, VCPU_AMR_TM(r9)
2822 std r10, VCPU_TAR_TM(r9)
2823 std r11, VCPU_XER_TM(r9)
2825 /* Restore r12 as trap number. */
2826 lwz r12, VCPU_TRAP(r9)
2829 addi r3, r9, VCPU_FPRS_TM
2831 addi r3, r9, VCPU_VRS_TM
2833 mfspr r6, SPRN_VRSAVE
2834 stw r6, VCPU_VRSAVE_TM(r9)
2837 * We need to save these SPRs after the treclaim so that the software
2838 * error code is recorded correctly in the TEXASR. Also the user may
2839 * change these outside of a transaction, so they must always be
2842 mfspr r5, SPRN_TFHAR
2843 mfspr r6, SPRN_TFIAR
2844 mfspr r7, SPRN_TEXASR
2845 std r5, VCPU_TFHAR(r9)
2846 std r6, VCPU_TFIAR(r9)
2847 std r7, VCPU_TEXASR(r9)
2849 ld r0, PPC_LR_STKOFF(r1)
2854 * Restore transactional state and TM-related registers.
2855 * Called with r4 pointing to the vcpu struct.
2856 * This potentially modifies all checkpointed registers.
2857 * It restores r1, r2, r4 from the PACA.
2861 std r0, PPC_LR_STKOFF(r1)
2863 /* Turn on TM/FP/VSX/VMX so we can restore them. */
2869 oris r5, r5, (MSR_VEC | MSR_VSX)@h
2873 * The user may change these outside of a transaction, so they must
2874 * always be context switched.
2876 ld r5, VCPU_TFHAR(r4)
2877 ld r6, VCPU_TFIAR(r4)
2878 ld r7, VCPU_TEXASR(r4)
2879 mtspr SPRN_TFHAR, r5
2880 mtspr SPRN_TFIAR, r6
2881 mtspr SPRN_TEXASR, r7
2884 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2885 beqlr /* TM not active in guest */
2886 std r1, HSTATE_HOST_R1(r13)
2888 /* Make sure the failure summary is set, otherwise we'll program check
2889 * when we trechkpt. It's possible that this might have been not set
2890 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
2893 oris r7, r7, (TEXASR_FS)@h
2894 mtspr SPRN_TEXASR, r7
2897 * We need to load up the checkpointed state for the guest.
2898 * We need to do this early as it will blow away any GPRs, VSRs and
2903 addi r3, r31, VCPU_FPRS_TM
2905 addi r3, r31, VCPU_VRS_TM
2908 lwz r7, VCPU_VRSAVE_TM(r4)
2909 mtspr SPRN_VRSAVE, r7
2911 ld r5, VCPU_LR_TM(r4)
2912 lwz r6, VCPU_CR_TM(r4)
2913 ld r7, VCPU_CTR_TM(r4)
2914 ld r8, VCPU_AMR_TM(r4)
2915 ld r9, VCPU_TAR_TM(r4)
2916 ld r10, VCPU_XER_TM(r4)
2925 * Load up PPR and DSCR values but don't put them in the actual SPRs
2926 * till the last moment to avoid running with userspace PPR and DSCR for
2929 ld r29, VCPU_DSCR_TM(r4)
2930 ld r30, VCPU_PPR_TM(r4)
2932 std r2, PACATMSCRATCH(r13) /* Save TOC */
2934 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2938 /* Load GPRs r0-r28 */
2941 ld reg, VCPU_GPRS_TM(reg)(r31)
2945 mtspr SPRN_DSCR, r29
2948 /* Load final GPRs */
2949 ld 29, VCPU_GPRS_TM(29)(r31)
2950 ld 30, VCPU_GPRS_TM(30)(r31)
2951 ld 31, VCPU_GPRS_TM(31)(r31)
2953 /* TM checkpointed state is now setup. All GPRs are now volatile. */
2956 /* Now let's get back the state we need. */
2959 ld r29, HSTATE_DSCR(r13)
2960 mtspr SPRN_DSCR, r29
2961 ld r4, HSTATE_KVM_VCPU(r13)
2962 ld r1, HSTATE_HOST_R1(r13)
2963 ld r2, PACATMSCRATCH(r13)
2965 /* Set the MSR RI since we have our registers back. */
2969 ld r0, PPC_LR_STKOFF(r1)
2975 * We come here if we get any exception or interrupt while we are
2976 * executing host real mode code while in guest MMU context.
2977 * For now just spin, but we should do something better.
2979 kvmppc_bad_host_intr:
2983 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2984 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2985 * r11 has the guest MSR value (in/out)
2986 * r9 has a vcpu pointer (in)
2987 * r0 is used as a scratch register
2989 kvmppc_msr_interrupt:
2990 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2991 cmpwi r0, 2 /* Check if we are in transactional state.. */
2992 ld r11, VCPU_INTR_MSR(r9)
2994 /* ... if transactional, change to suspended */
2996 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3000 * This works around a hardware bug on POWER8E processors, where
3001 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3002 * performance monitor interrupt. Instead, when we need to have
3003 * an interrupt pending, we have to arrange for a counter to overflow.
3007 mtspr SPRN_MMCR2, r3
3008 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3009 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3010 mtspr SPRN_MMCR0, r3
3017 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3019 * Start timing an activity
3020 * r3 = pointer to time accumulation struct, r4 = vcpu
3023 ld r5, HSTATE_KVM_VCORE(r13)
3024 lbz r6, VCORE_IN_GUEST(r5)
3026 beq 5f /* if in guest, need to */
3027 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3030 std r3, VCPU_CUR_ACTIVITY(r4)
3031 std r5, VCPU_ACTIVITY_START(r4)
3035 * Accumulate time to one activity and start another.
3036 * r3 = pointer to new time accumulation struct, r4 = vcpu
3038 kvmhv_accumulate_time:
3039 ld r5, HSTATE_KVM_VCORE(r13)
3040 lbz r8, VCORE_IN_GUEST(r5)
3042 beq 4f /* if in guest, need to */
3043 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
3044 4: ld r5, VCPU_CUR_ACTIVITY(r4)
3045 ld r6, VCPU_ACTIVITY_START(r4)
3046 std r3, VCPU_CUR_ACTIVITY(r4)
3049 std r7, VCPU_ACTIVITY_START(r4)
3053 ld r8, TAS_SEQCOUNT(r5)
3056 std r8, TAS_SEQCOUNT(r5)
3058 ld r7, TAS_TOTAL(r5)
3060 std r7, TAS_TOTAL(r5)
3066 3: std r3, TAS_MIN(r5)
3072 std r8, TAS_SEQCOUNT(r5)
projects / mirror_ubuntu-artful-kernel.git / blob