2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
33 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
35 #ifdef __LITTLE_ENDIAN__
36 #error Need to fix lppaca and SLB shadow accesses in little endian mode
39 /* Values in HSTATE_NAPPING(r13) */
40 #define NAPPING_CEDE 1
41 #define NAPPING_NOVCPU 2
44 * Call kvmppc_hv_entry in real mode.
45 * Must be called with interrupts hard-disabled.
49 * LR = return address to continue at after eventually re-enabling MMU
51 _GLOBAL(kvmppc_hv_entry_trampoline)
53 std r0, PPC_LR_STKOFF(r1)
56 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
61 mtmsrd r0,1 /* clear RI in MSR */
67 ld r4, HSTATE_KVM_VCPU(r13)
70 /* Back from guest - restore host state and return to caller */
73 /* Restore host DABR and DABRX */
74 ld r5,HSTATE_DABR(r13)
78 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
81 ld r3,PACA_SPRG_VDSO(r13)
82 mtspr SPRN_SPRG_VDSO_WRITE,r3
84 /* Reload the host's PMU registers */
85 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
86 lbz r4, LPPACA_PMCINUSE(r3)
88 beq 23f /* skip if not */
90 ld r3, HSTATE_MMCR(r13)
91 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
94 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
95 lwz r3, HSTATE_PMC(r13)
96 lwz r4, HSTATE_PMC + 4(r13)
97 lwz r5, HSTATE_PMC + 8(r13)
98 lwz r6, HSTATE_PMC + 12(r13)
99 lwz r8, HSTATE_PMC + 16(r13)
100 lwz r9, HSTATE_PMC + 20(r13)
102 lwz r10, HSTATE_PMC + 24(r13)
103 lwz r11, HSTATE_PMC + 28(r13)
104 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
114 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
115 ld r3, HSTATE_MMCR(r13)
116 ld r4, HSTATE_MMCR + 8(r13)
117 ld r5, HSTATE_MMCR + 16(r13)
118 ld r6, HSTATE_MMCR + 24(r13)
119 ld r7, HSTATE_MMCR + 32(r13)
125 ld r8, HSTATE_MMCR + 40(r13)
126 ld r9, HSTATE_MMCR + 48(r13)
129 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
135 * Reload DEC. HDEC interrupts were disabled when
136 * we reloaded the host's LPCR value.
138 ld r3, HSTATE_DECEXP(r13)
144 * For external and machine check interrupts, we need
145 * to call the Linux handler to process the interrupt.
146 * We do that by jumping to absolute address 0x500 for
147 * external interrupts, or the machine_check_fwnmi label
148 * for machine checks (since firmware might have patched
149 * the vector area at 0x200). The [h]rfid at the end of the
150 * handler will return to the book3s_hv_interrupts.S code.
151 * For other interrupts we do the rfid to get back
152 * to the book3s_hv_interrupts.S code here.
154 ld r8, 112+PPC_LR_STKOFF(r1)
156 ld r7, HSTATE_HOST_MSR(r13)
158 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
159 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
162 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
164 /* RFI into the highmem handler, or branch to interrupt handler */
168 mtmsrd r6, 1 /* Clear RI in MSR */
171 beqa 0x500 /* external interrupt (PPC970) */
172 beq cr1, 13f /* machine check */
175 /* On POWER7, we have external interrupts set to use HSRR0/1 */
176 11: mtspr SPRN_HSRR0, r8
180 13: b machine_check_fwnmi
182 kvmppc_primary_no_guest:
183 /* We handle this much like a ceded vcpu */
184 /* set our bit in napping_threads */
185 ld r5, HSTATE_KVM_VCORE(r13)
186 lbz r7, HSTATE_PTID(r13)
189 addi r6, r5, VCORE_NAPPING_THREADS
194 /* order napping_threads update vs testing entry_exit_count */
197 lwz r7, VCORE_ENTRY_EXIT(r5)
199 bge kvm_novcpu_exit /* another thread already exiting */
200 li r3, NAPPING_NOVCPU
201 stb r3, HSTATE_NAPPING(r13)
203 stb r3, HSTATE_HWTHREAD_REQ(r13)
208 ld r1, HSTATE_HOST_R1(r13)
209 ld r5, HSTATE_KVM_VCORE(r13)
211 stb r0, HSTATE_NAPPING(r13)
212 stb r0, HSTATE_HWTHREAD_REQ(r13)
214 /* check the wake reason */
215 bl kvmppc_check_wake_reason
217 /* see if any other thread is already exiting */
218 lwz r0, VCORE_ENTRY_EXIT(r5)
222 /* clear our bit in napping_threads */
223 lbz r7, HSTATE_PTID(r13)
226 addi r6, r5, VCORE_NAPPING_THREADS
232 /* See if the wake reason means we need to exit */
236 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
237 ld r4, HSTATE_KVM_VCPU(r13)
245 * We come in here when wakened from nap mode.
246 * Relocation is off and most register values are lost.
247 * r13 points to the PACA.
249 .globl kvm_start_guest
252 /* Set runlatch bit the minute you wake up from nap */
259 li r0,KVM_HWTHREAD_IN_KVM
260 stb r0,HSTATE_HWTHREAD_STATE(r13)
262 /* NV GPR values from power7_idle() will no longer be valid */
264 stb r0,PACA_NAPSTATELOST(r13)
266 /* were we napping due to cede? */
267 lbz r0,HSTATE_NAPPING(r13)
268 cmpwi r0,NAPPING_CEDE
270 cmpwi r0,NAPPING_NOVCPU
271 beq kvm_novcpu_wakeup
273 ld r1,PACAEMERGSP(r13)
274 subi r1,r1,STACK_FRAME_OVERHEAD
277 * We weren't napping due to cede, so this must be a secondary
278 * thread being woken up to run a guest, or being woken up due
279 * to a stray IPI. (Or due to some machine check or hypervisor
280 * maintenance interrupt while the core is in KVM.)
283 /* Check the wake reason in SRR1 to see why we got here */
284 bl kvmppc_check_wake_reason
288 /* get vcpu pointer, NULL if we have no vcpu to run */
289 ld r4,HSTATE_KVM_VCPU(r13)
291 /* if we have no vcpu to run, go back to sleep */
294 /* Set HSTATE_DSCR(r13) to something sensible */
295 LOAD_REG_ADDR(r6, dscr_default)
297 std r6, HSTATE_DSCR(r13)
301 /* Back from the guest, go back to nap */
302 /* Clear our vcpu pointer so we don't come back in early */
304 std r0, HSTATE_KVM_VCPU(r13)
306 * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing
307 * the nap_count, because once the increment to nap_count is
308 * visible we could be given another vcpu.
312 /* increment the nap count and then go to nap mode */
313 ld r4, HSTATE_KVM_VCORE(r13)
314 addi r4, r4, VCORE_NAP_COUNT
321 li r0, KVM_HWTHREAD_IN_NAP
322 stb r0, HSTATE_HWTHREAD_STATE(r13)
324 /* Clear the runlatch bit before napping */
331 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
334 std r0, HSTATE_SCRATCH0(r13)
336 ld r0, HSTATE_SCRATCH0(r13)
342 /******************************************************************************
346 *****************************************************************************/
348 .global kvmppc_hv_entry
353 * R4 = vcpu pointer (or NULL)
357 * all other volatile GPRS = free
360 std r0, PPC_LR_STKOFF(r1)
363 /* Save R1 in the PACA */
364 std r1, HSTATE_HOST_R1(r13)
366 li r6, KVM_GUEST_MODE_HOST_HV
367 stb r6, HSTATE_IN_GUEST(r13)
377 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
379 * POWER7 host -> guest partition switch code.
380 * We don't have to lock against concurrent tlbies,
381 * but we do have to coordinate across hardware threads.
383 /* Increment entry count iff exit count is zero. */
384 ld r5,HSTATE_KVM_VCORE(r13)
385 addi r9,r5,VCORE_ENTRY_EXIT
387 cmpwi r3,0x100 /* any threads starting to exit? */
388 bge secondary_too_late /* if so we're too late to the party */
393 /* Primary thread switches to guest partition. */
394 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
395 lbz r6,HSTATE_PTID(r13)
400 li r0,LPID_RSVD /* switch to reserved LPID */
403 mtspr SPRN_SDR1,r6 /* switch to partition page table */
407 /* See if we need to flush the TLB */
408 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
409 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
410 srdi r6,r6,6 /* doubleword number */
411 sldi r6,r6,3 /* address offset */
413 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
419 23: ldarx r7,0,r6 /* if set, clear the bit */
423 /* Flush the TLB of any entries for this LPID */
424 /* use arch 2.07S as a proxy for POWER8 */
426 li r6,512 /* POWER8 has 512 sets */
428 li r6,128 /* POWER7 has 128 sets */
429 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
431 li r7,0x800 /* IS field = 0b10 */
438 /* Add timebase offset onto timebase */
439 22: ld r8,VCORE_TB_OFFSET(r5)
442 mftb r6 /* current host timebase */
444 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
445 mftb r7 /* check if lower 24 bits overflowed */
450 addis r8,r8,0x100 /* if so, increment upper 40 bits */
453 /* Load guest PCR value to select appropriate compat mode */
454 37: ld r7, VCORE_PCR(r5)
461 /* DPDES is shared between threads */
462 ld r8, VCORE_DPDES(r5)
464 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
467 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
470 /* Secondary threads wait for primary to have done partition switch */
471 20: lbz r0,VCORE_IN_GUEST(r5)
475 /* Set LPCR and RMOR. */
476 10: ld r8,VCORE_LPCR(r5)
482 /* Check if HDEC expires soon */
484 cmpwi r3,512 /* 1 microsecond */
485 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
490 * PPC970 host -> guest partition switch code.
491 * We have to lock against concurrent tlbies,
492 * using native_tlbie_lock to lock against host tlbies
493 * and kvm->arch.tlbie_lock to lock against guest tlbies.
494 * We also have to invalidate the TLB since its
495 * entries aren't tagged with the LPID.
497 30: ld r5,HSTATE_KVM_VCORE(r13)
498 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
500 /* first take native_tlbie_lock */
503 .tc native_tlbie_lock[TC],native_tlbie_lock
505 ld r3,toc_tlbie_lock@toc(2)
506 #ifdef __BIG_ENDIAN__
507 lwz r8,PACA_LOCK_TOKEN(r13)
509 lwz r8,PACAPACAINDEX(r13)
518 ld r5,HSTATE_KVM_VCORE(r13)
519 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
521 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
525 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
528 stw r0,0(r3) /* drop native_tlbie_lock */
530 /* invalidate the whole TLB */
539 /* Take the guest's tlbie_lock */
540 addi r3,r9,KVM_TLBIE_LOCK
548 mtspr SPRN_SDR1,r6 /* switch to partition page table */
550 /* Set up HID4 with the guest's LPID etc. */
555 /* drop the guest's tlbie_lock */
559 /* Check if HDEC expires soon */
562 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
565 /* Enable HDEC interrupts */
568 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
578 /* Do we have a guest vcpu to run? */
580 beq kvmppc_primary_no_guest
583 /* Load up guest SLB entries */
584 lwz r5,VCPU_SLB_MAX(r4)
589 1: ld r8,VCPU_SLB_E(r6)
592 addi r6,r6,VCPU_SLB_SIZE
595 /* Increment yield count if they have a VPA */
599 lwz r5, LPPACA_YIELDCOUNT(r3)
601 stw r5, LPPACA_YIELDCOUNT(r3)
603 stb r6, VCPU_VPA_DIRTY(r4)
607 /* Save purr/spurr */
610 std r5,HSTATE_PURR(r13)
611 std r6,HSTATE_SPURR(r13)
616 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
619 /* Set partition DABR */
620 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
621 lwz r5,VCPU_DABRX(r4)
625 BEGIN_FTR_SECTION_NESTED(89)
627 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
628 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
630 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
633 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
635 /* Turn on TM/FP/VSX/VMX so we can restore them. */
641 oris r5, r5, (MSR_VEC | MSR_VSX)@h
645 * The user may change these outside of a transaction, so they must
646 * always be context switched.
648 ld r5, VCPU_TFHAR(r4)
649 ld r6, VCPU_TFIAR(r4)
650 ld r7, VCPU_TEXASR(r4)
653 mtspr SPRN_TEXASR, r7
656 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
657 beq skip_tm /* TM not active in guest */
659 /* Make sure the failure summary is set, otherwise we'll program check
660 * when we trechkpt. It's possible that this might have been not set
661 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
664 oris r7, r7, (TEXASR_FS)@h
665 mtspr SPRN_TEXASR, r7
668 * We need to load up the checkpointed state for the guest.
669 * We need to do this early as it will blow away any GPRs, VSRs and
674 addi r3, r31, VCPU_FPRS_TM
676 addi r3, r31, VCPU_VRS_TM
679 lwz r7, VCPU_VRSAVE_TM(r4)
680 mtspr SPRN_VRSAVE, r7
682 ld r5, VCPU_LR_TM(r4)
683 lwz r6, VCPU_CR_TM(r4)
684 ld r7, VCPU_CTR_TM(r4)
685 ld r8, VCPU_AMR_TM(r4)
686 ld r9, VCPU_TAR_TM(r4)
694 * Load up PPR and DSCR values but don't put them in the actual SPRs
695 * till the last moment to avoid running with userspace PPR and DSCR for
698 ld r29, VCPU_DSCR_TM(r4)
699 ld r30, VCPU_PPR_TM(r4)
701 std r2, PACATMSCRATCH(r13) /* Save TOC */
703 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
707 /* Load GPRs r0-r28 */
710 ld reg, VCPU_GPRS_TM(reg)(r31)
717 /* Load final GPRs */
718 ld 29, VCPU_GPRS_TM(29)(r31)
719 ld 30, VCPU_GPRS_TM(30)(r31)
720 ld 31, VCPU_GPRS_TM(31)(r31)
722 /* TM checkpointed state is now setup. All GPRs are now volatile. */
725 /* Now let's get back the state we need. */
728 ld r29, HSTATE_DSCR(r13)
730 ld r4, HSTATE_KVM_VCPU(r13)
731 ld r1, HSTATE_HOST_R1(r13)
732 ld r2, PACATMSCRATCH(r13)
734 /* Set the MSR RI since we have our registers back. */
740 /* Load guest PMU registers */
741 /* R4 is live here (vcpu pointer) */
743 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
744 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
748 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
751 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
752 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
753 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
754 lwz r6, VCPU_PMC + 8(r4)
755 lwz r7, VCPU_PMC + 12(r4)
756 lwz r8, VCPU_PMC + 16(r4)
757 lwz r9, VCPU_PMC + 20(r4)
759 lwz r10, VCPU_PMC + 24(r4)
760 lwz r11, VCPU_PMC + 28(r4)
761 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
771 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
773 ld r5, VCPU_MMCR + 8(r4)
774 ld r6, VCPU_MMCR + 16(r4)
782 ld r5, VCPU_MMCR + 24(r4)
784 lwz r7, VCPU_PMC + 24(r4)
785 lwz r8, VCPU_PMC + 28(r4)
786 ld r9, VCPU_MMCR + 32(r4)
792 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
796 /* Load up FP, VMX and VSX registers */
799 ld r14, VCPU_GPR(R14)(r4)
800 ld r15, VCPU_GPR(R15)(r4)
801 ld r16, VCPU_GPR(R16)(r4)
802 ld r17, VCPU_GPR(R17)(r4)
803 ld r18, VCPU_GPR(R18)(r4)
804 ld r19, VCPU_GPR(R19)(r4)
805 ld r20, VCPU_GPR(R20)(r4)
806 ld r21, VCPU_GPR(R21)(r4)
807 ld r22, VCPU_GPR(R22)(r4)
808 ld r23, VCPU_GPR(R23)(r4)
809 ld r24, VCPU_GPR(R24)(r4)
810 ld r25, VCPU_GPR(R25)(r4)
811 ld r26, VCPU_GPR(R26)(r4)
812 ld r27, VCPU_GPR(R27)(r4)
813 ld r28, VCPU_GPR(R28)(r4)
814 ld r29, VCPU_GPR(R29)(r4)
815 ld r30, VCPU_GPR(R30)(r4)
816 ld r31, VCPU_GPR(R31)(r4)
819 /* Switch DSCR to guest value */
822 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
825 /* Skip next section on POWER7 or PPC970 */
827 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
828 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
831 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
834 /* Load up POWER8-specific registers */
836 lwz r6, VCPU_PSPB(r4)
842 ld r6, VCPU_DAWRX(r4)
843 ld r7, VCPU_CIABR(r4)
853 ld r8, VCPU_EBBHR(r4)
855 ld r5, VCPU_EBBRR(r4)
856 ld r6, VCPU_BESCR(r4)
857 ld r7, VCPU_CSIGR(r4)
863 ld r5, VCPU_TCSCR(r4)
865 lwz r7, VCPU_GUEST_PID(r4)
874 * Set the decrementer to the guest decrementer.
876 ld r8,VCPU_DEC_EXPIRES(r4)
877 /* r8 is a host timebase value here, convert to guest TB */
878 ld r5,HSTATE_KVM_VCORE(r13)
879 ld r6,VCORE_TB_OFFSET(r5)
886 ld r5, VCPU_SPRG0(r4)
887 ld r6, VCPU_SPRG1(r4)
888 ld r7, VCPU_SPRG2(r4)
889 ld r8, VCPU_SPRG3(r4)
895 /* Load up DAR and DSISR */
897 lwz r6, VCPU_DSISR(r4)
902 /* Restore AMR and UAMOR, set AMOR to all 1s */
909 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
911 /* Restore state of CTRL run bit; assume 1 on entry */
925 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
933 deliver_guest_interrupt:
934 /* r11 = vcpu->arch.msr & ~MSR_HV */
935 rldicl r11, r11, 63 - MSR_HV_LG, 1
936 rotldi r11, r11, 1 + MSR_HV_LG
939 /* Check if we can deliver an external or decrementer interrupt now */
940 ld r0, VCPU_PENDING_EXC(r4)
941 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
943 andi. r8, r11, MSR_EE
946 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
947 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
950 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
952 li r0, BOOK3S_INTERRUPT_EXTERNAL
956 li r0, BOOK3S_INTERRUPT_DECREMENTER
959 12: mtspr SPRN_SRR0, r10
963 bl kvmppc_msr_interrupt
969 * R10: value for HSRR0
970 * R11: value for HSRR1
975 stb r0,VCPU_CEDED(r4) /* cancel cede */
979 /* Activate guest mode, so faults get handled by KVM */
980 li r9, KVM_GUEST_MODE_GUEST_HV
981 stb r9, HSTATE_IN_GUEST(r13)
988 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
991 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
998 ld r1, VCPU_GPR(R1)(r4)
999 ld r2, VCPU_GPR(R2)(r4)
1000 ld r3, VCPU_GPR(R3)(r4)
1001 ld r5, VCPU_GPR(R5)(r4)
1002 ld r6, VCPU_GPR(R6)(r4)
1003 ld r7, VCPU_GPR(R7)(r4)
1004 ld r8, VCPU_GPR(R8)(r4)
1005 ld r9, VCPU_GPR(R9)(r4)
1006 ld r10, VCPU_GPR(R10)(r4)
1007 ld r11, VCPU_GPR(R11)(r4)
1008 ld r12, VCPU_GPR(R12)(r4)
1009 ld r13, VCPU_GPR(R13)(r4)
1013 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1014 ld r0, VCPU_GPR(R0)(r4)
1015 ld r4, VCPU_GPR(R4)(r4)
1020 /******************************************************************************
1024 *****************************************************************************/
1027 * We come here from the first-level interrupt handlers.
1029 .globl kvmppc_interrupt_hv
1030 kvmppc_interrupt_hv:
1032 * Register contents:
1033 * R12 = interrupt vector
1035 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1036 * guest R13 saved in SPRN_SCRATCH0
1038 std r9, HSTATE_SCRATCH2(r13)
1040 lbz r9, HSTATE_IN_GUEST(r13)
1041 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1042 beq kvmppc_bad_host_intr
1043 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1044 cmpwi r9, KVM_GUEST_MODE_GUEST
1045 ld r9, HSTATE_SCRATCH2(r13)
1046 beq kvmppc_interrupt_pr
1048 /* We're now back in the host but in guest MMU context */
1049 li r9, KVM_GUEST_MODE_HOST_HV
1050 stb r9, HSTATE_IN_GUEST(r13)
1052 ld r9, HSTATE_KVM_VCPU(r13)
1054 /* Save registers */
1056 std r0, VCPU_GPR(R0)(r9)
1057 std r1, VCPU_GPR(R1)(r9)
1058 std r2, VCPU_GPR(R2)(r9)
1059 std r3, VCPU_GPR(R3)(r9)
1060 std r4, VCPU_GPR(R4)(r9)
1061 std r5, VCPU_GPR(R5)(r9)
1062 std r6, VCPU_GPR(R6)(r9)
1063 std r7, VCPU_GPR(R7)(r9)
1064 std r8, VCPU_GPR(R8)(r9)
1065 ld r0, HSTATE_SCRATCH2(r13)
1066 std r0, VCPU_GPR(R9)(r9)
1067 std r10, VCPU_GPR(R10)(r9)
1068 std r11, VCPU_GPR(R11)(r9)
1069 ld r3, HSTATE_SCRATCH0(r13)
1070 lwz r4, HSTATE_SCRATCH1(r13)
1071 std r3, VCPU_GPR(R12)(r9)
1074 ld r3, HSTATE_CFAR(r13)
1075 std r3, VCPU_CFAR(r9)
1076 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1078 ld r4, HSTATE_PPR(r13)
1079 std r4, VCPU_PPR(r9)
1080 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1082 /* Restore R1/R2 so we can handle faults */
1083 ld r1, HSTATE_HOST_R1(r13)
1086 mfspr r10, SPRN_SRR0
1087 mfspr r11, SPRN_SRR1
1088 std r10, VCPU_SRR0(r9)
1089 std r11, VCPU_SRR1(r9)
1090 andi. r0, r12, 2 /* need to read HSRR0/1? */
1092 mfspr r10, SPRN_HSRR0
1093 mfspr r11, SPRN_HSRR1
1095 1: std r10, VCPU_PC(r9)
1096 std r11, VCPU_MSR(r9)
1100 std r3, VCPU_GPR(R13)(r9)
1103 stw r12,VCPU_TRAP(r9)
1105 /* Save HEIR (HV emulation assist reg) in last_inst
1106 if this is an HEI (HV emulation interrupt, e40) */
1107 li r3,KVM_INST_FETCH_FAILED
1109 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1112 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1113 11: stw r3,VCPU_LAST_INST(r9)
1115 /* these are volatile across C function calls */
1118 std r3, VCPU_CTR(r9)
1119 stw r4, VCPU_XER(r9)
1122 /* If this is a page table miss then see if it's theirs or ours */
1123 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1125 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1127 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1129 /* See if this is a leftover HDEC interrupt */
1130 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1136 /* See if this is an hcall we can handle in real mode */
1137 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1138 beq hcall_try_real_mode
1140 /* Only handle external interrupts here on arch 206 and later */
1142 b ext_interrupt_to_host
1143 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1145 /* External interrupt ? */
1146 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1147 bne+ ext_interrupt_to_host
1149 /* External interrupt, first check for host_ipi. If this is
1150 * set, we know the host wants us out so let's do it now
1154 bgt ext_interrupt_to_host
1156 /* Check if any CPU is heading out to the host, if so head out too */
1157 ld r5, HSTATE_KVM_VCORE(r13)
1158 lwz r0, VCORE_ENTRY_EXIT(r5)
1160 bge ext_interrupt_to_host
1162 /* Return to guest after delivering any pending interrupt */
1164 b deliver_guest_interrupt
1166 ext_interrupt_to_host:
1168 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1169 /* Save more register state */
1172 std r6, VCPU_DAR(r9)
1173 stw r7, VCPU_DSISR(r9)
1175 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1176 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1178 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1179 std r6, VCPU_FAULT_DAR(r9)
1180 stw r7, VCPU_FAULT_DSISR(r9)
1182 /* See if it is a machine check */
1183 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1184 beq machine_check_realmode
1187 /* Save guest CTRL register, set runlatch to 1 */
1188 6: mfspr r6,SPRN_CTRLF
1189 stw r6,VCPU_CTRL(r9)
1195 /* Read the guest SLB and save it away */
1196 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1202 andis. r0,r8,SLB_ESID_V@h
1204 add r8,r8,r6 /* put index in */
1206 std r8,VCPU_SLB_E(r7)
1207 std r3,VCPU_SLB_V(r7)
1208 addi r7,r7,VCPU_SLB_SIZE
1212 stw r5,VCPU_SLB_MAX(r9)
1215 * Save the guest PURR/SPURR
1221 ld r8,VCPU_SPURR(r9)
1222 std r5,VCPU_PURR(r9)
1223 std r6,VCPU_SPURR(r9)
1228 * Restore host PURR/SPURR and add guest times
1229 * so that the time in the guest gets accounted.
1231 ld r3,HSTATE_PURR(r13)
1232 ld r4,HSTATE_SPURR(r13)
1237 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
1244 /* r5 is a guest timebase value here, convert to host TB */
1245 ld r3,HSTATE_KVM_VCORE(r13)
1246 ld r4,VCORE_TB_OFFSET(r3)
1248 std r5,VCPU_DEC_EXPIRES(r9)
1252 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1253 /* Save POWER8-specific registers */
1257 std r5, VCPU_IAMR(r9)
1258 stw r6, VCPU_PSPB(r9)
1259 std r7, VCPU_FSCR(r9)
1264 std r6, VCPU_VTB(r9)
1265 std r7, VCPU_TAR(r9)
1266 mfspr r8, SPRN_EBBHR
1267 std r8, VCPU_EBBHR(r9)
1268 mfspr r5, SPRN_EBBRR
1269 mfspr r6, SPRN_BESCR
1270 mfspr r7, SPRN_CSIGR
1272 std r5, VCPU_EBBRR(r9)
1273 std r6, VCPU_BESCR(r9)
1274 std r7, VCPU_CSIGR(r9)
1275 std r8, VCPU_TACR(r9)
1276 mfspr r5, SPRN_TCSCR
1280 std r5, VCPU_TCSCR(r9)
1281 std r6, VCPU_ACOP(r9)
1282 stw r7, VCPU_GUEST_PID(r9)
1283 std r8, VCPU_WORT(r9)
1286 /* Save and reset AMR and UAMOR before turning on the MMU */
1291 std r6,VCPU_UAMOR(r9)
1294 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1296 /* Switch DSCR back to host value */
1299 ld r7, HSTATE_DSCR(r13)
1300 std r8, VCPU_DSCR(r9)
1302 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1304 /* Save non-volatile GPRs */
1305 std r14, VCPU_GPR(R14)(r9)
1306 std r15, VCPU_GPR(R15)(r9)
1307 std r16, VCPU_GPR(R16)(r9)
1308 std r17, VCPU_GPR(R17)(r9)
1309 std r18, VCPU_GPR(R18)(r9)
1310 std r19, VCPU_GPR(R19)(r9)
1311 std r20, VCPU_GPR(R20)(r9)
1312 std r21, VCPU_GPR(R21)(r9)
1313 std r22, VCPU_GPR(R22)(r9)
1314 std r23, VCPU_GPR(R23)(r9)
1315 std r24, VCPU_GPR(R24)(r9)
1316 std r25, VCPU_GPR(R25)(r9)
1317 std r26, VCPU_GPR(R26)(r9)
1318 std r27, VCPU_GPR(R27)(r9)
1319 std r28, VCPU_GPR(R28)(r9)
1320 std r29, VCPU_GPR(R29)(r9)
1321 std r30, VCPU_GPR(R30)(r9)
1322 std r31, VCPU_GPR(R31)(r9)
1325 mfspr r3, SPRN_SPRG0
1326 mfspr r4, SPRN_SPRG1
1327 mfspr r5, SPRN_SPRG2
1328 mfspr r6, SPRN_SPRG3
1329 std r3, VCPU_SPRG0(r9)
1330 std r4, VCPU_SPRG1(r9)
1331 std r5, VCPU_SPRG2(r9)
1332 std r6, VCPU_SPRG3(r9)
1338 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1341 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
1345 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1349 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
1350 beq 1f /* TM not active in guest. */
1352 li r3, TM_CAUSE_KVM_RESCHED
1354 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
1358 /* All GPRs are volatile at this point. */
1361 /* Temporarily store r13 and r9 so we have some regs to play with */
1364 std r9, PACATMSCRATCH(r13)
1365 ld r9, HSTATE_KVM_VCPU(r13)
1367 /* Get a few more GPRs free. */
1368 std r29, VCPU_GPRS_TM(29)(r9)
1369 std r30, VCPU_GPRS_TM(30)(r9)
1370 std r31, VCPU_GPRS_TM(31)(r9)
1372 /* Save away PPR and DSCR soon so don't run with user values. */
1375 mfspr r30, SPRN_DSCR
1376 ld r29, HSTATE_DSCR(r13)
1377 mtspr SPRN_DSCR, r29
1379 /* Save all but r9, r13 & r29-r31 */
1382 .if (reg != 9) && (reg != 13)
1383 std reg, VCPU_GPRS_TM(reg)(r9)
1387 /* ... now save r13 */
1389 std r4, VCPU_GPRS_TM(13)(r9)
1390 /* ... and save r9 */
1391 ld r4, PACATMSCRATCH(r13)
1392 std r4, VCPU_GPRS_TM(9)(r9)
1394 /* Reload stack pointer and TOC. */
1395 ld r1, HSTATE_HOST_R1(r13)
1398 /* Set MSR RI now we have r1 and r13 back. */
1402 /* Save away checkpinted SPRs. */
1403 std r31, VCPU_PPR_TM(r9)
1404 std r30, VCPU_DSCR_TM(r9)
1410 std r5, VCPU_LR_TM(r9)
1411 stw r6, VCPU_CR_TM(r9)
1412 std r7, VCPU_CTR_TM(r9)
1413 std r8, VCPU_AMR_TM(r9)
1414 std r10, VCPU_TAR_TM(r9)
1416 /* Restore r12 as trap number. */
1417 lwz r12, VCPU_TRAP(r9)
1420 addi r3, r9, VCPU_FPRS_TM
1422 addi r3, r9, VCPU_VRS_TM
1424 mfspr r6, SPRN_VRSAVE
1425 stw r6, VCPU_VRSAVE_TM(r9)
1428 * We need to save these SPRs after the treclaim so that the software
1429 * error code is recorded correctly in the TEXASR. Also the user may
1430 * change these outside of a transaction, so they must always be
1433 mfspr r5, SPRN_TFHAR
1434 mfspr r6, SPRN_TFIAR
1435 mfspr r7, SPRN_TEXASR
1436 std r5, VCPU_TFHAR(r9)
1437 std r6, VCPU_TFIAR(r9)
1438 std r7, VCPU_TEXASR(r9)
1442 /* Increment yield count if they have a VPA */
1443 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1446 lwz r3, LPPACA_YIELDCOUNT(r8)
1448 stw r3, LPPACA_YIELDCOUNT(r8)
1450 stb r3, VCPU_VPA_DIRTY(r9)
1452 /* Save PMU registers if requested */
1453 /* r8 and cr0.eq are live here */
1456 * POWER8 seems to have a hardware bug where setting
1457 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1458 * when some counters are already negative doesn't seem
1459 * to cause a performance monitor alert (and hence interrupt).
1460 * The effect of this is that when saving the PMU state,
1461 * if there is no PMU alert pending when we read MMCR0
1462 * before freezing the counters, but one becomes pending
1463 * before we read the counters, we lose it.
1464 * To work around this, we need a way to freeze the counters
1465 * before reading MMCR0. Normally, freezing the counters
1466 * is done by writing MMCR0 (to set MMCR0[FC]) which
1467 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1468 * we can also freeze the counters using MMCR2, by writing
1469 * 1s to all the counter freeze condition bits (there are
1470 * 9 bits each for 6 counters).
1472 li r3, -1 /* set all freeze bits */
1474 mfspr r10, SPRN_MMCR2
1475 mtspr SPRN_MMCR2, r3
1477 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1479 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1480 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1481 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1482 mfspr r6, SPRN_MMCRA
1484 /* On P7, clear MMCRA in order to disable SDAR updates */
1486 mtspr SPRN_MMCRA, r7
1487 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1489 beq 21f /* if no VPA, save PMU stuff anyway */
1490 lbz r7, LPPACA_PMCINUSE(r8)
1491 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1493 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1495 21: mfspr r5, SPRN_MMCR1
1498 std r4, VCPU_MMCR(r9)
1499 std r5, VCPU_MMCR + 8(r9)
1500 std r6, VCPU_MMCR + 16(r9)
1502 std r10, VCPU_MMCR + 24(r9)
1503 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1504 std r7, VCPU_SIAR(r9)
1505 std r8, VCPU_SDAR(r9)
1513 mfspr r10, SPRN_PMC7
1514 mfspr r11, SPRN_PMC8
1515 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1516 stw r3, VCPU_PMC(r9)
1517 stw r4, VCPU_PMC + 4(r9)
1518 stw r5, VCPU_PMC + 8(r9)
1519 stw r6, VCPU_PMC + 12(r9)
1520 stw r7, VCPU_PMC + 16(r9)
1521 stw r8, VCPU_PMC + 20(r9)
1523 stw r10, VCPU_PMC + 24(r9)
1524 stw r11, VCPU_PMC + 28(r9)
1525 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1528 mfspr r6, SPRN_SPMC1
1529 mfspr r7, SPRN_SPMC2
1530 mfspr r8, SPRN_MMCRS
1531 std r5, VCPU_SIER(r9)
1532 stw r6, VCPU_PMC + 24(r9)
1533 stw r7, VCPU_PMC + 28(r9)
1534 std r8, VCPU_MMCR + 32(r9)
1536 mtspr SPRN_MMCRS, r4
1537 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1545 hdec_soon: /* r12 = trap, r13 = paca */
1548 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1550 * POWER7 guest -> host partition switch code.
1551 * We don't have to lock against tlbies but we do
1552 * have to coordinate the hardware threads.
1554 /* Increment the threads-exiting-guest count in the 0xff00
1555 bits of vcore->entry_exit_count */
1556 ld r5,HSTATE_KVM_VCORE(r13)
1557 addi r6,r5,VCORE_ENTRY_EXIT
1562 isync /* order stwcx. vs. reading napping_threads */
1565 * At this point we have an interrupt that we have to pass
1566 * up to the kernel or qemu; we can't handle it in real mode.
1567 * Thus we have to do a partition switch, so we have to
1568 * collect the other threads, if we are the first thread
1569 * to take an interrupt. To do this, we set the HDEC to 0,
1570 * which causes an HDEC interrupt in all threads within 2ns
1571 * because the HDEC register is shared between all 4 threads.
1572 * However, we don't need to bother if this is an HDEC
1573 * interrupt, since the other threads will already be on their
1574 * way here in that case.
1576 cmpwi r3,0x100 /* Are we the first here? */
1578 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1584 * Send an IPI to any napping threads, since an HDEC interrupt
1585 * doesn't wake CPUs up from nap.
1587 lwz r3,VCORE_NAPPING_THREADS(r5)
1588 lbz r4,HSTATE_PTID(r13)
1591 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1593 /* Order entry/exit update vs. IPIs */
1595 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1599 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1602 stbcix r0,r7,r8 /* trigger the IPI */
1604 addi r6,r6,PACA_SIZE
1608 /* Secondary threads wait for primary to do partition switch */
1609 43: ld r5,HSTATE_KVM_VCORE(r13)
1610 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1611 lbz r3,HSTATE_PTID(r13)
1615 13: lbz r3,VCORE_IN_GUEST(r5)
1621 /* Primary thread waits for all the secondaries to exit guest */
1622 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1629 /* Primary thread switches back to host partition */
1630 ld r6,KVM_HOST_SDR1(r4)
1631 lwz r7,KVM_HOST_LPID(r4)
1632 li r8,LPID_RSVD /* switch to reserved LPID */
1635 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1640 /* DPDES is shared between threads */
1641 mfspr r7, SPRN_DPDES
1642 std r7, VCORE_DPDES(r5)
1643 /* clear DPDES so we don't get guest doorbells in the host */
1645 mtspr SPRN_DPDES, r8
1646 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1648 /* Subtract timebase offset from timebase */
1649 ld r8,VCORE_TB_OFFSET(r5)
1652 mftb r6 /* current guest timebase */
1654 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1655 mftb r7 /* check if lower 24 bits overflowed */
1660 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1664 17: ld r0, VCORE_PCR(r5)
1670 /* Signal secondary CPUs to continue */
1671 stb r0,VCORE_IN_GUEST(r5)
1672 lis r8,0x7fff /* MAX_INT@h */
1675 16: ld r8,KVM_HOST_LPCR(r4)
1681 * PPC970 guest -> host partition switch code.
1682 * We have to lock against concurrent tlbies, and
1683 * we have to flush the whole TLB.
1685 32: ld r5,HSTATE_KVM_VCORE(r13)
1686 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1688 /* Take the guest's tlbie_lock */
1689 #ifdef __BIG_ENDIAN__
1690 lwz r8,PACA_LOCK_TOKEN(r13)
1692 lwz r8,PACAPACAINDEX(r13)
1694 addi r3,r4,KVM_TLBIE_LOCK
1702 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1704 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1708 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1711 stw r0,0(r3) /* drop guest tlbie_lock */
1713 /* invalidate the whole TLB */
1722 /* take native_tlbie_lock */
1723 ld r3,toc_tlbie_lock@toc(2)
1731 ld r6,KVM_HOST_SDR1(r4)
1732 mtspr SPRN_SDR1,r6 /* switch to host page table */
1734 /* Set up host HID4 value */
1739 stw r0,0(r3) /* drop native_tlbie_lock */
1741 lis r8,0x7fff /* MAX_INT@h */
1744 /* Disable HDEC interrupts */
1747 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1757 /* load host SLB entries */
1758 33: ld r8,PACA_SLBSHADOWPTR(r13)
1760 .rept SLB_NUM_BOLTED
1761 ld r5,SLBSHADOW_SAVEAREA(r8)
1762 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1763 andis. r7,r5,SLB_ESID_V@h
1769 /* Unset guest mode */
1770 li r0, KVM_GUEST_MODE_NONE
1771 stb r0, HSTATE_IN_GUEST(r13)
1773 ld r0, 112+PPC_LR_STKOFF(r1)
1779 * Check whether an HDSI is an HPTE not found fault or something else.
1780 * If it is an HPTE not found fault that is due to the guest accessing
1781 * a page that they have mapped but which we have paged out, then
1782 * we continue on with the guest exit path. In all other cases,
1783 * reflect the HDSI to the guest as a DSI.
1787 mfspr r6, SPRN_HDSISR
1788 /* HPTE not found fault or protection fault? */
1789 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1790 beq 1f /* if not, send it to the guest */
1791 andi. r0, r11, MSR_DR /* data relocation enabled? */
1794 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1795 bne 1f /* if no SLB entry found */
1796 4: std r4, VCPU_FAULT_DAR(r9)
1797 stw r6, VCPU_FAULT_DSISR(r9)
1799 /* Search the hash table. */
1800 mr r3, r9 /* vcpu pointer */
1801 li r7, 1 /* data fault */
1802 bl .kvmppc_hpte_hv_fault
1803 ld r9, HSTATE_KVM_VCPU(r13)
1805 ld r11, VCPU_MSR(r9)
1806 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1807 cmpdi r3, 0 /* retry the instruction */
1809 cmpdi r3, -1 /* handle in kernel mode */
1811 cmpdi r3, -2 /* MMIO emulation; need instr word */
1814 /* Synthesize a DSI for the guest */
1815 ld r4, VCPU_FAULT_DAR(r9)
1817 1: mtspr SPRN_DAR, r4
1818 mtspr SPRN_DSISR, r6
1819 mtspr SPRN_SRR0, r10
1820 mtspr SPRN_SRR1, r11
1821 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1822 bl kvmppc_msr_interrupt
1823 fast_interrupt_c_return:
1824 6: ld r7, VCPU_CTR(r9)
1825 lwz r8, VCPU_XER(r9)
1831 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1832 ld r5, KVM_VRMA_SLB_V(r5)
1835 /* If this is for emulated MMIO, load the instruction word */
1836 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1838 /* Set guest mode to 'jump over instruction' so if lwz faults
1839 * we'll just continue at the next IP. */
1840 li r0, KVM_GUEST_MODE_SKIP
1841 stb r0, HSTATE_IN_GUEST(r13)
1843 /* Do the access with MSR:DR enabled */
1845 ori r4, r3, MSR_DR /* Enable paging for data */
1850 /* Store the result */
1851 stw r8, VCPU_LAST_INST(r9)
1853 /* Unset guest mode. */
1854 li r0, KVM_GUEST_MODE_HOST_HV
1855 stb r0, HSTATE_IN_GUEST(r13)
1859 * Similarly for an HISI, reflect it to the guest as an ISI unless
1860 * it is an HPTE not found fault for a page that we have paged out.
1863 andis. r0, r11, SRR1_ISI_NOPT@h
1865 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1868 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1869 bne 1f /* if no SLB entry found */
1871 /* Search the hash table. */
1872 mr r3, r9 /* vcpu pointer */
1875 li r7, 0 /* instruction fault */
1876 bl .kvmppc_hpte_hv_fault
1877 ld r9, HSTATE_KVM_VCPU(r13)
1879 ld r11, VCPU_MSR(r9)
1880 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1881 cmpdi r3, 0 /* retry the instruction */
1882 beq fast_interrupt_c_return
1883 cmpdi r3, -1 /* handle in kernel mode */
1886 /* Synthesize an ISI for the guest */
1888 1: mtspr SPRN_SRR0, r10
1889 mtspr SPRN_SRR1, r11
1890 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1891 bl kvmppc_msr_interrupt
1892 b fast_interrupt_c_return
1894 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1895 ld r5, KVM_VRMA_SLB_V(r6)
1899 * Try to handle an hcall in real mode.
1900 * Returns to the guest if we handle it, or continues on up to
1901 * the kernel if we can't (i.e. if we don't have a handler for
1902 * it, or if the handler returns H_TOO_HARD).
1904 .globl hcall_try_real_mode
1905 hcall_try_real_mode:
1906 ld r3,VCPU_GPR(R3)(r9)
1908 /* sc 1 from userspace - reflect to guest syscall */
1909 bne sc_1_fast_return
1911 cmpldi r3,hcall_real_table_end - hcall_real_table
1913 LOAD_REG_ADDR(r4, hcall_real_table)
1919 mr r3,r9 /* get vcpu pointer */
1920 ld r4,VCPU_GPR(R4)(r9)
1923 beq hcall_real_fallback
1924 ld r4,HSTATE_KVM_VCPU(r13)
1925 std r3,VCPU_GPR(R3)(r4)
1933 li r10, BOOK3S_INTERRUPT_SYSCALL
1934 bl kvmppc_msr_interrupt
1938 /* We've attempted a real mode hcall, but it's punted it back
1939 * to userspace. We need to restore some clobbered volatiles
1940 * before resuming the pass-it-to-qemu path */
1941 hcall_real_fallback:
1942 li r12,BOOK3S_INTERRUPT_SYSCALL
1943 ld r9, HSTATE_KVM_VCPU(r13)
1947 .globl hcall_real_table
1949 .long 0 /* 0 - unused */
1950 .long .kvmppc_h_remove - hcall_real_table
1951 .long .kvmppc_h_enter - hcall_real_table
1952 .long .kvmppc_h_read - hcall_real_table
1953 .long 0 /* 0x10 - H_CLEAR_MOD */
1954 .long 0 /* 0x14 - H_CLEAR_REF */
1955 .long .kvmppc_h_protect - hcall_real_table
1956 .long .kvmppc_h_get_tce - hcall_real_table
1957 .long .kvmppc_h_put_tce - hcall_real_table
1958 .long 0 /* 0x24 - H_SET_SPRG0 */
1959 .long .kvmppc_h_set_dabr - hcall_real_table
1974 #ifdef CONFIG_KVM_XICS
1975 .long .kvmppc_rm_h_eoi - hcall_real_table
1976 .long .kvmppc_rm_h_cppr - hcall_real_table
1977 .long .kvmppc_rm_h_ipi - hcall_real_table
1978 .long 0 /* 0x70 - H_IPOLL */
1979 .long .kvmppc_rm_h_xirr - hcall_real_table
1981 .long 0 /* 0x64 - H_EOI */
1982 .long 0 /* 0x68 - H_CPPR */
1983 .long 0 /* 0x6c - H_IPI */
1984 .long 0 /* 0x70 - H_IPOLL */
1985 .long 0 /* 0x74 - H_XIRR */
2013 .long .kvmppc_h_cede - hcall_real_table
2030 .long .kvmppc_h_bulk_remove - hcall_real_table
2034 .long .kvmppc_h_set_xdabr - hcall_real_table
2035 hcall_real_table_end:
2041 _GLOBAL(kvmppc_h_set_xdabr)
2042 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2044 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2047 6: li r3, H_PARAMETER
2050 _GLOBAL(kvmppc_h_set_dabr)
2051 li r5, DABRX_USER | DABRX_KERNEL
2055 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2056 std r4,VCPU_DABR(r3)
2057 stw r5, VCPU_DABRX(r3)
2058 mtspr SPRN_DABRX, r5
2059 /* Work around P7 bug where DABR can get corrupted on mtspr */
2060 1: mtspr SPRN_DABR,r4
2068 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2069 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2070 rlwimi r5, r4, 1, DAWRX_WT
2072 std r4, VCPU_DAWR(r3)
2073 std r5, VCPU_DAWRX(r3)
2075 mtspr SPRN_DAWRX, r5
2079 _GLOBAL(kvmppc_h_cede)
2081 std r11,VCPU_MSR(r3)
2083 stb r0,VCPU_CEDED(r3)
2084 sync /* order setting ceded vs. testing prodded */
2085 lbz r5,VCPU_PRODDED(r3)
2087 bne kvm_cede_prodded
2088 li r0,0 /* set trap to 0 to say hcall is handled */
2089 stw r0,VCPU_TRAP(r3)
2091 std r0,VCPU_GPR(R3)(r3)
2093 b kvm_cede_exit /* just send it up to host on 970 */
2094 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
2097 * Set our bit in the bitmask of napping threads unless all the
2098 * other threads are already napping, in which case we send this
2101 ld r5,HSTATE_KVM_VCORE(r13)
2102 lbz r6,HSTATE_PTID(r13)
2103 lwz r8,VCORE_ENTRY_EXIT(r5)
2107 addi r6,r5,VCORE_NAPPING_THREADS
2115 /* order napping_threads update vs testing entry_exit_count */
2118 stb r0,HSTATE_NAPPING(r13)
2119 lwz r7,VCORE_ENTRY_EXIT(r5)
2121 bge 33f /* another thread already exiting */
2124 * Although not specifically required by the architecture, POWER7
2125 * preserves the following registers in nap mode, even if an SMT mode
2126 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2127 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2129 /* Save non-volatile GPRs */
2130 std r14, VCPU_GPR(R14)(r3)
2131 std r15, VCPU_GPR(R15)(r3)
2132 std r16, VCPU_GPR(R16)(r3)
2133 std r17, VCPU_GPR(R17)(r3)
2134 std r18, VCPU_GPR(R18)(r3)
2135 std r19, VCPU_GPR(R19)(r3)
2136 std r20, VCPU_GPR(R20)(r3)
2137 std r21, VCPU_GPR(R21)(r3)
2138 std r22, VCPU_GPR(R22)(r3)
2139 std r23, VCPU_GPR(R23)(r3)
2140 std r24, VCPU_GPR(R24)(r3)
2141 std r25, VCPU_GPR(R25)(r3)
2142 std r26, VCPU_GPR(R26)(r3)
2143 std r27, VCPU_GPR(R27)(r3)
2144 std r28, VCPU_GPR(R28)(r3)
2145 std r29, VCPU_GPR(R29)(r3)
2146 std r30, VCPU_GPR(R30)(r3)
2147 std r31, VCPU_GPR(R31)(r3)
2153 * Take a nap until a decrementer or external or doobell interrupt
2154 * occurs, with PECE1, PECE0 and PECEDP set in LPCR. Also clear the
2155 * runlatch bit before napping.
2157 mfspr r2, SPRN_CTRLF
2159 mtspr SPRN_CTRLT, r2
2162 stb r0,HSTATE_HWTHREAD_REQ(r13)
2164 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2166 oris r5,r5,LPCR_PECEDP@h
2167 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2171 std r0, HSTATE_SCRATCH0(r13)
2173 ld r0, HSTATE_SCRATCH0(r13)
2185 /* get vcpu pointer */
2186 ld r4, HSTATE_KVM_VCPU(r13)
2188 /* Woken by external or decrementer interrupt */
2189 ld r1, HSTATE_HOST_R1(r13)
2191 /* load up FP state */
2195 ld r14, VCPU_GPR(R14)(r4)
2196 ld r15, VCPU_GPR(R15)(r4)
2197 ld r16, VCPU_GPR(R16)(r4)
2198 ld r17, VCPU_GPR(R17)(r4)
2199 ld r18, VCPU_GPR(R18)(r4)
2200 ld r19, VCPU_GPR(R19)(r4)
2201 ld r20, VCPU_GPR(R20)(r4)
2202 ld r21, VCPU_GPR(R21)(r4)
2203 ld r22, VCPU_GPR(R22)(r4)
2204 ld r23, VCPU_GPR(R23)(r4)
2205 ld r24, VCPU_GPR(R24)(r4)
2206 ld r25, VCPU_GPR(R25)(r4)
2207 ld r26, VCPU_GPR(R26)(r4)
2208 ld r27, VCPU_GPR(R27)(r4)
2209 ld r28, VCPU_GPR(R28)(r4)
2210 ld r29, VCPU_GPR(R29)(r4)
2211 ld r30, VCPU_GPR(R30)(r4)
2212 ld r31, VCPU_GPR(R31)(r4)
2214 /* Check the wake reason in SRR1 to see why we got here */
2215 bl kvmppc_check_wake_reason
2217 /* clear our bit in vcore->napping_threads */
2218 34: ld r5,HSTATE_KVM_VCORE(r13)
2219 lbz r7,HSTATE_PTID(r13)
2222 addi r6,r5,VCORE_NAPPING_THREADS
2228 stb r0,HSTATE_NAPPING(r13)
2230 /* See if the wake reason means we need to exit */
2231 stw r12, VCPU_TRAP(r4)
2236 /* see if any other thread is already exiting */
2237 lwz r0,VCORE_ENTRY_EXIT(r5)
2241 b kvmppc_cede_reentry /* if not go back to guest */
2243 /* cede when already previously prodded case */
2246 stb r0,VCPU_PRODDED(r3)
2247 sync /* order testing prodded vs. clearing ceded */
2248 stb r0,VCPU_CEDED(r3)
2252 /* we've ceded but we want to give control to the host */
2254 b hcall_real_fallback
2256 /* Try to handle a machine check in real mode */
2257 machine_check_realmode:
2258 mr r3, r9 /* get vcpu pointer */
2259 bl .kvmppc_realmode_machine_check
2261 cmpdi r3, 0 /* continue exiting from guest? */
2262 ld r9, HSTATE_KVM_VCPU(r13)
2263 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2265 /* If not, deliver a machine check. SRR0/1 are already set */
2266 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2267 ld r11, VCPU_MSR(r9)
2268 bl kvmppc_msr_interrupt
2269 b fast_interrupt_c_return
2272 * Check the reason we woke from nap, and take appropriate action.
2274 * 0 if nothing needs to be done
2275 * 1 if something happened that needs to be handled by the host
2276 * -1 if there was a guest wakeup (IPI)
2278 * Also sets r12 to the interrupt vector for any interrupt that needs
2279 * to be handled now by the host (0x500 for external interrupt), or zero.
2281 kvmppc_check_wake_reason:
2284 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2286 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2287 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2288 cmpwi r6, 8 /* was it an external interrupt? */
2289 li r12, BOOK3S_INTERRUPT_EXTERNAL
2290 beq kvmppc_read_intr /* if so, see what it was */
2293 cmpwi r6, 6 /* was it the decrementer? */
2296 cmpwi r6, 5 /* privileged doorbell? */
2298 cmpwi r6, 3 /* hypervisor doorbell? */
2300 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2301 li r3, 1 /* anything else, return 1 */
2304 /* hypervisor doorbell */
2305 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2310 * Determine what sort of external interrupt is pending (if any).
2312 * 0 if no interrupt is pending
2313 * 1 if an interrupt is pending that needs to be handled by the host
2314 * -1 if there was a guest wakeup IPI (which has now been cleared)
2317 /* see if a host IPI is pending */
2319 lbz r0, HSTATE_HOST_IPI(r13)
2323 /* Now read the interrupt from the ICP */
2324 ld r6, HSTATE_XICS_PHYS(r13)
2329 rlwinm. r3, r0, 0, 0xffffff
2331 beq 1f /* if nothing pending in the ICP */
2333 /* We found something in the ICP...
2335 * If it's not an IPI, stash it in the PACA and return to
2336 * the host, we don't (yet) handle directing real external
2337 * interrupts directly to the guest
2339 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2342 /* It's an IPI, clear the MFRR and EOI it */
2345 stbcix r3, r6, r8 /* clear the IPI */
2346 stwcix r0, r6, r7 /* EOI it */
2349 /* We need to re-check host IPI now in case it got set in the
2350 * meantime. If it's clear, we bounce the interrupt to the
2353 lbz r0, HSTATE_HOST_IPI(r13)
2357 /* OK, it's an IPI for us */
2361 42: /* It's not an IPI and it's for the host, stash it in the PACA
2362 * before exit, it will be picked up by the host ICP driver
2364 stw r0, HSTATE_SAVED_XIRR(r13)
2368 43: /* We raced with the host, we need to resend that IPI, bummer */
2370 stbcix r0, r6, r8 /* set the IPI */
2376 * Save away FP, VMX and VSX registers.
2378 * N.B. r30 and r31 are volatile across this function,
2379 * thus it is not callable from C.
2386 #ifdef CONFIG_ALTIVEC
2388 oris r8,r8,MSR_VEC@h
2389 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2393 oris r8,r8,MSR_VSX@h
2394 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2398 addi r3,r3,VCPU_FPRS
2400 #ifdef CONFIG_ALTIVEC
2402 addi r3,r31,VCPU_VRS
2404 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2406 mfspr r6,SPRN_VRSAVE
2407 stw r6,VCPU_VRSAVE(r31)
2412 * Load up FP, VMX and VSX registers
2414 * N.B. r30 and r31 are volatile across this function,
2415 * thus it is not callable from C.
2422 #ifdef CONFIG_ALTIVEC
2424 oris r8,r8,MSR_VEC@h
2425 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2429 oris r8,r8,MSR_VSX@h
2430 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2434 addi r3,r4,VCPU_FPRS
2436 #ifdef CONFIG_ALTIVEC
2438 addi r3,r31,VCPU_VRS
2440 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2442 lwz r7,VCPU_VRSAVE(r31)
2443 mtspr SPRN_VRSAVE,r7
2449 * We come here if we get any exception or interrupt while we are
2450 * executing host real mode code while in guest MMU context.
2451 * For now just spin, but we should do something better.
2453 kvmppc_bad_host_intr:
2457 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2458 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2459 * r11 has the guest MSR value (in/out)
2460 * r9 has a vcpu pointer (in)
2461 * r0 is used as a scratch register
2463 kvmppc_msr_interrupt:
2464 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2465 cmpwi r0, 2 /* Check if we are in transactional state.. */
2466 ld r11, VCPU_INTR_MSR(r9)
2468 /* ... if transactional, change to suspended */
2470 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2474 * This works around a hardware bug on POWER8E processors, where
2475 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2476 * performance monitor interrupt. Instead, when we need to have
2477 * an interrupt pending, we have to arrange for a counter to overflow.
2481 mtspr SPRN_MMCR2, r3
2482 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2483 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2484 mtspr SPRN_MMCR0, r3
projects / mirror_ubuntu-artful-kernel.git / blob