arch/powerpc/kvm/book3s_segment.S

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, write to the Free Software
  13  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  14  *
  15  * Copyright SUSE Linux Products GmbH 2010
  16  *
  17  * Authors: Alexander Graf <agraf@suse.de>
  18  */
  19
  20 /* Real mode helpers */
  21
  22 #if defined(CONFIG_PPC_BOOK3S_64)
  23
  24 #define GET_SHADOW_VCPU(reg)    \
  25         mr      reg, r13
  26
  27 #elif defined(CONFIG_PPC_BOOK3S_32)
  28
  29 #define GET_SHADOW_VCPU(reg)                            \
  30         tophys(reg, r2);                        \
  31         lwz     reg, (THREAD + THREAD_KVM_SVCPU)(reg);  \
  32         tophys(reg, reg)
  33
  34 #endif
  35
  36 /* Disable for nested KVM */
  37 #define USE_QUICK_LAST_INST
  38
  39
  40 /* Get helper functions for subarch specific functionality */
  41
  42 #if defined(CONFIG_PPC_BOOK3S_64)
  43 #include "book3s_64_slb.S"
  44 #elif defined(CONFIG_PPC_BOOK3S_32)
  45 #include "book3s_32_sr.S"
  46 #endif
  47
  48 /******************************************************************************
  49  *                                                                            *
  50  *                               Entry code                                   *
  51  *                                                                            *
  52  *****************************************************************************/
  53
  54 .global kvmppc_handler_trampoline_enter
  55 kvmppc_handler_trampoline_enter:
  56
  57         /* Required state:
  58          *
  59          * MSR = ~IR|DR
  60          * R1 = host R1
  61          * R2 = host R2
  62          * R4 = guest shadow MSR
  63          * R5 = normal host MSR
  64          * R6 = current host MSR (EE, IR, DR off)
  65          * LR = highmem guest exit code
  66          * all other volatile GPRS = free
  67          * SVCPU[CR] = guest CR
  68          * SVCPU[XER] = guest XER
  69          * SVCPU[CTR] = guest CTR
  70          * SVCPU[LR] = guest LR
  71          */
  72
  73         /* r3 = shadow vcpu */
  74         GET_SHADOW_VCPU(r3)
  75
  76         /* Save guest exit handler address and MSR */
  77         mflr    r0
  78         PPC_STL r0, HSTATE_VMHANDLER(r3)
  79         PPC_STL r5, HSTATE_HOST_MSR(r3)
  80
  81         /* Save R1/R2 in the PACA (64-bit) or shadow_vcpu (32-bit) */
  82         PPC_STL r1, HSTATE_HOST_R1(r3)
  83         PPC_STL r2, HSTATE_HOST_R2(r3)
  84
  85         /* Activate guest mode, so faults get handled by KVM */
  86         li      r11, KVM_GUEST_MODE_GUEST
  87         stb     r11, HSTATE_IN_GUEST(r3)
  88
  89         /* Switch to guest segment. This is subarch specific. */
  90         LOAD_GUEST_SEGMENTS
  91
  92 #ifdef CONFIG_PPC_BOOK3S_64
  93 BEGIN_FTR_SECTION
  94         /* Save host FSCR */
  95         mfspr   r8, SPRN_FSCR
  96         std     r8, HSTATE_HOST_FSCR(r13)
  97         /* Set FSCR during guest execution */
  98         ld      r9, SVCPU_SHADOW_FSCR(r13)
  99         mtspr   SPRN_FSCR, r9
 100 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 101
 102         /* Some guests may need to have dcbz set to 32 byte length.
 103          *
 104          * Usually we ensure that by patching the guest's instructions
 105          * to trap on dcbz and emulate it in the hypervisor.
 106          *
 107          * If we can, we should tell the CPU to use 32 byte dcbz though,
 108          * because that's a lot faster.
 109          */
 110         lbz     r0, HSTATE_RESTORE_HID5(r3)
 111         cmpwi   r0, 0
 112         beq     no_dcbz32_on
 113
 114         mfspr   r0,SPRN_HID5
 115         ori     r0, r0, 0x80            /* XXX HID5_dcbz32 = 0x80 */
 116         mtspr   SPRN_HID5,r0
 117 no_dcbz32_on:
 118
 119 #endif /* CONFIG_PPC_BOOK3S_64 */
 120
 121         /* Enter guest */
 122
 123         PPC_LL  r8, SVCPU_CTR(r3)
 124         PPC_LL  r9, SVCPU_LR(r3)
 125         lwz     r10, SVCPU_CR(r3)
 126         PPC_LL  r11, SVCPU_XER(r3)
 127
 128         mtctr   r8
 129         mtlr    r9
 130         mtcr    r10
 131         mtxer   r11
 132
 133         /* Move SRR0 and SRR1 into the respective regs */
 134         PPC_LL  r9, SVCPU_PC(r3)
 135         /* First clear RI in our current MSR value */
 136         li      r0, MSR_RI
 137         andc    r6, r6, r0
 138
 139         PPC_LL  r0, SVCPU_R0(r3)
 140         PPC_LL  r1, SVCPU_R1(r3)
 141         PPC_LL  r2, SVCPU_R2(r3)
 142         PPC_LL  r5, SVCPU_R5(r3)
 143         PPC_LL  r7, SVCPU_R7(r3)
 144         PPC_LL  r8, SVCPU_R8(r3)
 145         PPC_LL  r10, SVCPU_R10(r3)
 146         PPC_LL  r11, SVCPU_R11(r3)
 147         PPC_LL  r12, SVCPU_R12(r3)
 148         PPC_LL  r13, SVCPU_R13(r3)
 149
 150         MTMSR_EERI(r6)
 151         mtsrr0  r9
 152         mtsrr1  r4
 153
 154         PPC_LL  r4, SVCPU_R4(r3)
 155         PPC_LL  r6, SVCPU_R6(r3)
 156         PPC_LL  r9, SVCPU_R9(r3)
 157         PPC_LL  r3, (SVCPU_R3)(r3)
 158
 159         RFI
 160 kvmppc_handler_trampoline_enter_end:
 161
 162
 163
 164 /******************************************************************************
 165  *                                                                            *
 166  *                               Exit code                                    *
 167  *                                                                            *
 168  *****************************************************************************/
 169
 170 .global kvmppc_handler_trampoline_exit
 171 kvmppc_handler_trampoline_exit:
 172
 173 .global kvmppc_interrupt_pr
 174 kvmppc_interrupt_pr:
 175
 176         /* Register usage at this point:
 177          *
 178          * SPRG_SCRATCH0  = guest R13
 179          * R12            = exit handler id
 180          * R13            = shadow vcpu (32-bit) or PACA (64-bit)
 181          * HSTATE.SCRATCH0 = guest R12
 182          * HSTATE.SCRATCH1 = guest CR
 183          *
 184          */
 185
 186         /* Save registers */
 187
 188         PPC_STL r0, SVCPU_R0(r13)
 189         PPC_STL r1, SVCPU_R1(r13)
 190         PPC_STL r2, SVCPU_R2(r13)
 191         PPC_STL r3, SVCPU_R3(r13)
 192         PPC_STL r4, SVCPU_R4(r13)
 193         PPC_STL r5, SVCPU_R5(r13)
 194         PPC_STL r6, SVCPU_R6(r13)
 195         PPC_STL r7, SVCPU_R7(r13)
 196         PPC_STL r8, SVCPU_R8(r13)
 197         PPC_STL r9, SVCPU_R9(r13)
 198         PPC_STL r10, SVCPU_R10(r13)
 199         PPC_STL r11, SVCPU_R11(r13)
 200
 201         /* Restore R1/R2 so we can handle faults */
 202         PPC_LL  r1, HSTATE_HOST_R1(r13)
 203         PPC_LL  r2, HSTATE_HOST_R2(r13)
 204
 205         /* Save guest PC and MSR */
 206 #ifdef CONFIG_PPC64
 207 BEGIN_FTR_SECTION
 208         andi.   r0, r12, 0x2
 209         cmpwi   cr1, r0, 0
 210         beq     1f
 211         mfspr   r3,SPRN_HSRR0
 212         mfspr   r4,SPRN_HSRR1
 213         andi.   r12,r12,0x3ffd
 214         b       2f
 215 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 216 #endif
 217 1:      mfsrr0  r3
 218         mfsrr1  r4
 219 2:
 220         PPC_STL r3, SVCPU_PC(r13)
 221         PPC_STL r4, SVCPU_SHADOW_SRR1(r13)
 222
 223         /* Get scratch'ed off registers */
 224         GET_SCRATCH0(r9)
 225         PPC_LL  r8, HSTATE_SCRATCH0(r13)
 226         lwz     r7, HSTATE_SCRATCH1(r13)
 227
 228         PPC_STL r9, SVCPU_R13(r13)
 229         PPC_STL r8, SVCPU_R12(r13)
 230         stw     r7, SVCPU_CR(r13)
 231
 232         /* Save more register state  */
 233
 234         mfxer   r5
 235         mfdar   r6
 236         mfdsisr r7
 237         mfctr   r8
 238         mflr    r9
 239
 240         PPC_STL r5, SVCPU_XER(r13)
 241         PPC_STL r6, SVCPU_FAULT_DAR(r13)
 242         stw     r7, SVCPU_FAULT_DSISR(r13)
 243         PPC_STL r8, SVCPU_CTR(r13)
 244         PPC_STL r9, SVCPU_LR(r13)
 245
 246         /*
 247          * In order for us to easily get the last instruction,
 248          * we got the #vmexit at, we exploit the fact that the
 249          * virtual layout is still the same here, so we can just
 250          * ld from the guest's PC address
 251          */
 252
 253         /* We only load the last instruction when it's safe */
 254         cmpwi   r12, BOOK3S_INTERRUPT_DATA_STORAGE
 255         beq     ld_last_inst
 256         cmpwi   r12, BOOK3S_INTERRUPT_PROGRAM
 257         beq     ld_last_inst
 258         cmpwi   r12, BOOK3S_INTERRUPT_SYSCALL
 259         beq     ld_last_prev_inst
 260         cmpwi   r12, BOOK3S_INTERRUPT_ALIGNMENT
 261         beq-    ld_last_inst
 262 #ifdef CONFIG_PPC64
 263 BEGIN_FTR_SECTION
 264         cmpwi   r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
 265         beq-    ld_last_inst
 266 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 267 BEGIN_FTR_SECTION
 268         cmpwi   r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
 269         beq-    ld_last_inst
 270 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 271 #endif
 272
 273         b       no_ld_last_inst
 274
 275 ld_last_prev_inst:
 276         addi    r3, r3, -4
 277
 278 ld_last_inst:
 279         /* Save off the guest instruction we're at */
 280
 281         /* In case lwz faults */
 282         li      r0, KVM_INST_FETCH_FAILED
 283
 284 #ifdef USE_QUICK_LAST_INST
 285
 286         /* Set guest mode to 'jump over instruction' so if lwz faults
 287          * we'll just continue at the next IP. */
 288         li      r9, KVM_GUEST_MODE_SKIP
 289         stb     r9, HSTATE_IN_GUEST(r13)
 290
 291         /*    1) enable paging for data */
 292         mfmsr   r9
 293         ori     r11, r9, MSR_DR                 /* Enable paging for data */
 294         mtmsr   r11
 295         sync
 296         /*    2) fetch the instruction */
 297         lwz     r0, 0(r3)
 298         /*    3) disable paging again */
 299         mtmsr   r9
 300         sync
 301
 302 #endif
 303         stw     r0, SVCPU_LAST_INST(r13)
 304
 305 no_ld_last_inst:
 306
 307         /* Unset guest mode */
 308         li      r9, KVM_GUEST_MODE_NONE
 309         stb     r9, HSTATE_IN_GUEST(r13)
 310
 311         /* Switch back to host MMU */
 312         LOAD_HOST_SEGMENTS
 313
 314 #ifdef CONFIG_PPC_BOOK3S_64
 315
 316         lbz     r5, HSTATE_RESTORE_HID5(r13)
 317         cmpwi   r5, 0
 318         beq     no_dcbz32_off
 319
 320         li      r4, 0
 321         mfspr   r5,SPRN_HID5
 322         rldimi  r5,r4,6,56
 323         mtspr   SPRN_HID5,r5
 324
 325 no_dcbz32_off:
 326
 327 BEGIN_FTR_SECTION
 328         /* Save guest FSCR on a FAC_UNAVAIL interrupt */
 329         cmpwi   r12, BOOK3S_INTERRUPT_FAC_UNAVAIL
 330         bne+    no_fscr_save
 331         mfspr   r7, SPRN_FSCR
 332         std     r7, SVCPU_SHADOW_FSCR(r13)
 333 no_fscr_save:
 334         /* Restore host FSCR */
 335         ld      r8, HSTATE_HOST_FSCR(r13)
 336         mtspr   SPRN_FSCR, r8
 337 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 338
 339 #endif /* CONFIG_PPC_BOOK3S_64 */
 340
 341         /*
 342          * For some interrupts, we need to call the real Linux
 343          * handler, so it can do work for us. This has to happen
 344          * as if the interrupt arrived from the kernel though,
 345          * so let's fake it here where most state is restored.
 346          *
 347          * Having set up SRR0/1 with the address where we want
 348          * to continue with relocation on (potentially in module
 349          * space), we either just go straight there with rfi[d],
 350          * or we jump to an interrupt handler if there is an
 351          * interrupt to be handled first.  In the latter case,
 352          * the rfi[d] at the end of the interrupt handler will
 353          * get us back to where we want to continue.
 354          */
 355
 356         /* Register usage at this point:
 357          *
 358          * R1       = host R1
 359          * R2       = host R2
 360          * R10      = raw exit handler id
 361          * R12      = exit handler id
 362          * R13      = shadow vcpu (32-bit) or PACA (64-bit)
 363          * SVCPU.*  = guest *
 364          *
 365          */
 366
 367         PPC_LL  r6, HSTATE_HOST_MSR(r13)
 368         PPC_LL  r8, HSTATE_VMHANDLER(r13)
 369
 370 #ifdef CONFIG_PPC64
 371 BEGIN_FTR_SECTION
 372         beq     cr1, 1f
 373         mtspr   SPRN_HSRR1, r6
 374         mtspr   SPRN_HSRR0, r8
 375 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 376 #endif
 377 1:      /* Restore host msr -> SRR1 */
 378         mtsrr1  r6
 379         /* Load highmem handler address */
 380         mtsrr0  r8
 381
 382         /* RFI into the highmem handler, or jump to interrupt handler */
 383         cmpwi   r12, BOOK3S_INTERRUPT_EXTERNAL
 384         beqa    BOOK3S_INTERRUPT_EXTERNAL
 385         cmpwi   r12, BOOK3S_INTERRUPT_DECREMENTER
 386         beqa    BOOK3S_INTERRUPT_DECREMENTER
 387         cmpwi   r12, BOOK3S_INTERRUPT_PERFMON
 388         beqa    BOOK3S_INTERRUPT_PERFMON
 389         cmpwi   r12, BOOK3S_INTERRUPT_DOORBELL
 390         beqa    BOOK3S_INTERRUPT_DOORBELL
 391
 392         RFI
 393 kvmppc_handler_trampoline_exit_end: