arch/powerpc/mm/44x_mmu.c

   1 /*
   2  * Modifications by Matt Porter (mporter@mvista.com) to support
   3  * PPC44x Book E processors.
   4  *
   5  * This file contains the routines for initializing the MMU
   6  * on the 4xx series of chips.
   7  *  -- paulus
   8  *
   9  *  Derived from arch/ppc/mm/init.c:
  10  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  11  *
  12  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  13  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  14  *    Copyright (C) 1996 Paul Mackerras
  15  *
  16  *  Derived from "arch/i386/mm/init.c"
  17  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  *
  24  */
  25
  26 #include <linux/init.h>
  27 #include <asm/mmu.h>
  28 #include <asm/system.h>
  29 #include <asm/page.h>
  30 #include <asm/cacheflush.h>
  31
  32 #include "mmu_decl.h"
  33
  34 /* Used by the 44x TLB replacement exception handler.
  35  * Just needed it declared someplace.
  36  */
  37 unsigned int tlb_44x_index; /* = 0 */
  38 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
  39 int icache_44x_need_flush;
  40
  41 static void __init ppc44x_update_tlb_hwater(void)
  42 {
  43         extern unsigned int tlb_44x_patch_hwater_D[];
  44         extern unsigned int tlb_44x_patch_hwater_I[];
  45
  46         /* The TLB miss handlers hard codes the watermark in a cmpli
  47          * instruction to improve performances rather than loading it
  48          * from the global variable. Thus, we patch the instructions
  49          * in the 2 TLB miss handlers when updating the value
  50          */
  51         tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) |
  52                 tlb_44x_hwater;
  53         flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0],
  54                            (unsigned long)&tlb_44x_patch_hwater_D[1]);
  55         tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) |
  56                 tlb_44x_hwater;
  57         flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0],
  58                            (unsigned long)&tlb_44x_patch_hwater_I[1]);
  59 }
  60
  61 /*
  62  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
  63  */
  64 static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
  65 {
  66         unsigned int entry = tlb_44x_hwater--;
  67
  68         ppc44x_update_tlb_hwater();
  69
  70         __asm__ __volatile__(
  71                 "tlbwe  %2,%3,%4\n"
  72                 "tlbwe  %1,%3,%5\n"
  73                 "tlbwe  %0,%3,%6\n"
  74         :
  75         : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
  76           "r" (phys),
  77           "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
  78           "r" (entry),
  79           "i" (PPC44x_TLB_PAGEID),
  80           "i" (PPC44x_TLB_XLAT),
  81           "i" (PPC44x_TLB_ATTRIB));
  82 }
  83
  84 void __init MMU_init_hw(void)
  85 {
  86         ppc44x_update_tlb_hwater();
  87
  88         flush_instruction_cache();
  89 }
  90
  91 unsigned long __init mmu_mapin_ram(void)
  92 {
  93         unsigned long addr;
  94
  95         /* Pin in enough TLBs to cover any lowmem not covered by the
  96          * initial 256M mapping established in head_44x.S */
  97         for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
  98              addr += PPC_PIN_SIZE)
  99                 ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
 100
 101         return total_lowmem;
 102 }