arch/powerpc/mm/8xx_mmu.c

   1 /*
   2  * This file contains the routines for initializing the MMU
   3  * on the 8xx series of chips.
   4  *  -- christophe
   5  *
   6  *  Derived from arch/powerpc/mm/40x_mmu.c:
   7  *
   8  *  This program is free software; you can redistribute it and/or
   9  *  modify it under the terms of the GNU General Public License
  10  *  as published by the Free Software Foundation; either version
  11  *  2 of the License, or (at your option) any later version.
  12  *
  13  */
  14
  15 #include <linux/memblock.h>
  16 #include <asm/fixmap.h>
  17 #include <asm/code-patching.h>
  18
  19 #include "mmu_decl.h"
  20
  21 #define IMMR_SIZE (FIX_IMMR_SIZE << PAGE_SHIFT)
  22
  23 extern int __map_without_ltlbs;
  24
  25 static unsigned long block_mapped_ram;
  26
  27 /*
  28  * Return PA for this VA if it is in an area mapped with LTLBs.
  29  * Otherwise, returns 0
  30  */
  31 phys_addr_t v_block_mapped(unsigned long va)
  32 {
  33         unsigned long p = PHYS_IMMR_BASE;
  34
  35         if (__map_without_ltlbs)
  36                 return 0;
  37         if (va >= VIRT_IMMR_BASE && va < VIRT_IMMR_BASE + IMMR_SIZE)
  38                 return p + va - VIRT_IMMR_BASE;
  39         if (va >= PAGE_OFFSET && va < PAGE_OFFSET + block_mapped_ram)
  40                 return __pa(va);
  41         return 0;
  42 }
  43
  44 /*
  45  * Return VA for a given PA mapped with LTLBs or 0 if not mapped
  46  */
  47 unsigned long p_block_mapped(phys_addr_t pa)
  48 {
  49         unsigned long p = PHYS_IMMR_BASE;
  50
  51         if (__map_without_ltlbs)
  52                 return 0;
  53         if (pa >= p && pa < p + IMMR_SIZE)
  54                 return VIRT_IMMR_BASE + pa - p;
  55         if (pa < block_mapped_ram)
  56                 return (unsigned long)__va(pa);
  57         return 0;
  58 }
  59
  60 #define LARGE_PAGE_SIZE_8M      (1<<23)
  61
  62 /*
  63  * MMU_init_hw does the chip-specific initialization of the MMU hardware.
  64  */
  65 void __init MMU_init_hw(void)
  66 {
  67         /* PIN up to the 3 first 8Mb after IMMR in DTLB table */
  68 #ifdef CONFIG_PIN_TLB
  69         unsigned long ctr = mfspr(SPRN_MD_CTR) & 0xfe000000;
  70         unsigned long flags = 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY;
  71 #ifdef CONFIG_PIN_TLB_IMMR
  72         int i = 29;
  73 #else
  74         int i = 28;
  75 #endif
  76         unsigned long addr = 0;
  77         unsigned long mem = total_lowmem;
  78
  79         for (; i < 32 && mem >= LARGE_PAGE_SIZE_8M; i++) {
  80                 mtspr(SPRN_MD_CTR, ctr | (i << 8));
  81                 mtspr(SPRN_MD_EPN, (unsigned long)__va(addr) | MD_EVALID);
  82                 mtspr(SPRN_MD_TWC, MD_PS8MEG | MD_SVALID);
  83                 mtspr(SPRN_MD_RPN, addr | flags | _PAGE_PRESENT);
  84                 addr += LARGE_PAGE_SIZE_8M;
  85                 mem -= LARGE_PAGE_SIZE_8M;
  86         }
  87 #endif
  88 }
  89
  90 static void mmu_mapin_immr(void)
  91 {
  92         unsigned long p = PHYS_IMMR_BASE;
  93         unsigned long v = VIRT_IMMR_BASE;
  94         unsigned long f = pgprot_val(PAGE_KERNEL_NCG);
  95         int offset;
  96
  97         for (offset = 0; offset < IMMR_SIZE; offset += PAGE_SIZE)
  98                 map_kernel_page(v + offset, p + offset, f);
  99 }
 100
 101 /* Address of instructions to patch */
 102 #ifndef CONFIG_PIN_TLB_IMMR
 103 extern unsigned int DTLBMiss_jmp;
 104 #endif
 105 extern unsigned int DTLBMiss_cmp, FixupDAR_cmp;
 106
 107 void mmu_patch_cmp_limit(unsigned int *addr, unsigned long mapped)
 108 {
 109         unsigned int instr = *addr;
 110
 111         instr &= 0xffff0000;
 112         instr |= (unsigned long)__va(mapped) >> 16;
 113         patch_instruction(addr, instr);
 114 }
 115
 116 unsigned long __init mmu_mapin_ram(unsigned long top)
 117 {
 118         unsigned long mapped;
 119
 120         if (__map_without_ltlbs) {
 121                 mapped = 0;
 122                 mmu_mapin_immr();
 123 #ifndef CONFIG_PIN_TLB_IMMR
 124                 patch_instruction(&DTLBMiss_jmp, PPC_INST_NOP);
 125 #endif
 126         } else {
 127                 mapped = top & ~(LARGE_PAGE_SIZE_8M - 1);
 128         }
 129
 130         mmu_patch_cmp_limit(&DTLBMiss_cmp, mapped);
 131         mmu_patch_cmp_limit(&FixupDAR_cmp, mapped);
 132
 133         /* If the size of RAM is not an exact power of two, we may not
 134          * have covered RAM in its entirety with 8 MiB
 135          * pages. Consequently, restrict the top end of RAM currently
 136          * allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
 137          * coverage with normal-sized pages (or other reasons) do not
 138          * attempt to allocate outside the allowed range.
 139          */
 140         if (mapped)
 141                 memblock_set_current_limit(mapped);
 142
 143         block_mapped_ram = mapped;
 144
 145         return mapped;
 146 }
 147
 148 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 149                                 phys_addr_t first_memblock_size)
 150 {
 151         /* We don't currently support the first MEMBLOCK not mapping 0
 152          * physical on those processors
 153          */
 154         BUG_ON(first_memblock_base != 0);
 155
 156         /* 8xx can only access 24MB at the moment */
 157         memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000));
 158 }
 159
 160 /*
 161  * Set up to use a given MMU context.
 162  * id is context number, pgd is PGD pointer.
 163  *
 164  * We place the physical address of the new task page directory loaded
 165  * into the MMU base register, and set the ASID compare register with
 166  * the new "context."
 167  */
 168 void set_context(unsigned long id, pgd_t *pgd)
 169 {
 170         s16 offset = (s16)(__pa(swapper_pg_dir));
 171
 172 #ifdef CONFIG_BDI_SWITCH
 173         pgd_t   **ptr = *(pgd_t ***)(KERNELBASE + 0xf0);
 174
 175         /* Context switch the PTE pointer for the Abatron BDI2000.
 176          * The PGDIR is passed as second argument.
 177          */
 178         *(ptr + 1) = pgd;
 179 #endif
 180
 181         /* Register M_TW will contain base address of level 1 table minus the
 182          * lower part of the kernel PGDIR base address, so that all accesses to
 183          * level 1 table are done relative to lower part of kernel PGDIR base
 184          * address.
 185          */
 186         mtspr(SPRN_M_TW, __pa(pgd) - offset);
 187
 188         /* Update context */
 189         mtspr(SPRN_M_CASID, id);
 190         /* sync */
 191         mb();
 192 }
 193
 194 void flush_instruction_cache(void)
 195 {
 196         isync();
 197         mtspr(SPRN_IC_CST, IDC_INVALL);
 198         isync();
 199 }