2 * native hashtable management.
4 * SMP scalability work:
5 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
18 #include <linux/threads.h>
19 #include <linux/smp.h>
21 #include <asm/machdep.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
25 #include <asm/tlbflush.h>
27 #include <asm/cputable.h>
29 #include <asm/kexec.h>
30 #include <asm/ppc-opcode.h>
35 #define DBG_LOW(fmt...) udbg_printf(fmt)
37 #define DBG_LOW(fmt...)
41 #define HPTE_LOCK_BIT 3
43 #define HPTE_LOCK_BIT (56+3)
46 DEFINE_RAW_SPINLOCK(native_tlbie_lock
);
48 static inline void __tlbie(unsigned long vpn
, int psize
, int apsize
, int ssize
)
55 * We need 14 to 65 bits of va for a tlibe of 4K page
56 * With vpn we ignore the lower VPN_SHIFT bits already.
57 * And top two bits are already ignored because we can
58 * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
61 va
= vpn
<< VPN_SHIFT
;
63 * clear top 16 bits of 64bit va, non SLS segment
64 * Older versions of the architecture (2.02 and earler) require the
65 * masking of the top 16 bits.
67 va
&= ~(0xffffULL
<< 48);
71 /* clear out bits after (52) [0....52.....63] */
72 va
&= ~((1ul << (64 - 52)) - 1);
74 sllp
= ((mmu_psize_defs
[apsize
].sllp
& SLB_VSID_L
) >> 6) |
75 ((mmu_psize_defs
[apsize
].sllp
& SLB_VSID_LP
) >> 4);
77 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
78 : : "r" (va
), "r"(0), "i" (CPU_FTR_ARCH_206
)
82 /* We need 14 to 14 + i bits of va */
83 penc
= mmu_psize_defs
[psize
].penc
[apsize
];
84 va
&= ~((1ul << mmu_psize_defs
[apsize
].shift
) - 1);
89 * We don't need all the bits, but rest of the bits
90 * must be ignored by the processor.
91 * vpn cover upto 65 bits of va. (0...65) and we need
94 va
|= (vpn
& 0xfe); /* AVAL */
96 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
97 : : "r" (va
), "r"(0), "i" (CPU_FTR_ARCH_206
)
103 static inline void __tlbiel(unsigned long vpn
, int psize
, int apsize
, int ssize
)
109 /* VPN_SHIFT can be atmost 12 */
110 va
= vpn
<< VPN_SHIFT
;
112 * clear top 16 bits of 64 bit va, non SLS segment
113 * Older versions of the architecture (2.02 and earler) require the
114 * masking of the top 16 bits.
116 va
&= ~(0xffffULL
<< 48);
120 /* clear out bits after(52) [0....52.....63] */
121 va
&= ~((1ul << (64 - 52)) - 1);
123 sllp
= ((mmu_psize_defs
[apsize
].sllp
& SLB_VSID_L
) >> 6) |
124 ((mmu_psize_defs
[apsize
].sllp
& SLB_VSID_LP
) >> 4);
126 asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
127 : : "r"(va
) : "memory");
130 /* We need 14 to 14 + i bits of va */
131 penc
= mmu_psize_defs
[psize
].penc
[apsize
];
132 va
&= ~((1ul << mmu_psize_defs
[apsize
].shift
) - 1);
137 * We don't need all the bits, but rest of the bits
138 * must be ignored by the processor.
139 * vpn cover upto 65 bits of va. (0...65) and we need
144 asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
145 : : "r"(va
) : "memory");
151 static inline void tlbie(unsigned long vpn
, int psize
, int apsize
,
152 int ssize
, int local
)
154 unsigned int use_local
;
155 int lock_tlbie
= !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE
);
157 use_local
= local
&& mmu_has_feature(MMU_FTR_TLBIEL
) && !cxl_ctx_in_use();
160 use_local
= mmu_psize_defs
[psize
].tlbiel
;
161 if (lock_tlbie
&& !use_local
)
162 raw_spin_lock(&native_tlbie_lock
);
163 asm volatile("ptesync": : :"memory");
165 __tlbiel(vpn
, psize
, apsize
, ssize
);
166 asm volatile("ptesync": : :"memory");
168 __tlbie(vpn
, psize
, apsize
, ssize
);
169 asm volatile("eieio; tlbsync; ptesync": : :"memory");
171 if (lock_tlbie
&& !use_local
)
172 raw_spin_unlock(&native_tlbie_lock
);
175 static inline void native_lock_hpte(struct hash_pte
*hptep
)
177 unsigned long *word
= (unsigned long *)&hptep
->v
;
180 if (!test_and_set_bit_lock(HPTE_LOCK_BIT
, word
))
182 while(test_bit(HPTE_LOCK_BIT
, word
))
187 static inline void native_unlock_hpte(struct hash_pte
*hptep
)
189 unsigned long *word
= (unsigned long *)&hptep
->v
;
191 clear_bit_unlock(HPTE_LOCK_BIT
, word
);
194 static long native_hpte_insert(unsigned long hpte_group
, unsigned long vpn
,
195 unsigned long pa
, unsigned long rflags
,
196 unsigned long vflags
, int psize
, int apsize
, int ssize
)
198 struct hash_pte
*hptep
= htab_address
+ hpte_group
;
199 unsigned long hpte_v
, hpte_r
;
202 if (!(vflags
& HPTE_V_BOLTED
)) {
203 DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
204 " rflags=%lx, vflags=%lx, psize=%d)\n",
205 hpte_group
, vpn
, pa
, rflags
, vflags
, psize
);
208 for (i
= 0; i
< HPTES_PER_GROUP
; i
++) {
209 if (! (be64_to_cpu(hptep
->v
) & HPTE_V_VALID
)) {
210 /* retry with lock held */
211 native_lock_hpte(hptep
);
212 if (! (be64_to_cpu(hptep
->v
) & HPTE_V_VALID
))
214 native_unlock_hpte(hptep
);
220 if (i
== HPTES_PER_GROUP
)
223 hpte_v
= hpte_encode_v(vpn
, psize
, apsize
, ssize
) | vflags
| HPTE_V_VALID
;
224 hpte_r
= hpte_encode_r(pa
, psize
, apsize
) | rflags
;
226 if (!(vflags
& HPTE_V_BOLTED
)) {
227 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
231 hptep
->r
= cpu_to_be64(hpte_r
);
232 /* Guarantee the second dword is visible before the valid bit */
235 * Now set the first dword including the valid bit
236 * NOTE: this also unlocks the hpte
238 hptep
->v
= cpu_to_be64(hpte_v
);
240 __asm__
__volatile__ ("ptesync" : : : "memory");
242 return i
| (!!(vflags
& HPTE_V_SECONDARY
) << 3);
245 static long native_hpte_remove(unsigned long hpte_group
)
247 struct hash_pte
*hptep
;
250 unsigned long hpte_v
;
252 DBG_LOW(" remove(group=%lx)\n", hpte_group
);
254 /* pick a random entry to start at */
255 slot_offset
= mftb() & 0x7;
257 for (i
= 0; i
< HPTES_PER_GROUP
; i
++) {
258 hptep
= htab_address
+ hpte_group
+ slot_offset
;
259 hpte_v
= be64_to_cpu(hptep
->v
);
261 if ((hpte_v
& HPTE_V_VALID
) && !(hpte_v
& HPTE_V_BOLTED
)) {
262 /* retry with lock held */
263 native_lock_hpte(hptep
);
264 hpte_v
= be64_to_cpu(hptep
->v
);
265 if ((hpte_v
& HPTE_V_VALID
)
266 && !(hpte_v
& HPTE_V_BOLTED
))
268 native_unlock_hpte(hptep
);
275 if (i
== HPTES_PER_GROUP
)
278 /* Invalidate the hpte. NOTE: this also unlocks it */
284 static long native_hpte_updatepp(unsigned long slot
, unsigned long newpp
,
285 unsigned long vpn
, int bpsize
,
286 int apsize
, int ssize
, int local
)
288 struct hash_pte
*hptep
= htab_address
+ slot
;
289 unsigned long hpte_v
, want_v
;
292 want_v
= hpte_encode_avpn(vpn
, bpsize
, ssize
);
294 DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
295 vpn
, want_v
& HPTE_V_AVPN
, slot
, newpp
);
297 hpte_v
= be64_to_cpu(hptep
->v
);
299 * We need to invalidate the TLB always because hpte_remove doesn't do
300 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
301 * random entry from it. When we do that we don't invalidate the TLB
302 * (hpte_remove) because we assume the old translation is still
303 * technically "valid".
305 if (!HPTE_V_COMPARE(hpte_v
, want_v
) || !(hpte_v
& HPTE_V_VALID
)) {
306 DBG_LOW(" -> miss\n");
309 native_lock_hpte(hptep
);
310 /* recheck with locks held */
311 hpte_v
= be64_to_cpu(hptep
->v
);
312 if (unlikely(!HPTE_V_COMPARE(hpte_v
, want_v
) ||
313 !(hpte_v
& HPTE_V_VALID
))) {
316 DBG_LOW(" -> hit\n");
317 /* Update the HPTE */
318 hptep
->r
= cpu_to_be64((be64_to_cpu(hptep
->r
) &
319 ~(HPTE_R_PP
| HPTE_R_N
)) |
320 (newpp
& (HPTE_R_PP
| HPTE_R_N
|
323 native_unlock_hpte(hptep
);
325 /* Ensure it is out of the tlb too. */
326 tlbie(vpn
, bpsize
, apsize
, ssize
, local
);
330 static long native_hpte_find(unsigned long vpn
, int psize
, int ssize
)
332 struct hash_pte
*hptep
;
336 unsigned long want_v
, hpte_v
;
338 hash
= hpt_hash(vpn
, mmu_psize_defs
[psize
].shift
, ssize
);
339 want_v
= hpte_encode_avpn(vpn
, psize
, ssize
);
341 /* Bolted mappings are only ever in the primary group */
342 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
343 for (i
= 0; i
< HPTES_PER_GROUP
; i
++) {
344 hptep
= htab_address
+ slot
;
345 hpte_v
= be64_to_cpu(hptep
->v
);
347 if (HPTE_V_COMPARE(hpte_v
, want_v
) && (hpte_v
& HPTE_V_VALID
))
357 * Update the page protection bits. Intended to be used to create
358 * guard pages for kernel data structures on pages which are bolted
359 * in the HPT. Assumes pages being operated on will not be stolen.
361 * No need to lock here because we should be the only user.
363 static void native_hpte_updateboltedpp(unsigned long newpp
, unsigned long ea
,
364 int psize
, int ssize
)
369 struct hash_pte
*hptep
;
371 vsid
= get_kernel_vsid(ea
, ssize
);
372 vpn
= hpt_vpn(ea
, vsid
, ssize
);
374 slot
= native_hpte_find(vpn
, psize
, ssize
);
376 panic("could not find page to bolt\n");
377 hptep
= htab_address
+ slot
;
379 /* Update the HPTE */
380 hptep
->r
= cpu_to_be64((be64_to_cpu(hptep
->r
) &
381 ~(HPTE_R_PP
| HPTE_R_N
)) |
382 (newpp
& (HPTE_R_PP
| HPTE_R_N
)));
384 * Ensure it is out of the tlb too. Bolted entries base and
385 * actual page size will be same.
387 tlbie(vpn
, psize
, psize
, ssize
, 0);
390 static void native_hpte_invalidate(unsigned long slot
, unsigned long vpn
,
391 int bpsize
, int apsize
, int ssize
, int local
)
393 struct hash_pte
*hptep
= htab_address
+ slot
;
394 unsigned long hpte_v
;
395 unsigned long want_v
;
398 local_irq_save(flags
);
400 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn
, slot
);
402 want_v
= hpte_encode_avpn(vpn
, bpsize
, ssize
);
403 native_lock_hpte(hptep
);
404 hpte_v
= be64_to_cpu(hptep
->v
);
407 * We need to invalidate the TLB always because hpte_remove doesn't do
408 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
409 * random entry from it. When we do that we don't invalidate the TLB
410 * (hpte_remove) because we assume the old translation is still
411 * technically "valid".
413 if (!HPTE_V_COMPARE(hpte_v
, want_v
) || !(hpte_v
& HPTE_V_VALID
))
414 native_unlock_hpte(hptep
);
416 /* Invalidate the hpte. NOTE: this also unlocks it */
419 /* Invalidate the TLB */
420 tlbie(vpn
, bpsize
, apsize
, ssize
, local
);
422 local_irq_restore(flags
);
425 static void native_hugepage_invalidate(unsigned long vsid
,
427 unsigned char *hpte_slot_array
,
428 int psize
, int ssize
)
431 struct hash_pte
*hptep
;
432 int actual_psize
= MMU_PAGE_16M
;
433 unsigned int max_hpte_count
, valid
;
434 unsigned long flags
, s_addr
= addr
;
435 unsigned long hpte_v
, want_v
, shift
;
436 unsigned long hidx
, vpn
= 0, hash
, slot
;
438 shift
= mmu_psize_defs
[psize
].shift
;
439 max_hpte_count
= 1U << (PMD_SHIFT
- shift
);
441 local_irq_save(flags
);
442 for (i
= 0; i
< max_hpte_count
; i
++) {
443 valid
= hpte_valid(hpte_slot_array
, i
);
446 hidx
= hpte_hash_index(hpte_slot_array
, i
);
449 addr
= s_addr
+ (i
* (1ul << shift
));
450 vpn
= hpt_vpn(addr
, vsid
, ssize
);
451 hash
= hpt_hash(vpn
, shift
, ssize
);
452 if (hidx
& _PTEIDX_SECONDARY
)
455 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
456 slot
+= hidx
& _PTEIDX_GROUP_IX
;
458 hptep
= htab_address
+ slot
;
459 want_v
= hpte_encode_avpn(vpn
, psize
, ssize
);
460 native_lock_hpte(hptep
);
461 hpte_v
= be64_to_cpu(hptep
->v
);
463 /* Even if we miss, we need to invalidate the TLB */
464 if (!HPTE_V_COMPARE(hpte_v
, want_v
) || !(hpte_v
& HPTE_V_VALID
))
465 native_unlock_hpte(hptep
);
467 /* Invalidate the hpte. NOTE: this also unlocks it */
470 * We need to do tlb invalidate for all the address, tlbie
471 * instruction compares entry_VA in tlb with the VA specified
474 tlbie(vpn
, psize
, actual_psize
, ssize
, 0);
476 local_irq_restore(flags
);
479 static inline int __hpte_actual_psize(unsigned int lp
, int psize
)
484 /* start from 1 ignoring MMU_PAGE_4K */
485 for (i
= 1; i
< MMU_PAGE_COUNT
; i
++) {
488 if (mmu_psize_defs
[psize
].penc
[i
] == -1)
491 * encoding bits per actual page size
492 * PTE LP actual page size
499 shift
= mmu_psize_defs
[i
].shift
- LP_SHIFT
;
502 mask
= (1 << shift
) - 1;
503 if ((lp
& mask
) == mmu_psize_defs
[psize
].penc
[i
])
509 static void hpte_decode(struct hash_pte
*hpte
, unsigned long slot
,
510 int *psize
, int *apsize
, int *ssize
, unsigned long *vpn
)
512 unsigned long avpn
, pteg
, vpi
;
513 unsigned long hpte_v
= be64_to_cpu(hpte
->v
);
514 unsigned long hpte_r
= be64_to_cpu(hpte
->r
);
515 unsigned long vsid
, seg_off
;
516 int size
, a_size
, shift
;
517 /* Look at the 8 bit LP value */
518 unsigned int lp
= (hpte_r
>> LP_SHIFT
) & ((1 << LP_BITS
) - 1);
520 if (!(hpte_v
& HPTE_V_LARGE
)) {
522 a_size
= MMU_PAGE_4K
;
524 for (size
= 0; size
< MMU_PAGE_COUNT
; size
++) {
526 /* valid entries have a shift value */
527 if (!mmu_psize_defs
[size
].shift
)
530 a_size
= __hpte_actual_psize(lp
, size
);
535 /* This works for all page sizes, and for 256M and 1T segments */
536 *ssize
= hpte_v
>> HPTE_V_SSIZE_SHIFT
;
537 shift
= mmu_psize_defs
[size
].shift
;
539 avpn
= (HPTE_V_AVPN_VAL(hpte_v
) & ~mmu_psize_defs
[size
].avpnm
);
540 pteg
= slot
/ HPTES_PER_GROUP
;
541 if (hpte_v
& HPTE_V_SECONDARY
)
545 case MMU_SEGSIZE_256M
:
546 /* We only have 28 - 23 bits of seg_off in avpn */
547 seg_off
= (avpn
& 0x1f) << 23;
549 /* We can find more bits from the pteg value */
551 vpi
= (vsid
^ pteg
) & htab_hash_mask
;
552 seg_off
|= vpi
<< shift
;
554 *vpn
= vsid
<< (SID_SHIFT
- VPN_SHIFT
) | seg_off
>> VPN_SHIFT
;
557 /* We only have 40 - 23 bits of seg_off in avpn */
558 seg_off
= (avpn
& 0x1ffff) << 23;
561 vpi
= (vsid
^ (vsid
<< 25) ^ pteg
) & htab_hash_mask
;
562 seg_off
|= vpi
<< shift
;
564 *vpn
= vsid
<< (SID_SHIFT_1T
- VPN_SHIFT
) | seg_off
>> VPN_SHIFT
;
574 * clear all mappings on kexec. All cpus are in real mode (or they will
575 * be when they isi), and we are the only one left. We rely on our kernel
576 * mapping being 0xC0's and the hardware ignoring those two real bits.
578 * TODO: add batching support when enabled. remember, no dynamic memory here,
579 * athough there is the control page available...
581 static void native_hpte_clear(void)
583 unsigned long vpn
= 0;
584 unsigned long slot
, slots
, flags
;
585 struct hash_pte
*hptep
= htab_address
;
586 unsigned long hpte_v
;
587 unsigned long pteg_count
;
588 int psize
, apsize
, ssize
;
590 pteg_count
= htab_hash_mask
+ 1;
592 local_irq_save(flags
);
594 /* we take the tlbie lock and hold it. Some hardware will
595 * deadlock if we try to tlbie from two processors at once.
597 raw_spin_lock(&native_tlbie_lock
);
599 slots
= pteg_count
* HPTES_PER_GROUP
;
601 for (slot
= 0; slot
< slots
; slot
++, hptep
++) {
603 * we could lock the pte here, but we are the only cpu
604 * running, right? and for crash dump, we probably
605 * don't want to wait for a maybe bad cpu.
607 hpte_v
= be64_to_cpu(hptep
->v
);
610 * Call __tlbie() here rather than tlbie() since we
611 * already hold the native_tlbie_lock.
613 if (hpte_v
& HPTE_V_VALID
) {
614 hpte_decode(hptep
, slot
, &psize
, &apsize
, &ssize
, &vpn
);
616 __tlbie(vpn
, psize
, apsize
, ssize
);
620 asm volatile("eieio; tlbsync; ptesync":::"memory");
621 raw_spin_unlock(&native_tlbie_lock
);
622 local_irq_restore(flags
);
626 * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
627 * the lock all the time
629 static void native_flush_hash_range(unsigned long number
, int local
)
632 unsigned long hash
, index
, hidx
, shift
, slot
;
633 struct hash_pte
*hptep
;
634 unsigned long hpte_v
;
635 unsigned long want_v
;
638 struct ppc64_tlb_batch
*batch
= this_cpu_ptr(&ppc64_tlb_batch
);
639 unsigned long psize
= batch
->psize
;
640 int ssize
= batch
->ssize
;
643 local_irq_save(flags
);
645 for (i
= 0; i
< number
; i
++) {
649 pte_iterate_hashed_subpages(pte
, psize
, vpn
, index
, shift
) {
650 hash
= hpt_hash(vpn
, shift
, ssize
);
651 hidx
= __rpte_to_hidx(pte
, index
);
652 if (hidx
& _PTEIDX_SECONDARY
)
654 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
655 slot
+= hidx
& _PTEIDX_GROUP_IX
;
656 hptep
= htab_address
+ slot
;
657 want_v
= hpte_encode_avpn(vpn
, psize
, ssize
);
658 native_lock_hpte(hptep
);
659 hpte_v
= be64_to_cpu(hptep
->v
);
660 if (!HPTE_V_COMPARE(hpte_v
, want_v
) ||
661 !(hpte_v
& HPTE_V_VALID
))
662 native_unlock_hpte(hptep
);
665 } pte_iterate_hashed_end();
668 if (mmu_has_feature(MMU_FTR_TLBIEL
) &&
669 mmu_psize_defs
[psize
].tlbiel
&& local
) {
670 asm volatile("ptesync":::"memory");
671 for (i
= 0; i
< number
; i
++) {
675 pte_iterate_hashed_subpages(pte
, psize
,
677 __tlbiel(vpn
, psize
, psize
, ssize
);
678 } pte_iterate_hashed_end();
680 asm volatile("ptesync":::"memory");
682 int lock_tlbie
= !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE
);
685 raw_spin_lock(&native_tlbie_lock
);
687 asm volatile("ptesync":::"memory");
688 for (i
= 0; i
< number
; i
++) {
692 pte_iterate_hashed_subpages(pte
, psize
,
694 __tlbie(vpn
, psize
, psize
, ssize
);
695 } pte_iterate_hashed_end();
697 asm volatile("eieio; tlbsync; ptesync":::"memory");
700 raw_spin_unlock(&native_tlbie_lock
);
703 local_irq_restore(flags
);
706 void __init
hpte_init_native(void)
708 ppc_md
.hpte_invalidate
= native_hpte_invalidate
;
709 ppc_md
.hpte_updatepp
= native_hpte_updatepp
;
710 ppc_md
.hpte_updateboltedpp
= native_hpte_updateboltedpp
;
711 ppc_md
.hpte_insert
= native_hpte_insert
;
712 ppc_md
.hpte_remove
= native_hpte_remove
;
713 ppc_md
.hpte_clear_all
= native_hpte_clear
;
714 ppc_md
.flush_hash_range
= native_flush_hash_range
;
715 ppc_md
.hugepage_invalidate
= native_hugepage_invalidate
;