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powerpc/mm: Check for matching hpte without taking hpte lock
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1 /*
2 * native hashtable management.
3 *
4 * SMP scalability work:
5 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #undef DEBUG_LOW
14
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
17 #include <linux/of.h>
18 #include <linux/threads.h>
19 #include <linux/smp.h>
20
21 #include <asm/machdep.h>
22 #include <asm/mmu.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
25 #include <asm/tlbflush.h>
26 #include <asm/tlb.h>
27 #include <asm/cputable.h>
28 #include <asm/udbg.h>
29 #include <asm/kexec.h>
30 #include <asm/ppc-opcode.h>
31
32 #include <misc/cxl.h>
33
34 #ifdef DEBUG_LOW
35 #define DBG_LOW(fmt...) udbg_printf(fmt)
36 #else
37 #define DBG_LOW(fmt...)
38 #endif
39
40 #ifdef __BIG_ENDIAN__
41 #define HPTE_LOCK_BIT 3
42 #else
43 #define HPTE_LOCK_BIT (56+3)
44 #endif
45
46 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
47
48 static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
49 {
50 unsigned long va;
51 unsigned int penc;
52 unsigned long sllp;
53
54 /*
55 * We need 14 to 65 bits of va for a tlibe of 4K page
56 * With vpn we ignore the lower VPN_SHIFT bits already.
57 * And top two bits are already ignored because we can
58 * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
59 * of 12.
60 */
61 va = vpn << VPN_SHIFT;
62 /*
63 * clear top 16 bits of 64bit va, non SLS segment
64 * Older versions of the architecture (2.02 and earler) require the
65 * masking of the top 16 bits.
66 */
67 va &= ~(0xffffULL << 48);
68
69 switch (psize) {
70 case MMU_PAGE_4K:
71 /* clear out bits after (52) [0....52.....63] */
72 va &= ~((1ul << (64 - 52)) - 1);
73 va |= ssize << 8;
74 sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) |
75 ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4);
76 va |= sllp << 5;
77 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
78 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
79 : "memory");
80 break;
81 default:
82 /* We need 14 to 14 + i bits of va */
83 penc = mmu_psize_defs[psize].penc[apsize];
84 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
85 va |= penc << 12;
86 va |= ssize << 8;
87 /*
88 * AVAL bits:
89 * We don't need all the bits, but rest of the bits
90 * must be ignored by the processor.
91 * vpn cover upto 65 bits of va. (0...65) and we need
92 * 58..64 bits of va.
93 */
94 va |= (vpn & 0xfe); /* AVAL */
95 va |= 1; /* L */
96 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
97 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
98 : "memory");
99 break;
100 }
101 }
102
103 static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
104 {
105 unsigned long va;
106 unsigned int penc;
107 unsigned long sllp;
108
109 /* VPN_SHIFT can be atmost 12 */
110 va = vpn << VPN_SHIFT;
111 /*
112 * clear top 16 bits of 64 bit va, non SLS segment
113 * Older versions of the architecture (2.02 and earler) require the
114 * masking of the top 16 bits.
115 */
116 va &= ~(0xffffULL << 48);
117
118 switch (psize) {
119 case MMU_PAGE_4K:
120 /* clear out bits after(52) [0....52.....63] */
121 va &= ~((1ul << (64 - 52)) - 1);
122 va |= ssize << 8;
123 sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) |
124 ((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4);
125 va |= sllp << 5;
126 asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
127 : : "r"(va) : "memory");
128 break;
129 default:
130 /* We need 14 to 14 + i bits of va */
131 penc = mmu_psize_defs[psize].penc[apsize];
132 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
133 va |= penc << 12;
134 va |= ssize << 8;
135 /*
136 * AVAL bits:
137 * We don't need all the bits, but rest of the bits
138 * must be ignored by the processor.
139 * vpn cover upto 65 bits of va. (0...65) and we need
140 * 58..64 bits of va.
141 */
142 va |= (vpn & 0xfe);
143 va |= 1; /* L */
144 asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
145 : : "r"(va) : "memory");
146 break;
147 }
148
149 }
150
151 static inline void tlbie(unsigned long vpn, int psize, int apsize,
152 int ssize, int local)
153 {
154 unsigned int use_local;
155 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
156
157 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use();
158
159 if (use_local)
160 use_local = mmu_psize_defs[psize].tlbiel;
161 if (lock_tlbie && !use_local)
162 raw_spin_lock(&native_tlbie_lock);
163 asm volatile("ptesync": : :"memory");
164 if (use_local) {
165 __tlbiel(vpn, psize, apsize, ssize);
166 asm volatile("ptesync": : :"memory");
167 } else {
168 __tlbie(vpn, psize, apsize, ssize);
169 asm volatile("eieio; tlbsync; ptesync": : :"memory");
170 }
171 if (lock_tlbie && !use_local)
172 raw_spin_unlock(&native_tlbie_lock);
173 }
174
175 static inline void native_lock_hpte(struct hash_pte *hptep)
176 {
177 unsigned long *word = (unsigned long *)&hptep->v;
178
179 while (1) {
180 if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
181 break;
182 while(test_bit(HPTE_LOCK_BIT, word))
183 cpu_relax();
184 }
185 }
186
187 static inline void native_unlock_hpte(struct hash_pte *hptep)
188 {
189 unsigned long *word = (unsigned long *)&hptep->v;
190
191 clear_bit_unlock(HPTE_LOCK_BIT, word);
192 }
193
194 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
195 unsigned long pa, unsigned long rflags,
196 unsigned long vflags, int psize, int apsize, int ssize)
197 {
198 struct hash_pte *hptep = htab_address + hpte_group;
199 unsigned long hpte_v, hpte_r;
200 int i;
201
202 if (!(vflags & HPTE_V_BOLTED)) {
203 DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
204 " rflags=%lx, vflags=%lx, psize=%d)\n",
205 hpte_group, vpn, pa, rflags, vflags, psize);
206 }
207
208 for (i = 0; i < HPTES_PER_GROUP; i++) {
209 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) {
210 /* retry with lock held */
211 native_lock_hpte(hptep);
212 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID))
213 break;
214 native_unlock_hpte(hptep);
215 }
216
217 hptep++;
218 }
219
220 if (i == HPTES_PER_GROUP)
221 return -1;
222
223 hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
224 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
225
226 if (!(vflags & HPTE_V_BOLTED)) {
227 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
228 i, hpte_v, hpte_r);
229 }
230
231 hptep->r = cpu_to_be64(hpte_r);
232 /* Guarantee the second dword is visible before the valid bit */
233 eieio();
234 /*
235 * Now set the first dword including the valid bit
236 * NOTE: this also unlocks the hpte
237 */
238 hptep->v = cpu_to_be64(hpte_v);
239
240 __asm__ __volatile__ ("ptesync" : : : "memory");
241
242 return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
243 }
244
245 static long native_hpte_remove(unsigned long hpte_group)
246 {
247 struct hash_pte *hptep;
248 int i;
249 int slot_offset;
250 unsigned long hpte_v;
251
252 DBG_LOW(" remove(group=%lx)\n", hpte_group);
253
254 /* pick a random entry to start at */
255 slot_offset = mftb() & 0x7;
256
257 for (i = 0; i < HPTES_PER_GROUP; i++) {
258 hptep = htab_address + hpte_group + slot_offset;
259 hpte_v = be64_to_cpu(hptep->v);
260
261 if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
262 /* retry with lock held */
263 native_lock_hpte(hptep);
264 hpte_v = be64_to_cpu(hptep->v);
265 if ((hpte_v & HPTE_V_VALID)
266 && !(hpte_v & HPTE_V_BOLTED))
267 break;
268 native_unlock_hpte(hptep);
269 }
270
271 slot_offset++;
272 slot_offset &= 0x7;
273 }
274
275 if (i == HPTES_PER_GROUP)
276 return -1;
277
278 /* Invalidate the hpte. NOTE: this also unlocks it */
279 hptep->v = 0;
280
281 return i;
282 }
283
284 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
285 unsigned long vpn, int bpsize,
286 int apsize, int ssize, int local)
287 {
288 struct hash_pte *hptep = htab_address + slot;
289 unsigned long hpte_v, want_v;
290 int ret = 0;
291
292 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
293
294 DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
295 vpn, want_v & HPTE_V_AVPN, slot, newpp);
296
297 hpte_v = be64_to_cpu(hptep->v);
298 /*
299 * We need to invalidate the TLB always because hpte_remove doesn't do
300 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
301 * random entry from it. When we do that we don't invalidate the TLB
302 * (hpte_remove) because we assume the old translation is still
303 * technically "valid".
304 */
305 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
306 DBG_LOW(" -> miss\n");
307 ret = -1;
308 } else {
309 native_lock_hpte(hptep);
310 /* recheck with locks held */
311 hpte_v = be64_to_cpu(hptep->v);
312 if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) ||
313 !(hpte_v & HPTE_V_VALID))) {
314 ret = -1;
315 } else {
316 DBG_LOW(" -> hit\n");
317 /* Update the HPTE */
318 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
319 ~(HPTE_R_PP | HPTE_R_N)) |
320 (newpp & (HPTE_R_PP | HPTE_R_N |
321 HPTE_R_C)));
322 }
323 native_unlock_hpte(hptep);
324 }
325 /* Ensure it is out of the tlb too. */
326 tlbie(vpn, bpsize, apsize, ssize, local);
327 return ret;
328 }
329
330 static long native_hpte_find(unsigned long vpn, int psize, int ssize)
331 {
332 struct hash_pte *hptep;
333 unsigned long hash;
334 unsigned long i;
335 long slot;
336 unsigned long want_v, hpte_v;
337
338 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
339 want_v = hpte_encode_avpn(vpn, psize, ssize);
340
341 /* Bolted mappings are only ever in the primary group */
342 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
343 for (i = 0; i < HPTES_PER_GROUP; i++) {
344 hptep = htab_address + slot;
345 hpte_v = be64_to_cpu(hptep->v);
346
347 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
348 /* HPTE matches */
349 return slot;
350 ++slot;
351 }
352
353 return -1;
354 }
355
356 /*
357 * Update the page protection bits. Intended to be used to create
358 * guard pages for kernel data structures on pages which are bolted
359 * in the HPT. Assumes pages being operated on will not be stolen.
360 *
361 * No need to lock here because we should be the only user.
362 */
363 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
364 int psize, int ssize)
365 {
366 unsigned long vpn;
367 unsigned long vsid;
368 long slot;
369 struct hash_pte *hptep;
370
371 vsid = get_kernel_vsid(ea, ssize);
372 vpn = hpt_vpn(ea, vsid, ssize);
373
374 slot = native_hpte_find(vpn, psize, ssize);
375 if (slot == -1)
376 panic("could not find page to bolt\n");
377 hptep = htab_address + slot;
378
379 /* Update the HPTE */
380 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
381 ~(HPTE_R_PP | HPTE_R_N)) |
382 (newpp & (HPTE_R_PP | HPTE_R_N)));
383 /*
384 * Ensure it is out of the tlb too. Bolted entries base and
385 * actual page size will be same.
386 */
387 tlbie(vpn, psize, psize, ssize, 0);
388 }
389
390 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
391 int bpsize, int apsize, int ssize, int local)
392 {
393 struct hash_pte *hptep = htab_address + slot;
394 unsigned long hpte_v;
395 unsigned long want_v;
396 unsigned long flags;
397
398 local_irq_save(flags);
399
400 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
401
402 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
403 native_lock_hpte(hptep);
404 hpte_v = be64_to_cpu(hptep->v);
405
406 /*
407 * We need to invalidate the TLB always because hpte_remove doesn't do
408 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
409 * random entry from it. When we do that we don't invalidate the TLB
410 * (hpte_remove) because we assume the old translation is still
411 * technically "valid".
412 */
413 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
414 native_unlock_hpte(hptep);
415 else
416 /* Invalidate the hpte. NOTE: this also unlocks it */
417 hptep->v = 0;
418
419 /* Invalidate the TLB */
420 tlbie(vpn, bpsize, apsize, ssize, local);
421
422 local_irq_restore(flags);
423 }
424
425 static void native_hugepage_invalidate(unsigned long vsid,
426 unsigned long addr,
427 unsigned char *hpte_slot_array,
428 int psize, int ssize)
429 {
430 int i;
431 struct hash_pte *hptep;
432 int actual_psize = MMU_PAGE_16M;
433 unsigned int max_hpte_count, valid;
434 unsigned long flags, s_addr = addr;
435 unsigned long hpte_v, want_v, shift;
436 unsigned long hidx, vpn = 0, hash, slot;
437
438 shift = mmu_psize_defs[psize].shift;
439 max_hpte_count = 1U << (PMD_SHIFT - shift);
440
441 local_irq_save(flags);
442 for (i = 0; i < max_hpte_count; i++) {
443 valid = hpte_valid(hpte_slot_array, i);
444 if (!valid)
445 continue;
446 hidx = hpte_hash_index(hpte_slot_array, i);
447
448 /* get the vpn */
449 addr = s_addr + (i * (1ul << shift));
450 vpn = hpt_vpn(addr, vsid, ssize);
451 hash = hpt_hash(vpn, shift, ssize);
452 if (hidx & _PTEIDX_SECONDARY)
453 hash = ~hash;
454
455 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
456 slot += hidx & _PTEIDX_GROUP_IX;
457
458 hptep = htab_address + slot;
459 want_v = hpte_encode_avpn(vpn, psize, ssize);
460 native_lock_hpte(hptep);
461 hpte_v = be64_to_cpu(hptep->v);
462
463 /* Even if we miss, we need to invalidate the TLB */
464 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
465 native_unlock_hpte(hptep);
466 else
467 /* Invalidate the hpte. NOTE: this also unlocks it */
468 hptep->v = 0;
469 /*
470 * We need to do tlb invalidate for all the address, tlbie
471 * instruction compares entry_VA in tlb with the VA specified
472 * here
473 */
474 tlbie(vpn, psize, actual_psize, ssize, 0);
475 }
476 local_irq_restore(flags);
477 }
478
479 static inline int __hpte_actual_psize(unsigned int lp, int psize)
480 {
481 int i, shift;
482 unsigned int mask;
483
484 /* start from 1 ignoring MMU_PAGE_4K */
485 for (i = 1; i < MMU_PAGE_COUNT; i++) {
486
487 /* invalid penc */
488 if (mmu_psize_defs[psize].penc[i] == -1)
489 continue;
490 /*
491 * encoding bits per actual page size
492 * PTE LP actual page size
493 * rrrr rrrz >=8KB
494 * rrrr rrzz >=16KB
495 * rrrr rzzz >=32KB
496 * rrrr zzzz >=64KB
497 * .......
498 */
499 shift = mmu_psize_defs[i].shift - LP_SHIFT;
500 if (shift > LP_BITS)
501 shift = LP_BITS;
502 mask = (1 << shift) - 1;
503 if ((lp & mask) == mmu_psize_defs[psize].penc[i])
504 return i;
505 }
506 return -1;
507 }
508
509 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
510 int *psize, int *apsize, int *ssize, unsigned long *vpn)
511 {
512 unsigned long avpn, pteg, vpi;
513 unsigned long hpte_v = be64_to_cpu(hpte->v);
514 unsigned long hpte_r = be64_to_cpu(hpte->r);
515 unsigned long vsid, seg_off;
516 int size, a_size, shift;
517 /* Look at the 8 bit LP value */
518 unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
519
520 if (!(hpte_v & HPTE_V_LARGE)) {
521 size = MMU_PAGE_4K;
522 a_size = MMU_PAGE_4K;
523 } else {
524 for (size = 0; size < MMU_PAGE_COUNT; size++) {
525
526 /* valid entries have a shift value */
527 if (!mmu_psize_defs[size].shift)
528 continue;
529
530 a_size = __hpte_actual_psize(lp, size);
531 if (a_size != -1)
532 break;
533 }
534 }
535 /* This works for all page sizes, and for 256M and 1T segments */
536 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
537 shift = mmu_psize_defs[size].shift;
538
539 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
540 pteg = slot / HPTES_PER_GROUP;
541 if (hpte_v & HPTE_V_SECONDARY)
542 pteg = ~pteg;
543
544 switch (*ssize) {
545 case MMU_SEGSIZE_256M:
546 /* We only have 28 - 23 bits of seg_off in avpn */
547 seg_off = (avpn & 0x1f) << 23;
548 vsid = avpn >> 5;
549 /* We can find more bits from the pteg value */
550 if (shift < 23) {
551 vpi = (vsid ^ pteg) & htab_hash_mask;
552 seg_off |= vpi << shift;
553 }
554 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
555 break;
556 case MMU_SEGSIZE_1T:
557 /* We only have 40 - 23 bits of seg_off in avpn */
558 seg_off = (avpn & 0x1ffff) << 23;
559 vsid = avpn >> 17;
560 if (shift < 23) {
561 vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
562 seg_off |= vpi << shift;
563 }
564 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
565 break;
566 default:
567 *vpn = size = 0;
568 }
569 *psize = size;
570 *apsize = a_size;
571 }
572
573 /*
574 * clear all mappings on kexec. All cpus are in real mode (or they will
575 * be when they isi), and we are the only one left. We rely on our kernel
576 * mapping being 0xC0's and the hardware ignoring those two real bits.
577 *
578 * TODO: add batching support when enabled. remember, no dynamic memory here,
579 * athough there is the control page available...
580 */
581 static void native_hpte_clear(void)
582 {
583 unsigned long vpn = 0;
584 unsigned long slot, slots, flags;
585 struct hash_pte *hptep = htab_address;
586 unsigned long hpte_v;
587 unsigned long pteg_count;
588 int psize, apsize, ssize;
589
590 pteg_count = htab_hash_mask + 1;
591
592 local_irq_save(flags);
593
594 /* we take the tlbie lock and hold it. Some hardware will
595 * deadlock if we try to tlbie from two processors at once.
596 */
597 raw_spin_lock(&native_tlbie_lock);
598
599 slots = pteg_count * HPTES_PER_GROUP;
600
601 for (slot = 0; slot < slots; slot++, hptep++) {
602 /*
603 * we could lock the pte here, but we are the only cpu
604 * running, right? and for crash dump, we probably
605 * don't want to wait for a maybe bad cpu.
606 */
607 hpte_v = be64_to_cpu(hptep->v);
608
609 /*
610 * Call __tlbie() here rather than tlbie() since we
611 * already hold the native_tlbie_lock.
612 */
613 if (hpte_v & HPTE_V_VALID) {
614 hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
615 hptep->v = 0;
616 __tlbie(vpn, psize, apsize, ssize);
617 }
618 }
619
620 asm volatile("eieio; tlbsync; ptesync":::"memory");
621 raw_spin_unlock(&native_tlbie_lock);
622 local_irq_restore(flags);
623 }
624
625 /*
626 * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
627 * the lock all the time
628 */
629 static void native_flush_hash_range(unsigned long number, int local)
630 {
631 unsigned long vpn;
632 unsigned long hash, index, hidx, shift, slot;
633 struct hash_pte *hptep;
634 unsigned long hpte_v;
635 unsigned long want_v;
636 unsigned long flags;
637 real_pte_t pte;
638 struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);
639 unsigned long psize = batch->psize;
640 int ssize = batch->ssize;
641 int i;
642
643 local_irq_save(flags);
644
645 for (i = 0; i < number; i++) {
646 vpn = batch->vpn[i];
647 pte = batch->pte[i];
648
649 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
650 hash = hpt_hash(vpn, shift, ssize);
651 hidx = __rpte_to_hidx(pte, index);
652 if (hidx & _PTEIDX_SECONDARY)
653 hash = ~hash;
654 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
655 slot += hidx & _PTEIDX_GROUP_IX;
656 hptep = htab_address + slot;
657 want_v = hpte_encode_avpn(vpn, psize, ssize);
658 native_lock_hpte(hptep);
659 hpte_v = be64_to_cpu(hptep->v);
660 if (!HPTE_V_COMPARE(hpte_v, want_v) ||
661 !(hpte_v & HPTE_V_VALID))
662 native_unlock_hpte(hptep);
663 else
664 hptep->v = 0;
665 } pte_iterate_hashed_end();
666 }
667
668 if (mmu_has_feature(MMU_FTR_TLBIEL) &&
669 mmu_psize_defs[psize].tlbiel && local) {
670 asm volatile("ptesync":::"memory");
671 for (i = 0; i < number; i++) {
672 vpn = batch->vpn[i];
673 pte = batch->pte[i];
674
675 pte_iterate_hashed_subpages(pte, psize,
676 vpn, index, shift) {
677 __tlbiel(vpn, psize, psize, ssize);
678 } pte_iterate_hashed_end();
679 }
680 asm volatile("ptesync":::"memory");
681 } else {
682 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
683
684 if (lock_tlbie)
685 raw_spin_lock(&native_tlbie_lock);
686
687 asm volatile("ptesync":::"memory");
688 for (i = 0; i < number; i++) {
689 vpn = batch->vpn[i];
690 pte = batch->pte[i];
691
692 pte_iterate_hashed_subpages(pte, psize,
693 vpn, index, shift) {
694 __tlbie(vpn, psize, psize, ssize);
695 } pte_iterate_hashed_end();
696 }
697 asm volatile("eieio; tlbsync; ptesync":::"memory");
698
699 if (lock_tlbie)
700 raw_spin_unlock(&native_tlbie_lock);
701 }
702
703 local_irq_restore(flags);
704 }
705
706 void __init hpte_init_native(void)
707 {
708 ppc_md.hpte_invalidate = native_hpte_invalidate;
709 ppc_md.hpte_updatepp = native_hpte_updatepp;
710 ppc_md.hpte_updateboltedpp = native_hpte_updateboltedpp;
711 ppc_md.hpte_insert = native_hpte_insert;
712 ppc_md.hpte_remove = native_hpte_remove;
713 ppc_md.hpte_clear_all = native_hpte_clear;
714 ppc_md.flush_hash_range = native_flush_hash_range;
715 ppc_md.hugepage_invalidate = native_hugepage_invalidate;
716 }