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1 /*
2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
4 *
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
6 *
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
9 *
10 * Module name: htab.c
11 *
12 * Description:
13 * PowerPC Hashed Page Table functions
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 */
20
21 #undef DEBUG
22 #undef DEBUG_LOW
23
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
34 #include <linux/lmb.h>
35
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
38 #include <asm/mmu.h>
39 #include <asm/mmu_context.h>
40 #include <asm/page.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
45 #include <asm/prom.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
48 #include <asm/io.h>
49 #include <asm/eeh.h>
50 #include <asm/tlb.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/spu.h>
55 #include <asm/udbg.h>
56
57 #ifdef DEBUG
58 #define DBG(fmt...) udbg_printf(fmt)
59 #else
60 #define DBG(fmt...)
61 #endif
62
63 #ifdef DEBUG_LOW
64 #define DBG_LOW(fmt...) udbg_printf(fmt)
65 #else
66 #define DBG_LOW(fmt...)
67 #endif
68
69 #define KB (1024)
70 #define MB (1024*KB)
71
72 /*
73 * Note: pte --> Linux PTE
74 * HPTE --> PowerPC Hashed Page Table Entry
75 *
76 * Execution context:
77 * htab_initialize is called with the MMU off (of course), but
78 * the kernel has been copied down to zero so it can directly
79 * reference global data. At this point it is very difficult
80 * to print debug info.
81 *
82 */
83
84 #ifdef CONFIG_U3_DART
85 extern unsigned long dart_tablebase;
86 #endif /* CONFIG_U3_DART */
87
88 static unsigned long _SDR1;
89 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
90
91 struct hash_pte *htab_address;
92 unsigned long htab_size_bytes;
93 unsigned long htab_hash_mask;
94 int mmu_linear_psize = MMU_PAGE_4K;
95 int mmu_virtual_psize = MMU_PAGE_4K;
96 int mmu_vmalloc_psize = MMU_PAGE_4K;
97 int mmu_io_psize = MMU_PAGE_4K;
98 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
99 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
100 u16 mmu_slb_size = 64;
101 #ifdef CONFIG_HUGETLB_PAGE
102 int mmu_huge_psize = MMU_PAGE_16M;
103 unsigned int HPAGE_SHIFT;
104 #endif
105 #ifdef CONFIG_PPC_64K_PAGES
106 int mmu_ci_restrictions;
107 #endif
108 #ifdef CONFIG_DEBUG_PAGEALLOC
109 static u8 *linear_map_hash_slots;
110 static unsigned long linear_map_hash_count;
111 static DEFINE_SPINLOCK(linear_map_hash_lock);
112 #endif /* CONFIG_DEBUG_PAGEALLOC */
113
114 /* There are definitions of page sizes arrays to be used when none
115 * is provided by the firmware.
116 */
117
118 /* Pre-POWER4 CPUs (4k pages only)
119 */
120 struct mmu_psize_def mmu_psize_defaults_old[] = {
121 [MMU_PAGE_4K] = {
122 .shift = 12,
123 .sllp = 0,
124 .penc = 0,
125 .avpnm = 0,
126 .tlbiel = 0,
127 },
128 };
129
130 /* POWER4, GPUL, POWER5
131 *
132 * Support for 16Mb large pages
133 */
134 struct mmu_psize_def mmu_psize_defaults_gp[] = {
135 [MMU_PAGE_4K] = {
136 .shift = 12,
137 .sllp = 0,
138 .penc = 0,
139 .avpnm = 0,
140 .tlbiel = 1,
141 },
142 [MMU_PAGE_16M] = {
143 .shift = 24,
144 .sllp = SLB_VSID_L,
145 .penc = 0,
146 .avpnm = 0x1UL,
147 .tlbiel = 0,
148 },
149 };
150
151
152 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
153 unsigned long pstart, unsigned long mode,
154 int psize, int ssize)
155 {
156 unsigned long vaddr, paddr;
157 unsigned int step, shift;
158 unsigned long tmp_mode;
159 int ret = 0;
160
161 shift = mmu_psize_defs[psize].shift;
162 step = 1 << shift;
163
164 for (vaddr = vstart, paddr = pstart; vaddr < vend;
165 vaddr += step, paddr += step) {
166 unsigned long hash, hpteg;
167 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
168 unsigned long va = hpt_va(vaddr, vsid, ssize);
169
170 tmp_mode = mode;
171
172 /* Make non-kernel text non-executable */
173 if (!in_kernel_text(vaddr))
174 tmp_mode = mode | HPTE_R_N;
175
176 hash = hpt_hash(va, shift, ssize);
177 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
178
179 DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
180
181 BUG_ON(!ppc_md.hpte_insert);
182 ret = ppc_md.hpte_insert(hpteg, va, paddr,
183 tmp_mode, HPTE_V_BOLTED, psize, ssize);
184
185 if (ret < 0)
186 break;
187 #ifdef CONFIG_DEBUG_PAGEALLOC
188 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
189 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
190 #endif /* CONFIG_DEBUG_PAGEALLOC */
191 }
192 return ret < 0 ? ret : 0;
193 }
194
195 #ifdef CONFIG_MEMORY_HOTPLUG
196 static int htab_remove_mapping(unsigned long vstart, unsigned long vend,
197 int psize, int ssize)
198 {
199 unsigned long vaddr;
200 unsigned int step, shift;
201
202 shift = mmu_psize_defs[psize].shift;
203 step = 1 << shift;
204
205 if (!ppc_md.hpte_removebolted) {
206 printk(KERN_WARNING "Platform doesn't implement "
207 "hpte_removebolted\n");
208 return -EINVAL;
209 }
210
211 for (vaddr = vstart; vaddr < vend; vaddr += step)
212 ppc_md.hpte_removebolted(vaddr, psize, ssize);
213
214 return 0;
215 }
216 #endif /* CONFIG_MEMORY_HOTPLUG */
217
218 static int __init htab_dt_scan_seg_sizes(unsigned long node,
219 const char *uname, int depth,
220 void *data)
221 {
222 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
223 u32 *prop;
224 unsigned long size = 0;
225
226 /* We are scanning "cpu" nodes only */
227 if (type == NULL || strcmp(type, "cpu") != 0)
228 return 0;
229
230 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
231 &size);
232 if (prop == NULL)
233 return 0;
234 for (; size >= 4; size -= 4, ++prop) {
235 if (prop[0] == 40) {
236 DBG("1T segment support detected\n");
237 cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
238 return 1;
239 }
240 }
241 cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
242 return 0;
243 }
244
245 static void __init htab_init_seg_sizes(void)
246 {
247 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
248 }
249
250 static int __init htab_dt_scan_page_sizes(unsigned long node,
251 const char *uname, int depth,
252 void *data)
253 {
254 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
255 u32 *prop;
256 unsigned long size = 0;
257
258 /* We are scanning "cpu" nodes only */
259 if (type == NULL || strcmp(type, "cpu") != 0)
260 return 0;
261
262 prop = (u32 *)of_get_flat_dt_prop(node,
263 "ibm,segment-page-sizes", &size);
264 if (prop != NULL) {
265 DBG("Page sizes from device-tree:\n");
266 size /= 4;
267 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
268 while(size > 0) {
269 unsigned int shift = prop[0];
270 unsigned int slbenc = prop[1];
271 unsigned int lpnum = prop[2];
272 unsigned int lpenc = 0;
273 struct mmu_psize_def *def;
274 int idx = -1;
275
276 size -= 3; prop += 3;
277 while(size > 0 && lpnum) {
278 if (prop[0] == shift)
279 lpenc = prop[1];
280 prop += 2; size -= 2;
281 lpnum--;
282 }
283 switch(shift) {
284 case 0xc:
285 idx = MMU_PAGE_4K;
286 break;
287 case 0x10:
288 idx = MMU_PAGE_64K;
289 break;
290 case 0x14:
291 idx = MMU_PAGE_1M;
292 break;
293 case 0x18:
294 idx = MMU_PAGE_16M;
295 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
296 break;
297 case 0x22:
298 idx = MMU_PAGE_16G;
299 break;
300 }
301 if (idx < 0)
302 continue;
303 def = &mmu_psize_defs[idx];
304 def->shift = shift;
305 if (shift <= 23)
306 def->avpnm = 0;
307 else
308 def->avpnm = (1 << (shift - 23)) - 1;
309 def->sllp = slbenc;
310 def->penc = lpenc;
311 /* We don't know for sure what's up with tlbiel, so
312 * for now we only set it for 4K and 64K pages
313 */
314 if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
315 def->tlbiel = 1;
316 else
317 def->tlbiel = 0;
318
319 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
320 "tlbiel=%d, penc=%d\n",
321 idx, shift, def->sllp, def->avpnm, def->tlbiel,
322 def->penc);
323 }
324 return 1;
325 }
326 return 0;
327 }
328
329 static void __init htab_init_page_sizes(void)
330 {
331 int rc;
332
333 /* Default to 4K pages only */
334 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
335 sizeof(mmu_psize_defaults_old));
336
337 /*
338 * Try to find the available page sizes in the device-tree
339 */
340 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
341 if (rc != 0) /* Found */
342 goto found;
343
344 /*
345 * Not in the device-tree, let's fallback on known size
346 * list for 16M capable GP & GR
347 */
348 if (cpu_has_feature(CPU_FTR_16M_PAGE))
349 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
350 sizeof(mmu_psize_defaults_gp));
351 found:
352 #ifndef CONFIG_DEBUG_PAGEALLOC
353 /*
354 * Pick a size for the linear mapping. Currently, we only support
355 * 16M, 1M and 4K which is the default
356 */
357 if (mmu_psize_defs[MMU_PAGE_16M].shift)
358 mmu_linear_psize = MMU_PAGE_16M;
359 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
360 mmu_linear_psize = MMU_PAGE_1M;
361 #endif /* CONFIG_DEBUG_PAGEALLOC */
362
363 #ifdef CONFIG_PPC_64K_PAGES
364 /*
365 * Pick a size for the ordinary pages. Default is 4K, we support
366 * 64K for user mappings and vmalloc if supported by the processor.
367 * We only use 64k for ioremap if the processor
368 * (and firmware) support cache-inhibited large pages.
369 * If not, we use 4k and set mmu_ci_restrictions so that
370 * hash_page knows to switch processes that use cache-inhibited
371 * mappings to 4k pages.
372 */
373 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
374 mmu_virtual_psize = MMU_PAGE_64K;
375 mmu_vmalloc_psize = MMU_PAGE_64K;
376 if (mmu_linear_psize == MMU_PAGE_4K)
377 mmu_linear_psize = MMU_PAGE_64K;
378 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE)) {
379 /*
380 * Don't use 64k pages for ioremap on pSeries, since
381 * that would stop us accessing the HEA ethernet.
382 */
383 if (!machine_is(pseries))
384 mmu_io_psize = MMU_PAGE_64K;
385 } else
386 mmu_ci_restrictions = 1;
387 }
388 #endif /* CONFIG_PPC_64K_PAGES */
389
390 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
391 "virtual = %d, io = %d\n",
392 mmu_psize_defs[mmu_linear_psize].shift,
393 mmu_psize_defs[mmu_virtual_psize].shift,
394 mmu_psize_defs[mmu_io_psize].shift);
395
396 #ifdef CONFIG_HUGETLB_PAGE
397 /* Init large page size. Currently, we pick 16M or 1M depending
398 * on what is available
399 */
400 if (mmu_psize_defs[MMU_PAGE_16M].shift)
401 set_huge_psize(MMU_PAGE_16M);
402 /* With 4k/4level pagetables, we can't (for now) cope with a
403 * huge page size < PMD_SIZE */
404 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
405 set_huge_psize(MMU_PAGE_1M);
406 #endif /* CONFIG_HUGETLB_PAGE */
407 }
408
409 static int __init htab_dt_scan_pftsize(unsigned long node,
410 const char *uname, int depth,
411 void *data)
412 {
413 char *type = of_get_flat_dt_prop(node, "device_type", NULL);
414 u32 *prop;
415
416 /* We are scanning "cpu" nodes only */
417 if (type == NULL || strcmp(type, "cpu") != 0)
418 return 0;
419
420 prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
421 if (prop != NULL) {
422 /* pft_size[0] is the NUMA CEC cookie */
423 ppc64_pft_size = prop[1];
424 return 1;
425 }
426 return 0;
427 }
428
429 static unsigned long __init htab_get_table_size(void)
430 {
431 unsigned long mem_size, rnd_mem_size, pteg_count;
432
433 /* If hash size isn't already provided by the platform, we try to
434 * retrieve it from the device-tree. If it's not there neither, we
435 * calculate it now based on the total RAM size
436 */
437 if (ppc64_pft_size == 0)
438 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
439 if (ppc64_pft_size)
440 return 1UL << ppc64_pft_size;
441
442 /* round mem_size up to next power of 2 */
443 mem_size = lmb_phys_mem_size();
444 rnd_mem_size = 1UL << __ilog2(mem_size);
445 if (rnd_mem_size < mem_size)
446 rnd_mem_size <<= 1;
447
448 /* # pages / 2 */
449 pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
450
451 return pteg_count << 7;
452 }
453
454 #ifdef CONFIG_MEMORY_HOTPLUG
455 void create_section_mapping(unsigned long start, unsigned long end)
456 {
457 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
458 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
459 mmu_linear_psize, mmu_kernel_ssize));
460 }
461
462 int remove_section_mapping(unsigned long start, unsigned long end)
463 {
464 return htab_remove_mapping(start, end, mmu_linear_psize,
465 mmu_kernel_ssize);
466 }
467 #endif /* CONFIG_MEMORY_HOTPLUG */
468
469 static inline void make_bl(unsigned int *insn_addr, void *func)
470 {
471 unsigned long funcp = *((unsigned long *)func);
472 int offset = funcp - (unsigned long)insn_addr;
473
474 *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
475 flush_icache_range((unsigned long)insn_addr, 4+
476 (unsigned long)insn_addr);
477 }
478
479 static void __init htab_finish_init(void)
480 {
481 extern unsigned int *htab_call_hpte_insert1;
482 extern unsigned int *htab_call_hpte_insert2;
483 extern unsigned int *htab_call_hpte_remove;
484 extern unsigned int *htab_call_hpte_updatepp;
485
486 #ifdef CONFIG_PPC_HAS_HASH_64K
487 extern unsigned int *ht64_call_hpte_insert1;
488 extern unsigned int *ht64_call_hpte_insert2;
489 extern unsigned int *ht64_call_hpte_remove;
490 extern unsigned int *ht64_call_hpte_updatepp;
491
492 make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
493 make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
494 make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
495 make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
496 #endif /* CONFIG_PPC_HAS_HASH_64K */
497
498 make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
499 make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
500 make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
501 make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
502 }
503
504 void __init htab_initialize(void)
505 {
506 unsigned long table;
507 unsigned long pteg_count;
508 unsigned long mode_rw;
509 unsigned long base = 0, size = 0, limit;
510 int i;
511
512 extern unsigned long tce_alloc_start, tce_alloc_end;
513
514 DBG(" -> htab_initialize()\n");
515
516 /* Initialize segment sizes */
517 htab_init_seg_sizes();
518
519 /* Initialize page sizes */
520 htab_init_page_sizes();
521
522 if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
523 mmu_kernel_ssize = MMU_SEGSIZE_1T;
524 mmu_highuser_ssize = MMU_SEGSIZE_1T;
525 printk(KERN_INFO "Using 1TB segments\n");
526 }
527
528 /*
529 * Calculate the required size of the htab. We want the number of
530 * PTEGs to equal one half the number of real pages.
531 */
532 htab_size_bytes = htab_get_table_size();
533 pteg_count = htab_size_bytes >> 7;
534
535 htab_hash_mask = pteg_count - 1;
536
537 if (firmware_has_feature(FW_FEATURE_LPAR)) {
538 /* Using a hypervisor which owns the htab */
539 htab_address = NULL;
540 _SDR1 = 0;
541 } else {
542 /* Find storage for the HPT. Must be contiguous in
543 * the absolute address space. On cell we want it to be
544 * in the first 2 Gig so we can use it for IOMMU hacks.
545 */
546 if (machine_is(cell))
547 limit = 0x80000000;
548 else
549 limit = 0;
550
551 table = lmb_alloc_base(htab_size_bytes, htab_size_bytes, limit);
552
553 DBG("Hash table allocated at %lx, size: %lx\n", table,
554 htab_size_bytes);
555
556 htab_address = abs_to_virt(table);
557
558 /* htab absolute addr + encoded htabsize */
559 _SDR1 = table + __ilog2(pteg_count) - 11;
560
561 /* Initialize the HPT with no entries */
562 memset((void *)table, 0, htab_size_bytes);
563
564 /* Set SDR1 */
565 mtspr(SPRN_SDR1, _SDR1);
566 }
567
568 mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
569
570 #ifdef CONFIG_DEBUG_PAGEALLOC
571 linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
572 linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
573 1, lmb.rmo_size));
574 memset(linear_map_hash_slots, 0, linear_map_hash_count);
575 #endif /* CONFIG_DEBUG_PAGEALLOC */
576
577 /* On U3 based machines, we need to reserve the DART area and
578 * _NOT_ map it to avoid cache paradoxes as it's remapped non
579 * cacheable later on
580 */
581
582 /* create bolted the linear mapping in the hash table */
583 for (i=0; i < lmb.memory.cnt; i++) {
584 base = (unsigned long)__va(lmb.memory.region[i].base);
585 size = lmb.memory.region[i].size;
586
587 DBG("creating mapping for region: %lx : %lx\n", base, size);
588
589 #ifdef CONFIG_U3_DART
590 /* Do not map the DART space. Fortunately, it will be aligned
591 * in such a way that it will not cross two lmb regions and
592 * will fit within a single 16Mb page.
593 * The DART space is assumed to be a full 16Mb region even if
594 * we only use 2Mb of that space. We will use more of it later
595 * for AGP GART. We have to use a full 16Mb large page.
596 */
597 DBG("DART base: %lx\n", dart_tablebase);
598
599 if (dart_tablebase != 0 && dart_tablebase >= base
600 && dart_tablebase < (base + size)) {
601 unsigned long dart_table_end = dart_tablebase + 16 * MB;
602 if (base != dart_tablebase)
603 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
604 __pa(base), mode_rw,
605 mmu_linear_psize,
606 mmu_kernel_ssize));
607 if ((base + size) > dart_table_end)
608 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
609 base + size,
610 __pa(dart_table_end),
611 mode_rw,
612 mmu_linear_psize,
613 mmu_kernel_ssize));
614 continue;
615 }
616 #endif /* CONFIG_U3_DART */
617 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
618 mode_rw, mmu_linear_psize, mmu_kernel_ssize));
619 }
620
621 /*
622 * If we have a memory_limit and we've allocated TCEs then we need to
623 * explicitly map the TCE area at the top of RAM. We also cope with the
624 * case that the TCEs start below memory_limit.
625 * tce_alloc_start/end are 16MB aligned so the mapping should work
626 * for either 4K or 16MB pages.
627 */
628 if (tce_alloc_start) {
629 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
630 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
631
632 if (base + size >= tce_alloc_start)
633 tce_alloc_start = base + size + 1;
634
635 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
636 __pa(tce_alloc_start), mode_rw,
637 mmu_linear_psize, mmu_kernel_ssize));
638 }
639
640 htab_finish_init();
641
642 DBG(" <- htab_initialize()\n");
643 }
644 #undef KB
645 #undef MB
646
647 void htab_initialize_secondary(void)
648 {
649 if (!firmware_has_feature(FW_FEATURE_LPAR))
650 mtspr(SPRN_SDR1, _SDR1);
651 }
652
653 /*
654 * Called by asm hashtable.S for doing lazy icache flush
655 */
656 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
657 {
658 struct page *page;
659
660 if (!pfn_valid(pte_pfn(pte)))
661 return pp;
662
663 page = pte_page(pte);
664
665 /* page is dirty */
666 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
667 if (trap == 0x400) {
668 __flush_dcache_icache(page_address(page));
669 set_bit(PG_arch_1, &page->flags);
670 } else
671 pp |= HPTE_R_N;
672 }
673 return pp;
674 }
675
676 /*
677 * Demote a segment to using 4k pages.
678 * For now this makes the whole process use 4k pages.
679 */
680 #ifdef CONFIG_PPC_64K_PAGES
681 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
682 {
683 if (mm->context.user_psize == MMU_PAGE_4K)
684 return;
685 slice_set_user_psize(mm, MMU_PAGE_4K);
686 #ifdef CONFIG_SPU_BASE
687 spu_flush_all_slbs(mm);
688 #endif
689 if (get_paca()->context.user_psize != MMU_PAGE_4K) {
690 get_paca()->context = mm->context;
691 slb_flush_and_rebolt();
692 }
693 }
694 #endif /* CONFIG_PPC_64K_PAGES */
695
696 #ifdef CONFIG_PPC_SUBPAGE_PROT
697 /*
698 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
699 * Userspace sets the subpage permissions using the subpage_prot system call.
700 *
701 * Result is 0: full permissions, _PAGE_RW: read-only,
702 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
703 */
704 static int subpage_protection(pgd_t *pgdir, unsigned long ea)
705 {
706 struct subpage_prot_table *spt = pgd_subpage_prot(pgdir);
707 u32 spp = 0;
708 u32 **sbpm, *sbpp;
709
710 if (ea >= spt->maxaddr)
711 return 0;
712 if (ea < 0x100000000) {
713 /* addresses below 4GB use spt->low_prot */
714 sbpm = spt->low_prot;
715 } else {
716 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
717 if (!sbpm)
718 return 0;
719 }
720 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
721 if (!sbpp)
722 return 0;
723 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
724
725 /* extract 2-bit bitfield for this 4k subpage */
726 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
727
728 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
729 spp = ((spp & 2) ? _PAGE_USER : 0) | ((spp & 1) ? _PAGE_RW : 0);
730 return spp;
731 }
732
733 #else /* CONFIG_PPC_SUBPAGE_PROT */
734 static inline int subpage_protection(pgd_t *pgdir, unsigned long ea)
735 {
736 return 0;
737 }
738 #endif
739
740 /* Result code is:
741 * 0 - handled
742 * 1 - normal page fault
743 * -1 - critical hash insertion error
744 * -2 - access not permitted by subpage protection mechanism
745 */
746 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
747 {
748 void *pgdir;
749 unsigned long vsid;
750 struct mm_struct *mm;
751 pte_t *ptep;
752 cpumask_t tmp;
753 int rc, user_region = 0, local = 0;
754 int psize, ssize;
755
756 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
757 ea, access, trap);
758
759 if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
760 DBG_LOW(" out of pgtable range !\n");
761 return 1;
762 }
763
764 /* Get region & vsid */
765 switch (REGION_ID(ea)) {
766 case USER_REGION_ID:
767 user_region = 1;
768 mm = current->mm;
769 if (! mm) {
770 DBG_LOW(" user region with no mm !\n");
771 return 1;
772 }
773 #ifdef CONFIG_PPC_MM_SLICES
774 psize = get_slice_psize(mm, ea);
775 #else
776 psize = mm->context.user_psize;
777 #endif
778 ssize = user_segment_size(ea);
779 vsid = get_vsid(mm->context.id, ea, ssize);
780 break;
781 case VMALLOC_REGION_ID:
782 mm = &init_mm;
783 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
784 if (ea < VMALLOC_END)
785 psize = mmu_vmalloc_psize;
786 else
787 psize = mmu_io_psize;
788 ssize = mmu_kernel_ssize;
789 break;
790 default:
791 /* Not a valid range
792 * Send the problem up to do_page_fault
793 */
794 return 1;
795 }
796 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
797
798 /* Get pgdir */
799 pgdir = mm->pgd;
800 if (pgdir == NULL)
801 return 1;
802
803 /* Check CPU locality */
804 tmp = cpumask_of_cpu(smp_processor_id());
805 if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
806 local = 1;
807
808 #ifdef CONFIG_HUGETLB_PAGE
809 /* Handle hugepage regions */
810 if (HPAGE_SHIFT && psize == mmu_huge_psize) {
811 DBG_LOW(" -> huge page !\n");
812 return hash_huge_page(mm, access, ea, vsid, local, trap);
813 }
814 #endif /* CONFIG_HUGETLB_PAGE */
815
816 #ifndef CONFIG_PPC_64K_PAGES
817 /* If we use 4K pages and our psize is not 4K, then we are hitting
818 * a special driver mapping, we need to align the address before
819 * we fetch the PTE
820 */
821 if (psize != MMU_PAGE_4K)
822 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
823 #endif /* CONFIG_PPC_64K_PAGES */
824
825 /* Get PTE and page size from page tables */
826 ptep = find_linux_pte(pgdir, ea);
827 if (ptep == NULL || !pte_present(*ptep)) {
828 DBG_LOW(" no PTE !\n");
829 return 1;
830 }
831
832 #ifndef CONFIG_PPC_64K_PAGES
833 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
834 #else
835 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
836 pte_val(*(ptep + PTRS_PER_PTE)));
837 #endif
838 /* Pre-check access permissions (will be re-checked atomically
839 * in __hash_page_XX but this pre-check is a fast path
840 */
841 if (access & ~pte_val(*ptep)) {
842 DBG_LOW(" no access !\n");
843 return 1;
844 }
845
846 /* Do actual hashing */
847 #ifdef CONFIG_PPC_64K_PAGES
848 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
849 if (pte_val(*ptep) & _PAGE_4K_PFN) {
850 demote_segment_4k(mm, ea);
851 psize = MMU_PAGE_4K;
852 }
853
854 /* If this PTE is non-cacheable and we have restrictions on
855 * using non cacheable large pages, then we switch to 4k
856 */
857 if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
858 (pte_val(*ptep) & _PAGE_NO_CACHE)) {
859 if (user_region) {
860 demote_segment_4k(mm, ea);
861 psize = MMU_PAGE_4K;
862 } else if (ea < VMALLOC_END) {
863 /*
864 * some driver did a non-cacheable mapping
865 * in vmalloc space, so switch vmalloc
866 * to 4k pages
867 */
868 printk(KERN_ALERT "Reducing vmalloc segment "
869 "to 4kB pages because of "
870 "non-cacheable mapping\n");
871 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
872 #ifdef CONFIG_SPU_BASE
873 spu_flush_all_slbs(mm);
874 #endif
875 }
876 }
877 if (user_region) {
878 if (psize != get_paca()->context.user_psize) {
879 get_paca()->context = mm->context;
880 slb_flush_and_rebolt();
881 }
882 } else if (get_paca()->vmalloc_sllp !=
883 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
884 get_paca()->vmalloc_sllp =
885 mmu_psize_defs[mmu_vmalloc_psize].sllp;
886 slb_vmalloc_update();
887 }
888 #endif /* CONFIG_PPC_64K_PAGES */
889
890 #ifdef CONFIG_PPC_HAS_HASH_64K
891 if (psize == MMU_PAGE_64K)
892 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
893 else
894 #endif /* CONFIG_PPC_HAS_HASH_64K */
895 {
896 int spp = subpage_protection(pgdir, ea);
897 if (access & spp)
898 rc = -2;
899 else
900 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
901 local, ssize, spp);
902 }
903
904 #ifndef CONFIG_PPC_64K_PAGES
905 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
906 #else
907 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
908 pte_val(*(ptep + PTRS_PER_PTE)));
909 #endif
910 DBG_LOW(" -> rc=%d\n", rc);
911 return rc;
912 }
913 EXPORT_SYMBOL_GPL(hash_page);
914
915 void hash_preload(struct mm_struct *mm, unsigned long ea,
916 unsigned long access, unsigned long trap)
917 {
918 unsigned long vsid;
919 void *pgdir;
920 pte_t *ptep;
921 cpumask_t mask;
922 unsigned long flags;
923 int local = 0;
924 int ssize;
925
926 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
927
928 #ifdef CONFIG_PPC_MM_SLICES
929 /* We only prefault standard pages for now */
930 if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
931 return;
932 #endif
933
934 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
935 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
936
937 /* Get Linux PTE if available */
938 pgdir = mm->pgd;
939 if (pgdir == NULL)
940 return;
941 ptep = find_linux_pte(pgdir, ea);
942 if (!ptep)
943 return;
944
945 #ifdef CONFIG_PPC_64K_PAGES
946 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
947 * a 64K kernel), then we don't preload, hash_page() will take
948 * care of it once we actually try to access the page.
949 * That way we don't have to duplicate all of the logic for segment
950 * page size demotion here
951 */
952 if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
953 return;
954 #endif /* CONFIG_PPC_64K_PAGES */
955
956 /* Get VSID */
957 ssize = user_segment_size(ea);
958 vsid = get_vsid(mm->context.id, ea, ssize);
959
960 /* Hash doesn't like irqs */
961 local_irq_save(flags);
962
963 /* Is that local to this CPU ? */
964 mask = cpumask_of_cpu(smp_processor_id());
965 if (cpus_equal(mm->cpu_vm_mask, mask))
966 local = 1;
967
968 /* Hash it in */
969 #ifdef CONFIG_PPC_HAS_HASH_64K
970 if (mm->context.user_psize == MMU_PAGE_64K)
971 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
972 else
973 #endif /* CONFIG_PPC_HAS_HASH_64K */
974 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize,
975 subpage_protection(pgdir, ea));
976
977 local_irq_restore(flags);
978 }
979
980 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
981 * do not forget to update the assembly call site !
982 */
983 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
984 int local)
985 {
986 unsigned long hash, index, shift, hidx, slot;
987
988 DBG_LOW("flush_hash_page(va=%016x)\n", va);
989 pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
990 hash = hpt_hash(va, shift, ssize);
991 hidx = __rpte_to_hidx(pte, index);
992 if (hidx & _PTEIDX_SECONDARY)
993 hash = ~hash;
994 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
995 slot += hidx & _PTEIDX_GROUP_IX;
996 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
997 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
998 } pte_iterate_hashed_end();
999 }
1000
1001 void flush_hash_range(unsigned long number, int local)
1002 {
1003 if (ppc_md.flush_hash_range)
1004 ppc_md.flush_hash_range(number, local);
1005 else {
1006 int i;
1007 struct ppc64_tlb_batch *batch =
1008 &__get_cpu_var(ppc64_tlb_batch);
1009
1010 for (i = 0; i < number; i++)
1011 flush_hash_page(batch->vaddr[i], batch->pte[i],
1012 batch->psize, batch->ssize, local);
1013 }
1014 }
1015
1016 /*
1017 * low_hash_fault is called when we the low level hash code failed
1018 * to instert a PTE due to an hypervisor error
1019 */
1020 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1021 {
1022 if (user_mode(regs)) {
1023 #ifdef CONFIG_PPC_SUBPAGE_PROT
1024 if (rc == -2)
1025 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1026 else
1027 #endif
1028 _exception(SIGBUS, regs, BUS_ADRERR, address);
1029 } else
1030 bad_page_fault(regs, address, SIGBUS);
1031 }
1032
1033 #ifdef CONFIG_DEBUG_PAGEALLOC
1034 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1035 {
1036 unsigned long hash, hpteg;
1037 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1038 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1039 unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY |
1040 _PAGE_COHERENT | PP_RWXX | HPTE_R_N;
1041 int ret;
1042
1043 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1044 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
1045
1046 ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
1047 mode, HPTE_V_BOLTED,
1048 mmu_linear_psize, mmu_kernel_ssize);
1049 BUG_ON (ret < 0);
1050 spin_lock(&linear_map_hash_lock);
1051 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1052 linear_map_hash_slots[lmi] = ret | 0x80;
1053 spin_unlock(&linear_map_hash_lock);
1054 }
1055
1056 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1057 {
1058 unsigned long hash, hidx, slot;
1059 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1060 unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
1061
1062 hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
1063 spin_lock(&linear_map_hash_lock);
1064 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1065 hidx = linear_map_hash_slots[lmi] & 0x7f;
1066 linear_map_hash_slots[lmi] = 0;
1067 spin_unlock(&linear_map_hash_lock);
1068 if (hidx & _PTEIDX_SECONDARY)
1069 hash = ~hash;
1070 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1071 slot += hidx & _PTEIDX_GROUP_IX;
1072 ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
1073 }
1074
1075 void kernel_map_pages(struct page *page, int numpages, int enable)
1076 {
1077 unsigned long flags, vaddr, lmi;
1078 int i;
1079
1080 local_irq_save(flags);
1081 for (i = 0; i < numpages; i++, page++) {
1082 vaddr = (unsigned long)page_address(page);
1083 lmi = __pa(vaddr) >> PAGE_SHIFT;
1084 if (lmi >= linear_map_hash_count)
1085 continue;
1086 if (enable)
1087 kernel_map_linear_page(vaddr, lmi);
1088 else
1089 kernel_unmap_linear_page(vaddr, lmi);
1090 }
1091 local_irq_restore(flags);
1092 }
1093 #endif /* CONFIG_DEBUG_PAGEALLOC */