2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
38 #include <asm/processor.h>
39 #include <asm/pgtable.h>
41 #include <asm/mmu_context.h>
43 #include <asm/types.h>
44 #include <asm/uaccess.h>
45 #include <asm/machdep.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/copro.h>
56 #include <asm/code-patching.h>
57 #include <asm/fadump.h>
58 #include <asm/firmware.h>
60 #include <asm/trace.h>
63 #define DBG(fmt...) udbg_printf(fmt)
69 #define DBG_LOW(fmt...) udbg_printf(fmt)
71 #define DBG_LOW(fmt...)
79 * Note: pte --> Linux PTE
80 * HPTE --> PowerPC Hashed Page Table Entry
83 * htab_initialize is called with the MMU off (of course), but
84 * the kernel has been copied down to zero so it can directly
85 * reference global data. At this point it is very difficult
86 * to print debug info.
91 extern unsigned long dart_tablebase
;
92 #endif /* CONFIG_U3_DART */
94 static unsigned long _SDR1
;
95 struct mmu_psize_def mmu_psize_defs
[MMU_PAGE_COUNT
];
96 EXPORT_SYMBOL_GPL(mmu_psize_defs
);
98 struct hash_pte
*htab_address
;
99 unsigned long htab_size_bytes
;
100 unsigned long htab_hash_mask
;
101 EXPORT_SYMBOL_GPL(htab_hash_mask
);
102 int mmu_linear_psize
= MMU_PAGE_4K
;
103 EXPORT_SYMBOL_GPL(mmu_linear_psize
);
104 int mmu_virtual_psize
= MMU_PAGE_4K
;
105 int mmu_vmalloc_psize
= MMU_PAGE_4K
;
106 #ifdef CONFIG_SPARSEMEM_VMEMMAP
107 int mmu_vmemmap_psize
= MMU_PAGE_4K
;
109 int mmu_io_psize
= MMU_PAGE_4K
;
110 int mmu_kernel_ssize
= MMU_SEGSIZE_256M
;
111 EXPORT_SYMBOL_GPL(mmu_kernel_ssize
);
112 int mmu_highuser_ssize
= MMU_SEGSIZE_256M
;
113 u16 mmu_slb_size
= 64;
114 EXPORT_SYMBOL_GPL(mmu_slb_size
);
115 #ifdef CONFIG_PPC_64K_PAGES
116 int mmu_ci_restrictions
;
118 #ifdef CONFIG_DEBUG_PAGEALLOC
119 static u8
*linear_map_hash_slots
;
120 static unsigned long linear_map_hash_count
;
121 static DEFINE_SPINLOCK(linear_map_hash_lock
);
122 #endif /* CONFIG_DEBUG_PAGEALLOC */
124 /* There are definitions of page sizes arrays to be used when none
125 * is provided by the firmware.
128 /* Pre-POWER4 CPUs (4k pages only)
130 static struct mmu_psize_def mmu_psize_defaults_old
[] = {
134 .penc
= {[MMU_PAGE_4K
] = 0, [1 ... MMU_PAGE_COUNT
- 1] = -1},
140 /* POWER4, GPUL, POWER5
142 * Support for 16Mb large pages
144 static struct mmu_psize_def mmu_psize_defaults_gp
[] = {
148 .penc
= {[MMU_PAGE_4K
] = 0, [1 ... MMU_PAGE_COUNT
- 1] = -1},
155 .penc
= {[0 ... MMU_PAGE_16M
- 1] = -1, [MMU_PAGE_16M
] = 0,
156 [MMU_PAGE_16M
+ 1 ... MMU_PAGE_COUNT
- 1] = -1 },
162 static unsigned long htab_convert_pte_flags(unsigned long pteflags
)
164 unsigned long rflags
= pteflags
& 0x1fa;
166 /* _PAGE_EXEC -> NOEXEC */
167 if ((pteflags
& _PAGE_EXEC
) == 0)
170 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
171 * need to add in 0x1 if it's a read-only user page
173 if ((pteflags
& _PAGE_USER
) && !((pteflags
& _PAGE_RW
) &&
174 (pteflags
& _PAGE_DIRTY
)))
177 * Always add "C" bit for perf. Memory coherence is always enabled
179 return rflags
| HPTE_R_C
| HPTE_R_M
;
182 int htab_bolt_mapping(unsigned long vstart
, unsigned long vend
,
183 unsigned long pstart
, unsigned long prot
,
184 int psize
, int ssize
)
186 unsigned long vaddr
, paddr
;
187 unsigned int step
, shift
;
190 shift
= mmu_psize_defs
[psize
].shift
;
193 prot
= htab_convert_pte_flags(prot
);
195 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
196 vstart
, vend
, pstart
, prot
, psize
, ssize
);
198 for (vaddr
= vstart
, paddr
= pstart
; vaddr
< vend
;
199 vaddr
+= step
, paddr
+= step
) {
200 unsigned long hash
, hpteg
;
201 unsigned long vsid
= get_kernel_vsid(vaddr
, ssize
);
202 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, ssize
);
203 unsigned long tprot
= prot
;
206 * If we hit a bad address return error.
210 /* Make kernel text executable */
211 if (overlaps_kernel_text(vaddr
, vaddr
+ step
))
214 /* Make kvm guest trampolines executable */
215 if (overlaps_kvm_tmp(vaddr
, vaddr
+ step
))
219 * If relocatable, check if it overlaps interrupt vectors that
220 * are copied down to real 0. For relocatable kernel
221 * (e.g. kdump case) we copy interrupt vectors down to real
222 * address 0. Mark that region as executable. This is
223 * because on p8 system with relocation on exception feature
224 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
225 * in order to execute the interrupt handlers in virtual
226 * mode the vector region need to be marked as executable.
228 if ((PHYSICAL_START
> MEMORY_START
) &&
229 overlaps_interrupt_vector_text(vaddr
, vaddr
+ step
))
232 hash
= hpt_hash(vpn
, shift
, ssize
);
233 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
235 BUG_ON(!ppc_md
.hpte_insert
);
236 ret
= ppc_md
.hpte_insert(hpteg
, vpn
, paddr
, tprot
,
237 HPTE_V_BOLTED
, psize
, psize
, ssize
);
241 #ifdef CONFIG_DEBUG_PAGEALLOC
242 if ((paddr
>> PAGE_SHIFT
) < linear_map_hash_count
)
243 linear_map_hash_slots
[paddr
>> PAGE_SHIFT
] = ret
| 0x80;
244 #endif /* CONFIG_DEBUG_PAGEALLOC */
246 return ret
< 0 ? ret
: 0;
249 #ifdef CONFIG_MEMORY_HOTPLUG
250 int htab_remove_mapping(unsigned long vstart
, unsigned long vend
,
251 int psize
, int ssize
)
254 unsigned int step
, shift
;
256 shift
= mmu_psize_defs
[psize
].shift
;
259 if (!ppc_md
.hpte_removebolted
) {
260 printk(KERN_WARNING
"Platform doesn't implement "
261 "hpte_removebolted\n");
265 for (vaddr
= vstart
; vaddr
< vend
; vaddr
+= step
)
266 ppc_md
.hpte_removebolted(vaddr
, psize
, ssize
);
270 #endif /* CONFIG_MEMORY_HOTPLUG */
272 static int __init
htab_dt_scan_seg_sizes(unsigned long node
,
273 const char *uname
, int depth
,
276 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
280 /* We are scanning "cpu" nodes only */
281 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
284 prop
= of_get_flat_dt_prop(node
, "ibm,processor-segment-sizes", &size
);
287 for (; size
>= 4; size
-= 4, ++prop
) {
288 if (be32_to_cpu(prop
[0]) == 40) {
289 DBG("1T segment support detected\n");
290 cur_cpu_spec
->mmu_features
|= MMU_FTR_1T_SEGMENT
;
294 cur_cpu_spec
->mmu_features
&= ~MMU_FTR_NO_SLBIE_B
;
298 static void __init
htab_init_seg_sizes(void)
300 of_scan_flat_dt(htab_dt_scan_seg_sizes
, NULL
);
303 static int __init
get_idx_from_shift(unsigned int shift
)
327 static int __init
htab_dt_scan_page_sizes(unsigned long node
,
328 const char *uname
, int depth
,
331 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
335 /* We are scanning "cpu" nodes only */
336 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
339 prop
= of_get_flat_dt_prop(node
, "ibm,segment-page-sizes", &size
);
343 pr_info("Page sizes from device-tree:\n");
345 cur_cpu_spec
->mmu_features
&= ~(MMU_FTR_16M_PAGE
);
347 unsigned int base_shift
= be32_to_cpu(prop
[0]);
348 unsigned int slbenc
= be32_to_cpu(prop
[1]);
349 unsigned int lpnum
= be32_to_cpu(prop
[2]);
350 struct mmu_psize_def
*def
;
353 size
-= 3; prop
+= 3;
354 base_idx
= get_idx_from_shift(base_shift
);
356 /* skip the pte encoding also */
357 prop
+= lpnum
* 2; size
-= lpnum
* 2;
360 def
= &mmu_psize_defs
[base_idx
];
361 if (base_idx
== MMU_PAGE_16M
)
362 cur_cpu_spec
->mmu_features
|= MMU_FTR_16M_PAGE
;
364 def
->shift
= base_shift
;
365 if (base_shift
<= 23)
368 def
->avpnm
= (1 << (base_shift
- 23)) - 1;
371 * We don't know for sure what's up with tlbiel, so
372 * for now we only set it for 4K and 64K pages
374 if (base_idx
== MMU_PAGE_4K
|| base_idx
== MMU_PAGE_64K
)
379 while (size
> 0 && lpnum
) {
380 unsigned int shift
= be32_to_cpu(prop
[0]);
381 int penc
= be32_to_cpu(prop
[1]);
383 prop
+= 2; size
-= 2;
386 idx
= get_idx_from_shift(shift
);
391 pr_err("Invalid penc for base_shift=%d "
392 "shift=%d\n", base_shift
, shift
);
394 def
->penc
[idx
] = penc
;
395 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
396 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
397 base_shift
, shift
, def
->sllp
,
398 def
->avpnm
, def
->tlbiel
, def
->penc
[idx
]);
405 #ifdef CONFIG_HUGETLB_PAGE
406 /* Scan for 16G memory blocks that have been set aside for huge pages
407 * and reserve those blocks for 16G huge pages.
409 static int __init
htab_dt_scan_hugepage_blocks(unsigned long node
,
410 const char *uname
, int depth
,
412 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
413 const __be64
*addr_prop
;
414 const __be32
*page_count_prop
;
415 unsigned int expected_pages
;
416 long unsigned int phys_addr
;
417 long unsigned int block_size
;
419 /* We are scanning "memory" nodes only */
420 if (type
== NULL
|| strcmp(type
, "memory") != 0)
423 /* This property is the log base 2 of the number of virtual pages that
424 * will represent this memory block. */
425 page_count_prop
= of_get_flat_dt_prop(node
, "ibm,expected#pages", NULL
);
426 if (page_count_prop
== NULL
)
428 expected_pages
= (1 << be32_to_cpu(page_count_prop
[0]));
429 addr_prop
= of_get_flat_dt_prop(node
, "reg", NULL
);
430 if (addr_prop
== NULL
)
432 phys_addr
= be64_to_cpu(addr_prop
[0]);
433 block_size
= be64_to_cpu(addr_prop
[1]);
434 if (block_size
!= (16 * GB
))
436 printk(KERN_INFO
"Huge page(16GB) memory: "
437 "addr = 0x%lX size = 0x%lX pages = %d\n",
438 phys_addr
, block_size
, expected_pages
);
439 if (phys_addr
+ (16 * GB
) <= memblock_end_of_DRAM()) {
440 memblock_reserve(phys_addr
, block_size
* expected_pages
);
441 add_gpage(phys_addr
, block_size
, expected_pages
);
445 #endif /* CONFIG_HUGETLB_PAGE */
447 static void mmu_psize_set_default_penc(void)
450 for (bpsize
= 0; bpsize
< MMU_PAGE_COUNT
; bpsize
++)
451 for (apsize
= 0; apsize
< MMU_PAGE_COUNT
; apsize
++)
452 mmu_psize_defs
[bpsize
].penc
[apsize
] = -1;
455 #ifdef CONFIG_PPC_64K_PAGES
457 static bool might_have_hea(void)
460 * The HEA ethernet adapter requires awareness of the
461 * GX bus. Without that awareness we can easily assume
462 * we will never see an HEA ethernet device.
464 #ifdef CONFIG_IBMEBUS
465 return !cpu_has_feature(CPU_FTR_ARCH_207S
);
471 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
473 static void __init
htab_init_page_sizes(void)
477 /* se the invalid penc to -1 */
478 mmu_psize_set_default_penc();
480 /* Default to 4K pages only */
481 memcpy(mmu_psize_defs
, mmu_psize_defaults_old
,
482 sizeof(mmu_psize_defaults_old
));
485 * Try to find the available page sizes in the device-tree
487 rc
= of_scan_flat_dt(htab_dt_scan_page_sizes
, NULL
);
488 if (rc
!= 0) /* Found */
492 * Not in the device-tree, let's fallback on known size
493 * list for 16M capable GP & GR
495 if (mmu_has_feature(MMU_FTR_16M_PAGE
))
496 memcpy(mmu_psize_defs
, mmu_psize_defaults_gp
,
497 sizeof(mmu_psize_defaults_gp
));
499 #ifndef CONFIG_DEBUG_PAGEALLOC
501 * Pick a size for the linear mapping. Currently, we only support
502 * 16M, 1M and 4K which is the default
504 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
505 mmu_linear_psize
= MMU_PAGE_16M
;
506 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
507 mmu_linear_psize
= MMU_PAGE_1M
;
508 #endif /* CONFIG_DEBUG_PAGEALLOC */
510 #ifdef CONFIG_PPC_64K_PAGES
512 * Pick a size for the ordinary pages. Default is 4K, we support
513 * 64K for user mappings and vmalloc if supported by the processor.
514 * We only use 64k for ioremap if the processor
515 * (and firmware) support cache-inhibited large pages.
516 * If not, we use 4k and set mmu_ci_restrictions so that
517 * hash_page knows to switch processes that use cache-inhibited
518 * mappings to 4k pages.
520 if (mmu_psize_defs
[MMU_PAGE_64K
].shift
) {
521 mmu_virtual_psize
= MMU_PAGE_64K
;
522 mmu_vmalloc_psize
= MMU_PAGE_64K
;
523 if (mmu_linear_psize
== MMU_PAGE_4K
)
524 mmu_linear_psize
= MMU_PAGE_64K
;
525 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE
)) {
527 * When running on pSeries using 64k pages for ioremap
528 * would stop us accessing the HEA ethernet. So if we
529 * have the chance of ever seeing one, stay at 4k.
531 if (!might_have_hea() || !machine_is(pseries
))
532 mmu_io_psize
= MMU_PAGE_64K
;
534 mmu_ci_restrictions
= 1;
536 #endif /* CONFIG_PPC_64K_PAGES */
538 #ifdef CONFIG_SPARSEMEM_VMEMMAP
539 /* We try to use 16M pages for vmemmap if that is supported
540 * and we have at least 1G of RAM at boot
542 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
&&
543 memblock_phys_mem_size() >= 0x40000000)
544 mmu_vmemmap_psize
= MMU_PAGE_16M
;
545 else if (mmu_psize_defs
[MMU_PAGE_64K
].shift
)
546 mmu_vmemmap_psize
= MMU_PAGE_64K
;
548 mmu_vmemmap_psize
= MMU_PAGE_4K
;
549 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
551 printk(KERN_DEBUG
"Page orders: linear mapping = %d, "
552 "virtual = %d, io = %d"
553 #ifdef CONFIG_SPARSEMEM_VMEMMAP
557 mmu_psize_defs
[mmu_linear_psize
].shift
,
558 mmu_psize_defs
[mmu_virtual_psize
].shift
,
559 mmu_psize_defs
[mmu_io_psize
].shift
560 #ifdef CONFIG_SPARSEMEM_VMEMMAP
561 ,mmu_psize_defs
[mmu_vmemmap_psize
].shift
565 #ifdef CONFIG_HUGETLB_PAGE
566 /* Reserve 16G huge page memory sections for huge pages */
567 of_scan_flat_dt(htab_dt_scan_hugepage_blocks
, NULL
);
568 #endif /* CONFIG_HUGETLB_PAGE */
571 static int __init
htab_dt_scan_pftsize(unsigned long node
,
572 const char *uname
, int depth
,
575 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
578 /* We are scanning "cpu" nodes only */
579 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
582 prop
= of_get_flat_dt_prop(node
, "ibm,pft-size", NULL
);
584 /* pft_size[0] is the NUMA CEC cookie */
585 ppc64_pft_size
= be32_to_cpu(prop
[1]);
591 static unsigned long __init
htab_get_table_size(void)
593 unsigned long mem_size
, rnd_mem_size
, pteg_count
, psize
;
595 /* If hash size isn't already provided by the platform, we try to
596 * retrieve it from the device-tree. If it's not there neither, we
597 * calculate it now based on the total RAM size
599 if (ppc64_pft_size
== 0)
600 of_scan_flat_dt(htab_dt_scan_pftsize
, NULL
);
602 return 1UL << ppc64_pft_size
;
604 /* round mem_size up to next power of 2 */
605 mem_size
= memblock_phys_mem_size();
606 rnd_mem_size
= 1UL << __ilog2(mem_size
);
607 if (rnd_mem_size
< mem_size
)
611 psize
= mmu_psize_defs
[mmu_virtual_psize
].shift
;
612 pteg_count
= max(rnd_mem_size
>> (psize
+ 1), 1UL << 11);
614 return pteg_count
<< 7;
617 #ifdef CONFIG_MEMORY_HOTPLUG
618 int create_section_mapping(unsigned long start
, unsigned long end
)
620 return htab_bolt_mapping(start
, end
, __pa(start
),
621 pgprot_val(PAGE_KERNEL
), mmu_linear_psize
,
625 int remove_section_mapping(unsigned long start
, unsigned long end
)
627 return htab_remove_mapping(start
, end
, mmu_linear_psize
,
630 #endif /* CONFIG_MEMORY_HOTPLUG */
632 extern u32 htab_call_hpte_insert1
[];
633 extern u32 htab_call_hpte_insert2
[];
634 extern u32 htab_call_hpte_remove
[];
635 extern u32 htab_call_hpte_updatepp
[];
636 extern u32 ht64_call_hpte_insert1
[];
637 extern u32 ht64_call_hpte_insert2
[];
638 extern u32 ht64_call_hpte_remove
[];
639 extern u32 ht64_call_hpte_updatepp
[];
641 static void __init
htab_finish_init(void)
643 #ifdef CONFIG_PPC_64K_PAGES
644 patch_branch(ht64_call_hpte_insert1
,
645 ppc_function_entry(ppc_md
.hpte_insert
),
647 patch_branch(ht64_call_hpte_insert2
,
648 ppc_function_entry(ppc_md
.hpte_insert
),
650 patch_branch(ht64_call_hpte_remove
,
651 ppc_function_entry(ppc_md
.hpte_remove
),
653 patch_branch(ht64_call_hpte_updatepp
,
654 ppc_function_entry(ppc_md
.hpte_updatepp
),
656 #else /* !CONFIG_PPC_64K_PAGES */
658 patch_branch(htab_call_hpte_insert1
,
659 ppc_function_entry(ppc_md
.hpte_insert
),
661 patch_branch(htab_call_hpte_insert2
,
662 ppc_function_entry(ppc_md
.hpte_insert
),
664 patch_branch(htab_call_hpte_remove
,
665 ppc_function_entry(ppc_md
.hpte_remove
),
667 patch_branch(htab_call_hpte_updatepp
,
668 ppc_function_entry(ppc_md
.hpte_updatepp
),
674 static void __init
htab_initialize(void)
677 unsigned long pteg_count
;
679 unsigned long base
= 0, size
= 0, limit
;
680 struct memblock_region
*reg
;
682 DBG(" -> htab_initialize()\n");
684 /* Initialize segment sizes */
685 htab_init_seg_sizes();
687 /* Initialize page sizes */
688 htab_init_page_sizes();
690 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
)) {
691 mmu_kernel_ssize
= MMU_SEGSIZE_1T
;
692 mmu_highuser_ssize
= MMU_SEGSIZE_1T
;
693 printk(KERN_INFO
"Using 1TB segments\n");
697 * Calculate the required size of the htab. We want the number of
698 * PTEGs to equal one half the number of real pages.
700 htab_size_bytes
= htab_get_table_size();
701 pteg_count
= htab_size_bytes
>> 7;
703 htab_hash_mask
= pteg_count
- 1;
705 if (firmware_has_feature(FW_FEATURE_LPAR
)) {
706 /* Using a hypervisor which owns the htab */
709 #ifdef CONFIG_FA_DUMP
711 * If firmware assisted dump is active firmware preserves
712 * the contents of htab along with entire partition memory.
713 * Clear the htab if firmware assisted dump is active so
714 * that we dont end up using old mappings.
716 if (is_fadump_active() && ppc_md
.hpte_clear_all
)
717 ppc_md
.hpte_clear_all();
720 /* Find storage for the HPT. Must be contiguous in
721 * the absolute address space. On cell we want it to be
722 * in the first 2 Gig so we can use it for IOMMU hacks.
724 if (machine_is(cell
))
727 limit
= MEMBLOCK_ALLOC_ANYWHERE
;
729 table
= memblock_alloc_base(htab_size_bytes
, htab_size_bytes
, limit
);
731 DBG("Hash table allocated at %lx, size: %lx\n", table
,
734 htab_address
= __va(table
);
736 /* htab absolute addr + encoded htabsize */
737 _SDR1
= table
+ __ilog2(pteg_count
) - 11;
739 /* Initialize the HPT with no entries */
740 memset((void *)table
, 0, htab_size_bytes
);
743 mtspr(SPRN_SDR1
, _SDR1
);
746 prot
= pgprot_val(PAGE_KERNEL
);
748 #ifdef CONFIG_DEBUG_PAGEALLOC
749 linear_map_hash_count
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
750 linear_map_hash_slots
= __va(memblock_alloc_base(linear_map_hash_count
,
752 memset(linear_map_hash_slots
, 0, linear_map_hash_count
);
753 #endif /* CONFIG_DEBUG_PAGEALLOC */
755 /* On U3 based machines, we need to reserve the DART area and
756 * _NOT_ map it to avoid cache paradoxes as it's remapped non
760 /* create bolted the linear mapping in the hash table */
761 for_each_memblock(memory
, reg
) {
762 base
= (unsigned long)__va(reg
->base
);
765 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
768 #ifdef CONFIG_U3_DART
769 /* Do not map the DART space. Fortunately, it will be aligned
770 * in such a way that it will not cross two memblock regions and
771 * will fit within a single 16Mb page.
772 * The DART space is assumed to be a full 16Mb region even if
773 * we only use 2Mb of that space. We will use more of it later
774 * for AGP GART. We have to use a full 16Mb large page.
776 DBG("DART base: %lx\n", dart_tablebase
);
778 if (dart_tablebase
!= 0 && dart_tablebase
>= base
779 && dart_tablebase
< (base
+ size
)) {
780 unsigned long dart_table_end
= dart_tablebase
+ 16 * MB
;
781 if (base
!= dart_tablebase
)
782 BUG_ON(htab_bolt_mapping(base
, dart_tablebase
,
786 if ((base
+ size
) > dart_table_end
)
787 BUG_ON(htab_bolt_mapping(dart_tablebase
+16*MB
,
789 __pa(dart_table_end
),
795 #endif /* CONFIG_U3_DART */
796 BUG_ON(htab_bolt_mapping(base
, base
+ size
, __pa(base
),
797 prot
, mmu_linear_psize
, mmu_kernel_ssize
));
799 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE
);
802 * If we have a memory_limit and we've allocated TCEs then we need to
803 * explicitly map the TCE area at the top of RAM. We also cope with the
804 * case that the TCEs start below memory_limit.
805 * tce_alloc_start/end are 16MB aligned so the mapping should work
806 * for either 4K or 16MB pages.
808 if (tce_alloc_start
) {
809 tce_alloc_start
= (unsigned long)__va(tce_alloc_start
);
810 tce_alloc_end
= (unsigned long)__va(tce_alloc_end
);
812 if (base
+ size
>= tce_alloc_start
)
813 tce_alloc_start
= base
+ size
+ 1;
815 BUG_ON(htab_bolt_mapping(tce_alloc_start
, tce_alloc_end
,
816 __pa(tce_alloc_start
), prot
,
817 mmu_linear_psize
, mmu_kernel_ssize
));
822 DBG(" <- htab_initialize()\n");
827 void __init
early_init_mmu(void)
829 /* Initialize the MMU Hash table and create the linear mapping
830 * of memory. Has to be done before SLB initialization as this is
831 * currently where the page size encoding is obtained.
835 /* Initialize SLB management */
840 void early_init_mmu_secondary(void)
842 /* Initialize hash table for that CPU */
843 if (!firmware_has_feature(FW_FEATURE_LPAR
))
844 mtspr(SPRN_SDR1
, _SDR1
);
849 #endif /* CONFIG_SMP */
852 * Called by asm hashtable.S for doing lazy icache flush
854 unsigned int hash_page_do_lazy_icache(unsigned int pp
, pte_t pte
, int trap
)
858 if (!pfn_valid(pte_pfn(pte
)))
861 page
= pte_page(pte
);
864 if (!test_bit(PG_arch_1
, &page
->flags
) && !PageReserved(page
)) {
866 flush_dcache_icache_page(page
);
867 set_bit(PG_arch_1
, &page
->flags
);
874 #ifdef CONFIG_PPC_MM_SLICES
875 static unsigned int get_paca_psize(unsigned long addr
)
878 unsigned char *hpsizes
;
879 unsigned long index
, mask_index
;
881 if (addr
< SLICE_LOW_TOP
) {
882 lpsizes
= get_paca()->context
.low_slices_psize
;
883 index
= GET_LOW_SLICE_INDEX(addr
);
884 return (lpsizes
>> (index
* 4)) & 0xF;
886 hpsizes
= get_paca()->context
.high_slices_psize
;
887 index
= GET_HIGH_SLICE_INDEX(addr
);
888 mask_index
= index
& 0x1;
889 return (hpsizes
[index
>> 1] >> (mask_index
* 4)) & 0xF;
893 unsigned int get_paca_psize(unsigned long addr
)
895 return get_paca()->context
.user_psize
;
900 * Demote a segment to using 4k pages.
901 * For now this makes the whole process use 4k pages.
903 #ifdef CONFIG_PPC_64K_PAGES
904 void demote_segment_4k(struct mm_struct
*mm
, unsigned long addr
)
906 if (get_slice_psize(mm
, addr
) == MMU_PAGE_4K
)
908 slice_set_range_psize(mm
, addr
, 1, MMU_PAGE_4K
);
909 copro_flush_all_slbs(mm
);
910 if ((get_paca_psize(addr
) != MMU_PAGE_4K
) && (current
->mm
== mm
)) {
911 get_paca()->context
= mm
->context
;
912 slb_flush_and_rebolt();
915 #endif /* CONFIG_PPC_64K_PAGES */
917 #ifdef CONFIG_PPC_SUBPAGE_PROT
919 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
920 * Userspace sets the subpage permissions using the subpage_prot system call.
922 * Result is 0: full permissions, _PAGE_RW: read-only,
923 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
925 static int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
927 struct subpage_prot_table
*spt
= &mm
->context
.spt
;
931 if (ea
>= spt
->maxaddr
)
933 if (ea
< 0x100000000UL
) {
934 /* addresses below 4GB use spt->low_prot */
935 sbpm
= spt
->low_prot
;
937 sbpm
= spt
->protptrs
[ea
>> SBP_L3_SHIFT
];
941 sbpp
= sbpm
[(ea
>> SBP_L2_SHIFT
) & (SBP_L2_COUNT
- 1)];
944 spp
= sbpp
[(ea
>> PAGE_SHIFT
) & (SBP_L1_COUNT
- 1)];
946 /* extract 2-bit bitfield for this 4k subpage */
947 spp
>>= 30 - 2 * ((ea
>> 12) & 0xf);
949 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
950 spp
= ((spp
& 2) ? _PAGE_USER
: 0) | ((spp
& 1) ? _PAGE_RW
: 0);
954 #else /* CONFIG_PPC_SUBPAGE_PROT */
955 static inline int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
961 void hash_failure_debug(unsigned long ea
, unsigned long access
,
962 unsigned long vsid
, unsigned long trap
,
963 int ssize
, int psize
, int lpsize
, unsigned long pte
)
965 if (!printk_ratelimit())
967 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
968 ea
, access
, current
->comm
);
969 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
970 trap
, vsid
, ssize
, psize
, lpsize
, pte
);
973 static void check_paca_psize(unsigned long ea
, struct mm_struct
*mm
,
974 int psize
, bool user_region
)
977 if (psize
!= get_paca_psize(ea
)) {
978 get_paca()->context
= mm
->context
;
979 slb_flush_and_rebolt();
981 } else if (get_paca()->vmalloc_sllp
!=
982 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
) {
983 get_paca()->vmalloc_sllp
=
984 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
;
985 slb_vmalloc_update();
991 * 1 - normal page fault
992 * -1 - critical hash insertion error
993 * -2 - access not permitted by subpage protection mechanism
995 int hash_page_mm(struct mm_struct
*mm
, unsigned long ea
,
996 unsigned long access
, unsigned long trap
,
1000 enum ctx_state prev_state
= exception_enter();
1005 const struct cpumask
*tmp
;
1006 int rc
, user_region
= 0;
1009 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1011 trace_hash_fault(ea
, access
, trap
);
1013 /* Get region & vsid */
1014 switch (REGION_ID(ea
)) {
1015 case USER_REGION_ID
:
1018 DBG_LOW(" user region with no mm !\n");
1022 psize
= get_slice_psize(mm
, ea
);
1023 ssize
= user_segment_size(ea
);
1024 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
1026 case VMALLOC_REGION_ID
:
1027 vsid
= get_kernel_vsid(ea
, mmu_kernel_ssize
);
1028 if (ea
< VMALLOC_END
)
1029 psize
= mmu_vmalloc_psize
;
1031 psize
= mmu_io_psize
;
1032 ssize
= mmu_kernel_ssize
;
1035 /* Not a valid range
1036 * Send the problem up to do_page_fault
1041 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm
, mm
->pgd
, vsid
);
1045 DBG_LOW("Bad address!\n");
1051 if (pgdir
== NULL
) {
1056 /* Check CPU locality */
1057 tmp
= cpumask_of(smp_processor_id());
1058 if (user_region
&& cpumask_equal(mm_cpumask(mm
), tmp
))
1059 flags
|= HPTE_LOCAL_UPDATE
;
1061 #ifndef CONFIG_PPC_64K_PAGES
1062 /* If we use 4K pages and our psize is not 4K, then we might
1063 * be hitting a special driver mapping, and need to align the
1064 * address before we fetch the PTE.
1066 * It could also be a hugepage mapping, in which case this is
1067 * not necessary, but it's not harmful, either.
1069 if (psize
!= MMU_PAGE_4K
)
1070 ea
&= ~((1ul << mmu_psize_defs
[psize
].shift
) - 1);
1071 #endif /* CONFIG_PPC_64K_PAGES */
1073 /* Get PTE and page size from page tables */
1074 ptep
= __find_linux_pte_or_hugepte(pgdir
, ea
, &is_thp
, &hugeshift
);
1075 if (ptep
== NULL
|| !pte_present(*ptep
)) {
1076 DBG_LOW(" no PTE !\n");
1081 /* Add _PAGE_PRESENT to the required access perm */
1082 access
|= _PAGE_PRESENT
;
1084 /* Pre-check access permissions (will be re-checked atomically
1085 * in __hash_page_XX but this pre-check is a fast path
1087 if (access
& ~pte_val(*ptep
)) {
1088 DBG_LOW(" no access !\n");
1095 rc
= __hash_page_thp(ea
, access
, vsid
, (pmd_t
*)ptep
,
1096 trap
, flags
, ssize
, psize
);
1097 #ifdef CONFIG_HUGETLB_PAGE
1099 rc
= __hash_page_huge(ea
, access
, vsid
, ptep
, trap
,
1100 flags
, ssize
, hugeshift
, psize
);
1104 * if we have hugeshift, and is not transhuge with
1105 * hugetlb disabled, something is really wrong.
1111 if (current
->mm
== mm
)
1112 check_paca_psize(ea
, mm
, psize
, user_region
);
1117 #ifndef CONFIG_PPC_64K_PAGES
1118 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep
));
1120 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep
),
1121 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1123 /* Do actual hashing */
1124 #ifdef CONFIG_PPC_64K_PAGES
1125 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1126 if ((pte_val(*ptep
) & _PAGE_4K_PFN
) && psize
== MMU_PAGE_64K
) {
1127 demote_segment_4k(mm
, ea
);
1128 psize
= MMU_PAGE_4K
;
1131 /* If this PTE is non-cacheable and we have restrictions on
1132 * using non cacheable large pages, then we switch to 4k
1134 if (mmu_ci_restrictions
&& psize
== MMU_PAGE_64K
&&
1135 (pte_val(*ptep
) & _PAGE_NO_CACHE
)) {
1137 demote_segment_4k(mm
, ea
);
1138 psize
= MMU_PAGE_4K
;
1139 } else if (ea
< VMALLOC_END
) {
1141 * some driver did a non-cacheable mapping
1142 * in vmalloc space, so switch vmalloc
1145 printk(KERN_ALERT
"Reducing vmalloc segment "
1146 "to 4kB pages because of "
1147 "non-cacheable mapping\n");
1148 psize
= mmu_vmalloc_psize
= MMU_PAGE_4K
;
1149 copro_flush_all_slbs(mm
);
1153 #endif /* CONFIG_PPC_64K_PAGES */
1155 if (current
->mm
== mm
)
1156 check_paca_psize(ea
, mm
, psize
, user_region
);
1158 #ifdef CONFIG_PPC_64K_PAGES
1159 if (psize
== MMU_PAGE_64K
)
1160 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
,
1163 #endif /* CONFIG_PPC_64K_PAGES */
1165 int spp
= subpage_protection(mm
, ea
);
1169 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
,
1173 /* Dump some info in case of hash insertion failure, they should
1174 * never happen so it is really useful to know if/when they do
1177 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
, psize
,
1178 psize
, pte_val(*ptep
));
1179 #ifndef CONFIG_PPC_64K_PAGES
1180 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep
));
1182 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep
),
1183 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1185 DBG_LOW(" -> rc=%d\n", rc
);
1188 exception_exit(prev_state
);
1191 EXPORT_SYMBOL_GPL(hash_page_mm
);
1193 int hash_page(unsigned long ea
, unsigned long access
, unsigned long trap
,
1194 unsigned long dsisr
)
1196 unsigned long flags
= 0;
1197 struct mm_struct
*mm
= current
->mm
;
1199 if (REGION_ID(ea
) == VMALLOC_REGION_ID
)
1202 if (dsisr
& DSISR_NOHPTE
)
1203 flags
|= HPTE_NOHPTE_UPDATE
;
1205 return hash_page_mm(mm
, ea
, access
, trap
, flags
);
1207 EXPORT_SYMBOL_GPL(hash_page
);
1209 int __hash_page(unsigned long ea
, unsigned long msr
, unsigned long trap
,
1210 unsigned long dsisr
)
1212 unsigned long access
= _PAGE_PRESENT
;
1213 unsigned long flags
= 0;
1214 struct mm_struct
*mm
= current
->mm
;
1216 if (REGION_ID(ea
) == VMALLOC_REGION_ID
)
1219 if (dsisr
& DSISR_NOHPTE
)
1220 flags
|= HPTE_NOHPTE_UPDATE
;
1222 if (dsisr
& DSISR_ISSTORE
)
1225 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1226 * accessing a userspace segment (even from the kernel). We assume
1227 * kernel addresses always have the high bit set.
1229 if ((msr
& MSR_PR
) || (REGION_ID(ea
) == USER_REGION_ID
))
1230 access
|= _PAGE_USER
;
1233 access
|= _PAGE_EXEC
;
1235 return hash_page_mm(mm
, ea
, access
, trap
, flags
);
1238 void hash_preload(struct mm_struct
*mm
, unsigned long ea
,
1239 unsigned long access
, unsigned long trap
)
1245 unsigned long flags
;
1246 int rc
, ssize
, update_flags
= 0;
1248 BUG_ON(REGION_ID(ea
) != USER_REGION_ID
);
1250 #ifdef CONFIG_PPC_MM_SLICES
1251 /* We only prefault standard pages for now */
1252 if (unlikely(get_slice_psize(mm
, ea
) != mm
->context
.user_psize
))
1256 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1257 " trap=%lx\n", mm
, mm
->pgd
, ea
, access
, trap
);
1259 /* Get Linux PTE if available */
1265 ssize
= user_segment_size(ea
);
1266 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
1270 * Hash doesn't like irqs. Walking linux page table with irq disabled
1271 * saves us from holding multiple locks.
1273 local_irq_save(flags
);
1276 * THP pages use update_mmu_cache_pmd. We don't do
1277 * hash preload there. Hence can ignore THP here
1279 ptep
= find_linux_pte_or_hugepte(pgdir
, ea
, NULL
, &hugepage_shift
);
1283 WARN_ON(hugepage_shift
);
1284 #ifdef CONFIG_PPC_64K_PAGES
1285 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1286 * a 64K kernel), then we don't preload, hash_page() will take
1287 * care of it once we actually try to access the page.
1288 * That way we don't have to duplicate all of the logic for segment
1289 * page size demotion here
1291 if (pte_val(*ptep
) & (_PAGE_4K_PFN
| _PAGE_NO_CACHE
))
1293 #endif /* CONFIG_PPC_64K_PAGES */
1295 /* Is that local to this CPU ? */
1296 if (cpumask_equal(mm_cpumask(mm
), cpumask_of(smp_processor_id())))
1297 update_flags
|= HPTE_LOCAL_UPDATE
;
1300 #ifdef CONFIG_PPC_64K_PAGES
1301 if (mm
->context
.user_psize
== MMU_PAGE_64K
)
1302 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
,
1303 update_flags
, ssize
);
1305 #endif /* CONFIG_PPC_64K_PAGES */
1306 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, update_flags
,
1307 ssize
, subpage_protection(mm
, ea
));
1309 /* Dump some info in case of hash insertion failure, they should
1310 * never happen so it is really useful to know if/when they do
1313 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
,
1314 mm
->context
.user_psize
,
1315 mm
->context
.user_psize
,
1318 local_irq_restore(flags
);
1321 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1322 * do not forget to update the assembly call site !
1324 void flush_hash_page(unsigned long vpn
, real_pte_t pte
, int psize
, int ssize
,
1325 unsigned long flags
)
1327 unsigned long hash
, index
, shift
, hidx
, slot
;
1328 int local
= flags
& HPTE_LOCAL_UPDATE
;
1330 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn
);
1331 pte_iterate_hashed_subpages(pte
, psize
, vpn
, index
, shift
) {
1332 hash
= hpt_hash(vpn
, shift
, ssize
);
1333 hidx
= __rpte_to_hidx(pte
, index
);
1334 if (hidx
& _PTEIDX_SECONDARY
)
1336 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1337 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1338 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index
, slot
, hidx
);
1340 * We use same base page size and actual psize, because we don't
1341 * use these functions for hugepage
1343 ppc_md
.hpte_invalidate(slot
, vpn
, psize
, psize
, ssize
, local
);
1344 } pte_iterate_hashed_end();
1346 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1347 /* Transactions are not aborted by tlbiel, only tlbie.
1348 * Without, syncing a page back to a block device w/ PIO could pick up
1349 * transactional data (bad!) so we force an abort here. Before the
1350 * sync the page will be made read-only, which will flush_hash_page.
1351 * BIG ISSUE here: if the kernel uses a page from userspace without
1352 * unmapping it first, it may see the speculated version.
1354 if (local
&& cpu_has_feature(CPU_FTR_TM
) &&
1355 current
->thread
.regs
&&
1356 MSR_TM_ACTIVE(current
->thread
.regs
->msr
)) {
1358 tm_abort(TM_CAUSE_TLBI
);
1363 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1364 void flush_hash_hugepage(unsigned long vsid
, unsigned long addr
,
1365 pmd_t
*pmdp
, unsigned int psize
, int ssize
,
1366 unsigned long flags
)
1368 int i
, max_hpte_count
, valid
;
1369 unsigned long s_addr
;
1370 unsigned char *hpte_slot_array
;
1371 unsigned long hidx
, shift
, vpn
, hash
, slot
;
1372 int local
= flags
& HPTE_LOCAL_UPDATE
;
1374 s_addr
= addr
& HPAGE_PMD_MASK
;
1375 hpte_slot_array
= get_hpte_slot_array(pmdp
);
1377 * IF we try to do a HUGE PTE update after a withdraw is done.
1378 * we will find the below NULL. This happens when we do
1379 * split_huge_page_pmd
1381 if (!hpte_slot_array
)
1384 if (ppc_md
.hugepage_invalidate
) {
1385 ppc_md
.hugepage_invalidate(vsid
, s_addr
, hpte_slot_array
,
1386 psize
, ssize
, local
);
1390 * No bluk hpte removal support, invalidate each entry
1392 shift
= mmu_psize_defs
[psize
].shift
;
1393 max_hpte_count
= HPAGE_PMD_SIZE
>> shift
;
1394 for (i
= 0; i
< max_hpte_count
; i
++) {
1396 * 8 bits per each hpte entries
1397 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1399 valid
= hpte_valid(hpte_slot_array
, i
);
1402 hidx
= hpte_hash_index(hpte_slot_array
, i
);
1405 addr
= s_addr
+ (i
* (1ul << shift
));
1406 vpn
= hpt_vpn(addr
, vsid
, ssize
);
1407 hash
= hpt_hash(vpn
, shift
, ssize
);
1408 if (hidx
& _PTEIDX_SECONDARY
)
1411 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1412 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1413 ppc_md
.hpte_invalidate(slot
, vpn
, psize
,
1414 MMU_PAGE_16M
, ssize
, local
);
1417 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1418 /* Transactions are not aborted by tlbiel, only tlbie.
1419 * Without, syncing a page back to a block device w/ PIO could pick up
1420 * transactional data (bad!) so we force an abort here. Before the
1421 * sync the page will be made read-only, which will flush_hash_page.
1422 * BIG ISSUE here: if the kernel uses a page from userspace without
1423 * unmapping it first, it may see the speculated version.
1425 if (local
&& cpu_has_feature(CPU_FTR_TM
) &&
1426 current
->thread
.regs
&&
1427 MSR_TM_ACTIVE(current
->thread
.regs
->msr
)) {
1429 tm_abort(TM_CAUSE_TLBI
);
1434 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1436 void flush_hash_range(unsigned long number
, int local
)
1438 if (ppc_md
.flush_hash_range
)
1439 ppc_md
.flush_hash_range(number
, local
);
1442 struct ppc64_tlb_batch
*batch
=
1443 this_cpu_ptr(&ppc64_tlb_batch
);
1445 for (i
= 0; i
< number
; i
++)
1446 flush_hash_page(batch
->vpn
[i
], batch
->pte
[i
],
1447 batch
->psize
, batch
->ssize
, local
);
1452 * low_hash_fault is called when we the low level hash code failed
1453 * to instert a PTE due to an hypervisor error
1455 void low_hash_fault(struct pt_regs
*regs
, unsigned long address
, int rc
)
1457 enum ctx_state prev_state
= exception_enter();
1459 if (user_mode(regs
)) {
1460 #ifdef CONFIG_PPC_SUBPAGE_PROT
1462 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, address
);
1465 _exception(SIGBUS
, regs
, BUS_ADRERR
, address
);
1467 bad_page_fault(regs
, address
, SIGBUS
);
1469 exception_exit(prev_state
);
1472 long hpte_insert_repeating(unsigned long hash
, unsigned long vpn
,
1473 unsigned long pa
, unsigned long rflags
,
1474 unsigned long vflags
, int psize
, int ssize
)
1476 unsigned long hpte_group
;
1480 hpte_group
= ((hash
& htab_hash_mask
) *
1481 HPTES_PER_GROUP
) & ~0x7UL
;
1483 /* Insert into the hash table, primary slot */
1484 slot
= ppc_md
.hpte_insert(hpte_group
, vpn
, pa
, rflags
, vflags
,
1485 psize
, psize
, ssize
);
1487 /* Primary is full, try the secondary */
1488 if (unlikely(slot
== -1)) {
1489 hpte_group
= ((~hash
& htab_hash_mask
) *
1490 HPTES_PER_GROUP
) & ~0x7UL
;
1491 slot
= ppc_md
.hpte_insert(hpte_group
, vpn
, pa
, rflags
,
1492 vflags
| HPTE_V_SECONDARY
,
1493 psize
, psize
, ssize
);
1496 hpte_group
= ((hash
& htab_hash_mask
) *
1497 HPTES_PER_GROUP
)&~0x7UL
;
1499 ppc_md
.hpte_remove(hpte_group
);
1507 #ifdef CONFIG_DEBUG_PAGEALLOC
1508 static void kernel_map_linear_page(unsigned long vaddr
, unsigned long lmi
)
1511 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1512 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, mmu_kernel_ssize
);
1513 unsigned long mode
= htab_convert_pte_flags(pgprot_val(PAGE_KERNEL
));
1516 hash
= hpt_hash(vpn
, PAGE_SHIFT
, mmu_kernel_ssize
);
1518 /* Don't create HPTE entries for bad address */
1522 ret
= hpte_insert_repeating(hash
, vpn
, __pa(vaddr
), mode
,
1524 mmu_linear_psize
, mmu_kernel_ssize
);
1527 spin_lock(&linear_map_hash_lock
);
1528 BUG_ON(linear_map_hash_slots
[lmi
] & 0x80);
1529 linear_map_hash_slots
[lmi
] = ret
| 0x80;
1530 spin_unlock(&linear_map_hash_lock
);
1533 static void kernel_unmap_linear_page(unsigned long vaddr
, unsigned long lmi
)
1535 unsigned long hash
, hidx
, slot
;
1536 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1537 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, mmu_kernel_ssize
);
1539 hash
= hpt_hash(vpn
, PAGE_SHIFT
, mmu_kernel_ssize
);
1540 spin_lock(&linear_map_hash_lock
);
1541 BUG_ON(!(linear_map_hash_slots
[lmi
] & 0x80));
1542 hidx
= linear_map_hash_slots
[lmi
] & 0x7f;
1543 linear_map_hash_slots
[lmi
] = 0;
1544 spin_unlock(&linear_map_hash_lock
);
1545 if (hidx
& _PTEIDX_SECONDARY
)
1547 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1548 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1549 ppc_md
.hpte_invalidate(slot
, vpn
, mmu_linear_psize
, mmu_linear_psize
,
1550 mmu_kernel_ssize
, 0);
1553 void __kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1555 unsigned long flags
, vaddr
, lmi
;
1558 local_irq_save(flags
);
1559 for (i
= 0; i
< numpages
; i
++, page
++) {
1560 vaddr
= (unsigned long)page_address(page
);
1561 lmi
= __pa(vaddr
) >> PAGE_SHIFT
;
1562 if (lmi
>= linear_map_hash_count
)
1565 kernel_map_linear_page(vaddr
, lmi
);
1567 kernel_unmap_linear_page(vaddr
, lmi
);
1569 local_irq_restore(flags
);
1571 #endif /* CONFIG_DEBUG_PAGEALLOC */
1573 void setup_initial_memory_limit(phys_addr_t first_memblock_base
,
1574 phys_addr_t first_memblock_size
)
1576 /* We don't currently support the first MEMBLOCK not mapping 0
1577 * physical on those processors
1579 BUG_ON(first_memblock_base
!= 0);
1581 /* On LPAR systems, the first entry is our RMA region,
1582 * non-LPAR 64-bit hash MMU systems don't have a limitation
1583 * on real mode access, but using the first entry works well
1584 * enough. We also clamp it to 1G to avoid some funky things
1585 * such as RTAS bugs etc...
1587 ppc64_rma_size
= min_t(u64
, first_memblock_size
, 0x40000000);
1589 /* Finally limit subsequent allocations */
1590 memblock_set_current_limit(ppc64_rma_size
);