2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/ctype.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/signal.h>
35 #include <asm/processor.h>
36 #include <asm/pgtable.h>
38 #include <asm/mmu_context.h>
40 #include <asm/types.h>
41 #include <asm/system.h>
42 #include <asm/uaccess.h>
43 #include <asm/machdep.h>
45 #include <asm/abs_addr.h>
46 #include <asm/tlbflush.h>
50 #include <asm/cacheflush.h>
51 #include <asm/cputable.h>
52 #include <asm/abs_addr.h>
53 #include <asm/sections.h>
57 #define DBG(fmt...) udbg_printf(fmt)
63 #define DBG_LOW(fmt...) udbg_printf(fmt)
65 #define DBG_LOW(fmt...)
72 * Note: pte --> Linux PTE
73 * HPTE --> PowerPC Hashed Page Table Entry
76 * htab_initialize is called with the MMU off (of course), but
77 * the kernel has been copied down to zero so it can directly
78 * reference global data. At this point it is very difficult
79 * to print debug info.
84 extern unsigned long dart_tablebase
;
85 #endif /* CONFIG_U3_DART */
87 static unsigned long _SDR1
;
88 struct mmu_psize_def mmu_psize_defs
[MMU_PAGE_COUNT
];
90 struct hash_pte
*htab_address
;
91 unsigned long htab_size_bytes
;
92 unsigned long htab_hash_mask
;
93 int mmu_linear_psize
= MMU_PAGE_4K
;
94 int mmu_virtual_psize
= MMU_PAGE_4K
;
95 int mmu_vmalloc_psize
= MMU_PAGE_4K
;
96 int mmu_io_psize
= MMU_PAGE_4K
;
97 #ifdef CONFIG_HUGETLB_PAGE
98 int mmu_huge_psize
= MMU_PAGE_16M
;
99 unsigned int HPAGE_SHIFT
;
101 #ifdef CONFIG_PPC_64K_PAGES
102 int mmu_ci_restrictions
;
104 #ifdef CONFIG_DEBUG_PAGEALLOC
105 static u8
*linear_map_hash_slots
;
106 static unsigned long linear_map_hash_count
;
107 static DEFINE_SPINLOCK(linear_map_hash_lock
);
108 #endif /* CONFIG_DEBUG_PAGEALLOC */
110 /* There are definitions of page sizes arrays to be used when none
111 * is provided by the firmware.
114 /* Pre-POWER4 CPUs (4k pages only)
116 struct mmu_psize_def mmu_psize_defaults_old
[] = {
126 /* POWER4, GPUL, POWER5
128 * Support for 16Mb large pages
130 struct mmu_psize_def mmu_psize_defaults_gp
[] = {
148 int htab_bolt_mapping(unsigned long vstart
, unsigned long vend
,
149 unsigned long pstart
, unsigned long mode
, int psize
)
151 unsigned long vaddr
, paddr
;
152 unsigned int step
, shift
;
153 unsigned long tmp_mode
;
156 shift
= mmu_psize_defs
[psize
].shift
;
159 for (vaddr
= vstart
, paddr
= pstart
; vaddr
< vend
;
160 vaddr
+= step
, paddr
+= step
) {
161 unsigned long hash
, hpteg
;
162 unsigned long vsid
= get_kernel_vsid(vaddr
);
163 unsigned long va
= (vsid
<< 28) | (vaddr
& 0x0fffffff);
167 /* Make non-kernel text non-executable */
168 if (!in_kernel_text(vaddr
))
169 tmp_mode
= mode
| HPTE_R_N
;
171 hash
= hpt_hash(va
, shift
);
172 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
174 DBG("htab_bolt_mapping: calling %p\n", ppc_md
.hpte_insert
);
176 BUG_ON(!ppc_md
.hpte_insert
);
177 ret
= ppc_md
.hpte_insert(hpteg
, va
, paddr
,
178 tmp_mode
, HPTE_V_BOLTED
, psize
);
182 #ifdef CONFIG_DEBUG_PAGEALLOC
183 if ((paddr
>> PAGE_SHIFT
) < linear_map_hash_count
)
184 linear_map_hash_slots
[paddr
>> PAGE_SHIFT
] = ret
| 0x80;
185 #endif /* CONFIG_DEBUG_PAGEALLOC */
187 return ret
< 0 ? ret
: 0;
190 static int __init
htab_dt_scan_page_sizes(unsigned long node
,
191 const char *uname
, int depth
,
194 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
196 unsigned long size
= 0;
198 /* We are scanning "cpu" nodes only */
199 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
202 prop
= (u32
*)of_get_flat_dt_prop(node
,
203 "ibm,segment-page-sizes", &size
);
205 DBG("Page sizes from device-tree:\n");
207 cur_cpu_spec
->cpu_features
&= ~(CPU_FTR_16M_PAGE
);
209 unsigned int shift
= prop
[0];
210 unsigned int slbenc
= prop
[1];
211 unsigned int lpnum
= prop
[2];
212 unsigned int lpenc
= 0;
213 struct mmu_psize_def
*def
;
216 size
-= 3; prop
+= 3;
217 while(size
> 0 && lpnum
) {
218 if (prop
[0] == shift
)
220 prop
+= 2; size
-= 2;
235 cur_cpu_spec
->cpu_features
|= CPU_FTR_16M_PAGE
;
243 def
= &mmu_psize_defs
[idx
];
248 def
->avpnm
= (1 << (shift
- 23)) - 1;
251 /* We don't know for sure what's up with tlbiel, so
252 * for now we only set it for 4K and 64K pages
254 if (idx
== MMU_PAGE_4K
|| idx
== MMU_PAGE_64K
)
259 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
260 "tlbiel=%d, penc=%d\n",
261 idx
, shift
, def
->sllp
, def
->avpnm
, def
->tlbiel
,
270 static void __init
htab_init_page_sizes(void)
274 /* Default to 4K pages only */
275 memcpy(mmu_psize_defs
, mmu_psize_defaults_old
,
276 sizeof(mmu_psize_defaults_old
));
279 * Try to find the available page sizes in the device-tree
281 rc
= of_scan_flat_dt(htab_dt_scan_page_sizes
, NULL
);
282 if (rc
!= 0) /* Found */
286 * Not in the device-tree, let's fallback on known size
287 * list for 16M capable GP & GR
289 if (cpu_has_feature(CPU_FTR_16M_PAGE
))
290 memcpy(mmu_psize_defs
, mmu_psize_defaults_gp
,
291 sizeof(mmu_psize_defaults_gp
));
293 #ifndef CONFIG_DEBUG_PAGEALLOC
295 * Pick a size for the linear mapping. Currently, we only support
296 * 16M, 1M and 4K which is the default
298 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
299 mmu_linear_psize
= MMU_PAGE_16M
;
300 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
301 mmu_linear_psize
= MMU_PAGE_1M
;
302 #endif /* CONFIG_DEBUG_PAGEALLOC */
304 #ifdef CONFIG_PPC_64K_PAGES
306 * Pick a size for the ordinary pages. Default is 4K, we support
307 * 64K for user mappings and vmalloc if supported by the processor.
308 * We only use 64k for ioremap if the processor
309 * (and firmware) support cache-inhibited large pages.
310 * If not, we use 4k and set mmu_ci_restrictions so that
311 * hash_page knows to switch processes that use cache-inhibited
312 * mappings to 4k pages.
314 if (mmu_psize_defs
[MMU_PAGE_64K
].shift
) {
315 mmu_virtual_psize
= MMU_PAGE_64K
;
316 mmu_vmalloc_psize
= MMU_PAGE_64K
;
317 if (mmu_linear_psize
== MMU_PAGE_4K
)
318 mmu_linear_psize
= MMU_PAGE_64K
;
319 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE
))
320 mmu_io_psize
= MMU_PAGE_64K
;
322 mmu_ci_restrictions
= 1;
324 #endif /* CONFIG_PPC_64K_PAGES */
326 printk(KERN_DEBUG
"Page orders: linear mapping = %d, "
327 "virtual = %d, io = %d\n",
328 mmu_psize_defs
[mmu_linear_psize
].shift
,
329 mmu_psize_defs
[mmu_virtual_psize
].shift
,
330 mmu_psize_defs
[mmu_io_psize
].shift
);
332 #ifdef CONFIG_HUGETLB_PAGE
333 /* Init large page size. Currently, we pick 16M or 1M depending
334 * on what is available
336 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
337 mmu_huge_psize
= MMU_PAGE_16M
;
338 /* With 4k/4level pagetables, we can't (for now) cope with a
339 * huge page size < PMD_SIZE */
340 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
341 mmu_huge_psize
= MMU_PAGE_1M
;
343 /* Calculate HPAGE_SHIFT and sanity check it */
344 if (mmu_psize_defs
[mmu_huge_psize
].shift
> MIN_HUGEPTE_SHIFT
&&
345 mmu_psize_defs
[mmu_huge_psize
].shift
< SID_SHIFT
)
346 HPAGE_SHIFT
= mmu_psize_defs
[mmu_huge_psize
].shift
;
348 HPAGE_SHIFT
= 0; /* No huge pages dude ! */
349 #endif /* CONFIG_HUGETLB_PAGE */
352 static int __init
htab_dt_scan_pftsize(unsigned long node
,
353 const char *uname
, int depth
,
356 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
359 /* We are scanning "cpu" nodes only */
360 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
363 prop
= (u32
*)of_get_flat_dt_prop(node
, "ibm,pft-size", NULL
);
365 /* pft_size[0] is the NUMA CEC cookie */
366 ppc64_pft_size
= prop
[1];
372 static unsigned long __init
htab_get_table_size(void)
374 unsigned long mem_size
, rnd_mem_size
, pteg_count
;
376 /* If hash size isn't already provided by the platform, we try to
377 * retrieve it from the device-tree. If it's not there neither, we
378 * calculate it now based on the total RAM size
380 if (ppc64_pft_size
== 0)
381 of_scan_flat_dt(htab_dt_scan_pftsize
, NULL
);
383 return 1UL << ppc64_pft_size
;
385 /* round mem_size up to next power of 2 */
386 mem_size
= lmb_phys_mem_size();
387 rnd_mem_size
= 1UL << __ilog2(mem_size
);
388 if (rnd_mem_size
< mem_size
)
392 pteg_count
= max(rnd_mem_size
>> (12 + 1), 1UL << 11);
394 return pteg_count
<< 7;
397 #ifdef CONFIG_MEMORY_HOTPLUG
398 void create_section_mapping(unsigned long start
, unsigned long end
)
400 BUG_ON(htab_bolt_mapping(start
, end
, __pa(start
),
401 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_COHERENT
| PP_RWXX
,
404 #endif /* CONFIG_MEMORY_HOTPLUG */
406 static inline void make_bl(unsigned int *insn_addr
, void *func
)
408 unsigned long funcp
= *((unsigned long *)func
);
409 int offset
= funcp
- (unsigned long)insn_addr
;
411 *insn_addr
= (unsigned int)(0x48000001 | (offset
& 0x03fffffc));
412 flush_icache_range((unsigned long)insn_addr
, 4+
413 (unsigned long)insn_addr
);
416 static void __init
htab_finish_init(void)
418 extern unsigned int *htab_call_hpte_insert1
;
419 extern unsigned int *htab_call_hpte_insert2
;
420 extern unsigned int *htab_call_hpte_remove
;
421 extern unsigned int *htab_call_hpte_updatepp
;
423 #ifdef CONFIG_PPC_HAS_HASH_64K
424 extern unsigned int *ht64_call_hpte_insert1
;
425 extern unsigned int *ht64_call_hpte_insert2
;
426 extern unsigned int *ht64_call_hpte_remove
;
427 extern unsigned int *ht64_call_hpte_updatepp
;
429 make_bl(ht64_call_hpte_insert1
, ppc_md
.hpte_insert
);
430 make_bl(ht64_call_hpte_insert2
, ppc_md
.hpte_insert
);
431 make_bl(ht64_call_hpte_remove
, ppc_md
.hpte_remove
);
432 make_bl(ht64_call_hpte_updatepp
, ppc_md
.hpte_updatepp
);
433 #endif /* CONFIG_PPC_HAS_HASH_64K */
435 make_bl(htab_call_hpte_insert1
, ppc_md
.hpte_insert
);
436 make_bl(htab_call_hpte_insert2
, ppc_md
.hpte_insert
);
437 make_bl(htab_call_hpte_remove
, ppc_md
.hpte_remove
);
438 make_bl(htab_call_hpte_updatepp
, ppc_md
.hpte_updatepp
);
441 void __init
htab_initialize(void)
444 unsigned long pteg_count
;
445 unsigned long mode_rw
;
446 unsigned long base
= 0, size
= 0;
449 extern unsigned long tce_alloc_start
, tce_alloc_end
;
451 DBG(" -> htab_initialize()\n");
453 /* Initialize page sizes */
454 htab_init_page_sizes();
457 * Calculate the required size of the htab. We want the number of
458 * PTEGs to equal one half the number of real pages.
460 htab_size_bytes
= htab_get_table_size();
461 pteg_count
= htab_size_bytes
>> 7;
463 htab_hash_mask
= pteg_count
- 1;
465 if (firmware_has_feature(FW_FEATURE_LPAR
)) {
466 /* Using a hypervisor which owns the htab */
470 /* Find storage for the HPT. Must be contiguous in
471 * the absolute address space.
473 table
= lmb_alloc(htab_size_bytes
, htab_size_bytes
);
475 DBG("Hash table allocated at %lx, size: %lx\n", table
,
478 htab_address
= abs_to_virt(table
);
480 /* htab absolute addr + encoded htabsize */
481 _SDR1
= table
+ __ilog2(pteg_count
) - 11;
483 /* Initialize the HPT with no entries */
484 memset((void *)table
, 0, htab_size_bytes
);
487 mtspr(SPRN_SDR1
, _SDR1
);
490 mode_rw
= _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_COHERENT
| PP_RWXX
;
492 #ifdef CONFIG_DEBUG_PAGEALLOC
493 linear_map_hash_count
= lmb_end_of_DRAM() >> PAGE_SHIFT
;
494 linear_map_hash_slots
= __va(lmb_alloc_base(linear_map_hash_count
,
496 memset(linear_map_hash_slots
, 0, linear_map_hash_count
);
497 #endif /* CONFIG_DEBUG_PAGEALLOC */
499 /* On U3 based machines, we need to reserve the DART area and
500 * _NOT_ map it to avoid cache paradoxes as it's remapped non
504 /* create bolted the linear mapping in the hash table */
505 for (i
=0; i
< lmb
.memory
.cnt
; i
++) {
506 base
= (unsigned long)__va(lmb
.memory
.region
[i
].base
);
507 size
= lmb
.memory
.region
[i
].size
;
509 DBG("creating mapping for region: %lx : %lx\n", base
, size
);
511 #ifdef CONFIG_U3_DART
512 /* Do not map the DART space. Fortunately, it will be aligned
513 * in such a way that it will not cross two lmb regions and
514 * will fit within a single 16Mb page.
515 * The DART space is assumed to be a full 16Mb region even if
516 * we only use 2Mb of that space. We will use more of it later
517 * for AGP GART. We have to use a full 16Mb large page.
519 DBG("DART base: %lx\n", dart_tablebase
);
521 if (dart_tablebase
!= 0 && dart_tablebase
>= base
522 && dart_tablebase
< (base
+ size
)) {
523 unsigned long dart_table_end
= dart_tablebase
+ 16 * MB
;
524 if (base
!= dart_tablebase
)
525 BUG_ON(htab_bolt_mapping(base
, dart_tablebase
,
528 if ((base
+ size
) > dart_table_end
)
529 BUG_ON(htab_bolt_mapping(dart_tablebase
+16*MB
,
531 __pa(dart_table_end
),
536 #endif /* CONFIG_U3_DART */
537 BUG_ON(htab_bolt_mapping(base
, base
+ size
, __pa(base
),
538 mode_rw
, mmu_linear_psize
));
542 * If we have a memory_limit and we've allocated TCEs then we need to
543 * explicitly map the TCE area at the top of RAM. We also cope with the
544 * case that the TCEs start below memory_limit.
545 * tce_alloc_start/end are 16MB aligned so the mapping should work
546 * for either 4K or 16MB pages.
548 if (tce_alloc_start
) {
549 tce_alloc_start
= (unsigned long)__va(tce_alloc_start
);
550 tce_alloc_end
= (unsigned long)__va(tce_alloc_end
);
552 if (base
+ size
>= tce_alloc_start
)
553 tce_alloc_start
= base
+ size
+ 1;
555 BUG_ON(htab_bolt_mapping(tce_alloc_start
, tce_alloc_end
,
556 __pa(tce_alloc_start
), mode_rw
,
562 DBG(" <- htab_initialize()\n");
567 void htab_initialize_secondary(void)
569 if (!firmware_has_feature(FW_FEATURE_LPAR
))
570 mtspr(SPRN_SDR1
, _SDR1
);
574 * Called by asm hashtable.S for doing lazy icache flush
576 unsigned int hash_page_do_lazy_icache(unsigned int pp
, pte_t pte
, int trap
)
580 if (!pfn_valid(pte_pfn(pte
)))
583 page
= pte_page(pte
);
586 if (!test_bit(PG_arch_1
, &page
->flags
) && !PageReserved(page
)) {
588 __flush_dcache_icache(page_address(page
));
589 set_bit(PG_arch_1
, &page
->flags
);
597 * Demote a segment to using 4k pages.
598 * For now this makes the whole process use 4k pages.
600 #ifdef CONFIG_PPC_64K_PAGES
601 static void demote_segment_4k(struct mm_struct
*mm
, unsigned long addr
)
603 if (mm
->context
.user_psize
== MMU_PAGE_4K
)
605 #ifdef CONFIG_PPC_MM_SLICES
606 slice_set_user_psize(mm
, MMU_PAGE_4K
);
607 #else /* CONFIG_PPC_MM_SLICES */
608 mm
->context
.user_psize
= MMU_PAGE_4K
;
609 mm
->context
.sllp
= SLB_VSID_USER
| mmu_psize_defs
[MMU_PAGE_4K
].sllp
;
610 #endif /* CONFIG_PPC_MM_SLICES */
612 #ifdef CONFIG_SPU_BASE
613 spu_flush_all_slbs(mm
);
616 #endif /* CONFIG_PPC_64K_PAGES */
620 * 1 - normal page fault
621 * -1 - critical hash insertion error
623 int hash_page(unsigned long ea
, unsigned long access
, unsigned long trap
)
627 struct mm_struct
*mm
;
630 int rc
, user_region
= 0, local
= 0;
633 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
636 if ((ea
& ~REGION_MASK
) >= PGTABLE_RANGE
) {
637 DBG_LOW(" out of pgtable range !\n");
641 /* Get region & vsid */
642 switch (REGION_ID(ea
)) {
647 DBG_LOW(" user region with no mm !\n");
650 vsid
= get_vsid(mm
->context
.id
, ea
);
651 #ifdef CONFIG_PPC_MM_SLICES
652 psize
= get_slice_psize(mm
, ea
);
654 psize
= mm
->context
.user_psize
;
657 case VMALLOC_REGION_ID
:
659 vsid
= get_kernel_vsid(ea
);
660 if (ea
< VMALLOC_END
)
661 psize
= mmu_vmalloc_psize
;
663 psize
= mmu_io_psize
;
667 * Send the problem up to do_page_fault
671 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm
, mm
->pgd
, vsid
);
678 /* Check CPU locality */
679 tmp
= cpumask_of_cpu(smp_processor_id());
680 if (user_region
&& cpus_equal(mm
->cpu_vm_mask
, tmp
))
683 #ifdef CONFIG_HUGETLB_PAGE
684 /* Handle hugepage regions */
685 if (HPAGE_SHIFT
&& psize
== mmu_huge_psize
) {
686 DBG_LOW(" -> huge page !\n");
687 return hash_huge_page(mm
, access
, ea
, vsid
, local
, trap
);
689 #endif /* CONFIG_HUGETLB_PAGE */
691 #ifndef CONFIG_PPC_64K_PAGES
692 /* If we use 4K pages and our psize is not 4K, then we are hitting
693 * a special driver mapping, we need to align the address before
696 if (psize
!= MMU_PAGE_4K
)
697 ea
&= ~((1ul << mmu_psize_defs
[psize
].shift
) - 1);
698 #endif /* CONFIG_PPC_64K_PAGES */
700 /* Get PTE and page size from page tables */
701 ptep
= find_linux_pte(pgdir
, ea
);
702 if (ptep
== NULL
|| !pte_present(*ptep
)) {
703 DBG_LOW(" no PTE !\n");
707 #ifndef CONFIG_PPC_64K_PAGES
708 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep
));
710 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep
),
711 pte_val(*(ptep
+ PTRS_PER_PTE
)));
713 /* Pre-check access permissions (will be re-checked atomically
714 * in __hash_page_XX but this pre-check is a fast path
716 if (access
& ~pte_val(*ptep
)) {
717 DBG_LOW(" no access !\n");
721 /* Do actual hashing */
722 #ifdef CONFIG_PPC_64K_PAGES
723 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
724 if (pte_val(*ptep
) & _PAGE_4K_PFN
) {
725 demote_segment_4k(mm
, ea
);
729 /* If this PTE is non-cacheable and we have restrictions on
730 * using non cacheable large pages, then we switch to 4k
732 if (mmu_ci_restrictions
&& psize
== MMU_PAGE_64K
&&
733 (pte_val(*ptep
) & _PAGE_NO_CACHE
)) {
735 demote_segment_4k(mm
, ea
);
737 } else if (ea
< VMALLOC_END
) {
739 * some driver did a non-cacheable mapping
740 * in vmalloc space, so switch vmalloc
743 printk(KERN_ALERT
"Reducing vmalloc segment "
744 "to 4kB pages because of "
745 "non-cacheable mapping\n");
746 psize
= mmu_vmalloc_psize
= MMU_PAGE_4K
;
747 #ifdef CONFIG_SPU_BASE
748 spu_flush_all_slbs(mm
);
753 if (psize
!= get_paca()->context
.user_psize
) {
754 get_paca()->context
.user_psize
=
755 mm
->context
.user_psize
;
756 slb_flush_and_rebolt();
758 } else if (get_paca()->vmalloc_sllp
!=
759 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
) {
760 get_paca()->vmalloc_sllp
=
761 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
;
762 slb_vmalloc_update();
764 #endif /* CONFIG_PPC_64K_PAGES */
766 #ifdef CONFIG_PPC_HAS_HASH_64K
767 if (psize
== MMU_PAGE_64K
)
768 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
);
770 #endif /* CONFIG_PPC_HAS_HASH_64K */
771 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, local
);
773 #ifndef CONFIG_PPC_64K_PAGES
774 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep
));
776 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep
),
777 pte_val(*(ptep
+ PTRS_PER_PTE
)));
779 DBG_LOW(" -> rc=%d\n", rc
);
782 EXPORT_SYMBOL_GPL(hash_page
);
784 void hash_preload(struct mm_struct
*mm
, unsigned long ea
,
785 unsigned long access
, unsigned long trap
)
794 BUG_ON(REGION_ID(ea
) != USER_REGION_ID
);
796 #ifdef CONFIG_PPC_MM_SLICES
797 /* We only prefault standard pages for now */
798 if (unlikely(get_slice_psize(mm
, ea
) != mm
->context
.user_psize
))
802 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
803 " trap=%lx\n", mm
, mm
->pgd
, ea
, access
, trap
);
805 /* Get Linux PTE if available */
809 ptep
= find_linux_pte(pgdir
, ea
);
813 #ifdef CONFIG_PPC_64K_PAGES
814 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
815 * a 64K kernel), then we don't preload, hash_page() will take
816 * care of it once we actually try to access the page.
817 * That way we don't have to duplicate all of the logic for segment
818 * page size demotion here
820 if (pte_val(*ptep
) & (_PAGE_4K_PFN
| _PAGE_NO_CACHE
))
822 #endif /* CONFIG_PPC_64K_PAGES */
825 vsid
= get_vsid(mm
->context
.id
, ea
);
827 /* Hash doesn't like irqs */
828 local_irq_save(flags
);
830 /* Is that local to this CPU ? */
831 mask
= cpumask_of_cpu(smp_processor_id());
832 if (cpus_equal(mm
->cpu_vm_mask
, mask
))
836 #ifdef CONFIG_PPC_HAS_HASH_64K
837 if (mm
->context
.user_psize
== MMU_PAGE_64K
)
838 __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
);
840 #endif /* CONFIG_PPC_HAS_HASH_64K */
841 __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, local
);
843 local_irq_restore(flags
);
846 void flush_hash_page(unsigned long va
, real_pte_t pte
, int psize
, int local
)
848 unsigned long hash
, index
, shift
, hidx
, slot
;
850 DBG_LOW("flush_hash_page(va=%016x)\n", va
);
851 pte_iterate_hashed_subpages(pte
, psize
, va
, index
, shift
) {
852 hash
= hpt_hash(va
, shift
);
853 hidx
= __rpte_to_hidx(pte
, index
);
854 if (hidx
& _PTEIDX_SECONDARY
)
856 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
857 slot
+= hidx
& _PTEIDX_GROUP_IX
;
858 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index
, slot
, hidx
);
859 ppc_md
.hpte_invalidate(slot
, va
, psize
, local
);
860 } pte_iterate_hashed_end();
863 void flush_hash_range(unsigned long number
, int local
)
865 if (ppc_md
.flush_hash_range
)
866 ppc_md
.flush_hash_range(number
, local
);
869 struct ppc64_tlb_batch
*batch
=
870 &__get_cpu_var(ppc64_tlb_batch
);
872 for (i
= 0; i
< number
; i
++)
873 flush_hash_page(batch
->vaddr
[i
], batch
->pte
[i
],
874 batch
->psize
, local
);
879 * low_hash_fault is called when we the low level hash code failed
880 * to instert a PTE due to an hypervisor error
882 void low_hash_fault(struct pt_regs
*regs
, unsigned long address
)
884 if (user_mode(regs
)) {
887 info
.si_signo
= SIGBUS
;
889 info
.si_code
= BUS_ADRERR
;
890 info
.si_addr
= (void __user
*)address
;
891 force_sig_info(SIGBUS
, &info
, current
);
894 bad_page_fault(regs
, address
, SIGBUS
);
897 #ifdef CONFIG_DEBUG_PAGEALLOC
898 static void kernel_map_linear_page(unsigned long vaddr
, unsigned long lmi
)
900 unsigned long hash
, hpteg
, vsid
= get_kernel_vsid(vaddr
);
901 unsigned long va
= (vsid
<< 28) | (vaddr
& 0x0fffffff);
902 unsigned long mode
= _PAGE_ACCESSED
| _PAGE_DIRTY
|
903 _PAGE_COHERENT
| PP_RWXX
| HPTE_R_N
;
906 hash
= hpt_hash(va
, PAGE_SHIFT
);
907 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
909 ret
= ppc_md
.hpte_insert(hpteg
, va
, __pa(vaddr
),
910 mode
, HPTE_V_BOLTED
, mmu_linear_psize
);
912 spin_lock(&linear_map_hash_lock
);
913 BUG_ON(linear_map_hash_slots
[lmi
] & 0x80);
914 linear_map_hash_slots
[lmi
] = ret
| 0x80;
915 spin_unlock(&linear_map_hash_lock
);
918 static void kernel_unmap_linear_page(unsigned long vaddr
, unsigned long lmi
)
920 unsigned long hash
, hidx
, slot
, vsid
= get_kernel_vsid(vaddr
);
921 unsigned long va
= (vsid
<< 28) | (vaddr
& 0x0fffffff);
923 hash
= hpt_hash(va
, PAGE_SHIFT
);
924 spin_lock(&linear_map_hash_lock
);
925 BUG_ON(!(linear_map_hash_slots
[lmi
] & 0x80));
926 hidx
= linear_map_hash_slots
[lmi
] & 0x7f;
927 linear_map_hash_slots
[lmi
] = 0;
928 spin_unlock(&linear_map_hash_lock
);
929 if (hidx
& _PTEIDX_SECONDARY
)
931 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
932 slot
+= hidx
& _PTEIDX_GROUP_IX
;
933 ppc_md
.hpte_invalidate(slot
, va
, mmu_linear_psize
, 0);
936 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
938 unsigned long flags
, vaddr
, lmi
;
941 local_irq_save(flags
);
942 for (i
= 0; i
< numpages
; i
++, page
++) {
943 vaddr
= (unsigned long)page_address(page
);
944 lmi
= __pa(vaddr
) >> PAGE_SHIFT
;
945 if (lmi
>= linear_map_hash_count
)
948 kernel_map_linear_page(vaddr
, lmi
);
950 kernel_unmap_linear_page(vaddr
, lmi
);
952 local_irq_restore(flags
);
954 #endif /* CONFIG_DEBUG_PAGEALLOC */