arch/powerpc/mm/hash_utils_64.c

   1 /*
   2  * PowerPC64 port by Mike Corrigan and Dave Engebretsen
   3  *   {mikejc|engebret}@us.ibm.com
   4  *
   5  *    Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
   6  *
   7  * SMP scalability work:
   8  *    Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *
  10  *    Module name: htab.c
  11  *
  12  *    Description:
  13  *      PowerPC Hashed Page Table functions
  14  *
  15  * This program is free software; you can redistribute it and/or
  16  * modify it under the terms of the GNU General Public License
  17  * as published by the Free Software Foundation; either version
  18  * 2 of the License, or (at your option) any later version.
  19  */
  20
  21 #undef DEBUG
  22 #undef DEBUG_LOW
  23
  24 #include <linux/spinlock.h>
  25 #include <linux/errno.h>
  26 #include <linux/sched.h>
  27 #include <linux/proc_fs.h>
  28 #include <linux/stat.h>
  29 #include <linux/sysctl.h>
  30 #include <linux/ctype.h>
  31 #include <linux/cache.h>
  32 #include <linux/init.h>
  33 #include <linux/signal.h>
  34
  35 #include <asm/processor.h>
  36 #include <asm/pgtable.h>
  37 #include <asm/mmu.h>
  38 #include <asm/mmu_context.h>
  39 #include <asm/page.h>
  40 #include <asm/types.h>
  41 #include <asm/system.h>
  42 #include <asm/uaccess.h>
  43 #include <asm/machdep.h>
  44 #include <asm/lmb.h>
  45 #include <asm/abs_addr.h>
  46 #include <asm/tlbflush.h>
  47 #include <asm/io.h>
  48 #include <asm/eeh.h>
  49 #include <asm/tlb.h>
  50 #include <asm/cacheflush.h>
  51 #include <asm/cputable.h>
  52 #include <asm/sections.h>
  53 #include <asm/spu.h>
  54
  55 #ifdef DEBUG
  56 #define DBG(fmt...) udbg_printf(fmt)
  57 #else
  58 #define DBG(fmt...)
  59 #endif
  60
  61 #ifdef DEBUG_LOW
  62 #define DBG_LOW(fmt...) udbg_printf(fmt)
  63 #else
  64 #define DBG_LOW(fmt...)
  65 #endif
  66
  67 #define KB (1024)
  68 #define MB (1024*KB)
  69
  70 /*
  71  * Note:  pte   --> Linux PTE
  72  *        HPTE  --> PowerPC Hashed Page Table Entry
  73  *
  74  * Execution context:
  75  *   htab_initialize is called with the MMU off (of course), but
  76  *   the kernel has been copied down to zero so it can directly
  77  *   reference global data.  At this point it is very difficult
  78  *   to print debug info.
  79  *
  80  */
  81
  82 #ifdef CONFIG_U3_DART
  83 extern unsigned long dart_tablebase;
  84 #endif /* CONFIG_U3_DART */
  85
  86 static unsigned long _SDR1;
  87 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
  88
  89 struct hash_pte *htab_address;
  90 unsigned long htab_size_bytes;
  91 unsigned long htab_hash_mask;
  92 int mmu_linear_psize = MMU_PAGE_4K;
  93 int mmu_virtual_psize = MMU_PAGE_4K;
  94 int mmu_vmalloc_psize = MMU_PAGE_4K;
  95 int mmu_io_psize = MMU_PAGE_4K;
  96 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
  97 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
  98 #ifdef CONFIG_HUGETLB_PAGE
  99 int mmu_huge_psize = MMU_PAGE_16M;
 100 unsigned int HPAGE_SHIFT;
 101 #endif
 102 #ifdef CONFIG_PPC_64K_PAGES
 103 int mmu_ci_restrictions;
 104 #endif
 105 #ifdef CONFIG_DEBUG_PAGEALLOC
 106 static u8 *linear_map_hash_slots;
 107 static unsigned long linear_map_hash_count;
 108 static DEFINE_SPINLOCK(linear_map_hash_lock);
 109 #endif /* CONFIG_DEBUG_PAGEALLOC */
 110
 111 /* There are definitions of page sizes arrays to be used when none
 112  * is provided by the firmware.
 113  */
 114
 115 /* Pre-POWER4 CPUs (4k pages only)
 116  */
 117 struct mmu_psize_def mmu_psize_defaults_old[] = {
 118         [MMU_PAGE_4K] = {
 119                 .shift  = 12,
 120                 .sllp   = 0,
 121                 .penc   = 0,
 122                 .avpnm  = 0,
 123                 .tlbiel = 0,
 124         },
 125 };
 126
 127 /* POWER4, GPUL, POWER5
 128  *
 129  * Support for 16Mb large pages
 130  */
 131 struct mmu_psize_def mmu_psize_defaults_gp[] = {
 132         [MMU_PAGE_4K] = {
 133                 .shift  = 12,
 134                 .sllp   = 0,
 135                 .penc   = 0,
 136                 .avpnm  = 0,
 137                 .tlbiel = 1,
 138         },
 139         [MMU_PAGE_16M] = {
 140                 .shift  = 24,
 141                 .sllp   = SLB_VSID_L,
 142                 .penc   = 0,
 143                 .avpnm  = 0x1UL,
 144                 .tlbiel = 0,
 145         },
 146 };
 147
 148
 149 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
 150                       unsigned long pstart, unsigned long mode,
 151                       int psize, int ssize)
 152 {
 153         unsigned long vaddr, paddr;
 154         unsigned int step, shift;
 155         unsigned long tmp_mode;
 156         int ret = 0;
 157
 158         shift = mmu_psize_defs[psize].shift;
 159         step = 1 << shift;
 160
 161         for (vaddr = vstart, paddr = pstart; vaddr < vend;
 162              vaddr += step, paddr += step) {
 163                 unsigned long hash, hpteg;
 164                 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
 165                 unsigned long va = hpt_va(vaddr, vsid, ssize);
 166
 167                 tmp_mode = mode;
 168
 169                 /* Make non-kernel text non-executable */
 170                 if (!in_kernel_text(vaddr))
 171                         tmp_mode = mode | HPTE_R_N;
 172
 173                 hash = hpt_hash(va, shift, ssize);
 174                 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 175
 176                 DBG("htab_bolt_mapping: calling %p\n", ppc_md.hpte_insert);
 177
 178                 BUG_ON(!ppc_md.hpte_insert);
 179                 ret = ppc_md.hpte_insert(hpteg, va, paddr,
 180                                 tmp_mode, HPTE_V_BOLTED, psize, ssize);
 181
 182                 if (ret < 0)
 183                         break;
 184 #ifdef CONFIG_DEBUG_PAGEALLOC
 185                 if ((paddr >> PAGE_SHIFT) < linear_map_hash_count)
 186                         linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
 187 #endif /* CONFIG_DEBUG_PAGEALLOC */
 188         }
 189         return ret < 0 ? ret : 0;
 190 }
 191
 192 static int __init htab_dt_scan_seg_sizes(unsigned long node,
 193                                          const char *uname, int depth,
 194                                          void *data)
 195 {
 196         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 197         u32 *prop;
 198         unsigned long size = 0;
 199
 200         /* We are scanning "cpu" nodes only */
 201         if (type == NULL || strcmp(type, "cpu") != 0)
 202                 return 0;
 203
 204         prop = (u32 *)of_get_flat_dt_prop(node, "ibm,processor-segment-sizes",
 205                                           &size);
 206         if (prop == NULL)
 207                 return 0;
 208         for (; size >= 4; size -= 4, ++prop) {
 209                 if (prop[0] == 40) {
 210                         DBG("1T segment support detected\n");
 211                         cur_cpu_spec->cpu_features |= CPU_FTR_1T_SEGMENT;
 212                 }
 213                 return 1;
 214         }
 215         return 0;
 216 }
 217
 218 static void __init htab_init_seg_sizes(void)
 219 {
 220         of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
 221 }
 222
 223 static int __init htab_dt_scan_page_sizes(unsigned long node,
 224                                           const char *uname, int depth,
 225                                           void *data)
 226 {
 227         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 228         u32 *prop;
 229         unsigned long size = 0;
 230
 231         /* We are scanning "cpu" nodes only */
 232         if (type == NULL || strcmp(type, "cpu") != 0)
 233                 return 0;
 234
 235         prop = (u32 *)of_get_flat_dt_prop(node,
 236                                           "ibm,segment-page-sizes", &size);
 237         if (prop != NULL) {
 238                 DBG("Page sizes from device-tree:\n");
 239                 size /= 4;
 240                 cur_cpu_spec->cpu_features &= ~(CPU_FTR_16M_PAGE);
 241                 while(size > 0) {
 242                         unsigned int shift = prop[0];
 243                         unsigned int slbenc = prop[1];
 244                         unsigned int lpnum = prop[2];
 245                         unsigned int lpenc = 0;
 246                         struct mmu_psize_def *def;
 247                         int idx = -1;
 248
 249                         size -= 3; prop += 3;
 250                         while(size > 0 && lpnum) {
 251                                 if (prop[0] == shift)
 252                                         lpenc = prop[1];
 253                                 prop += 2; size -= 2;
 254                                 lpnum--;
 255                         }
 256                         switch(shift) {
 257                         case 0xc:
 258                                 idx = MMU_PAGE_4K;
 259                                 break;
 260                         case 0x10:
 261                                 idx = MMU_PAGE_64K;
 262                                 break;
 263                         case 0x14:
 264                                 idx = MMU_PAGE_1M;
 265                                 break;
 266                         case 0x18:
 267                                 idx = MMU_PAGE_16M;
 268                                 cur_cpu_spec->cpu_features |= CPU_FTR_16M_PAGE;
 269                                 break;
 270                         case 0x22:
 271                                 idx = MMU_PAGE_16G;
 272                                 break;
 273                         }
 274                         if (idx < 0)
 275                                 continue;
 276                         def = &mmu_psize_defs[idx];
 277                         def->shift = shift;
 278                         if (shift <= 23)
 279                                 def->avpnm = 0;
 280                         else
 281                                 def->avpnm = (1 << (shift - 23)) - 1;
 282                         def->sllp = slbenc;
 283                         def->penc = lpenc;
 284                         /* We don't know for sure what's up with tlbiel, so
 285                          * for now we only set it for 4K and 64K pages
 286                          */
 287                         if (idx == MMU_PAGE_4K || idx == MMU_PAGE_64K)
 288                                 def->tlbiel = 1;
 289                         else
 290                                 def->tlbiel = 0;
 291
 292                         DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
 293                             "tlbiel=%d, penc=%d\n",
 294                             idx, shift, def->sllp, def->avpnm, def->tlbiel,
 295                             def->penc);
 296                 }
 297                 return 1;
 298         }
 299         return 0;
 300 }
 301
 302 static void __init htab_init_page_sizes(void)
 303 {
 304         int rc;
 305
 306         /* Default to 4K pages only */
 307         memcpy(mmu_psize_defs, mmu_psize_defaults_old,
 308                sizeof(mmu_psize_defaults_old));
 309
 310         /*
 311          * Try to find the available page sizes in the device-tree
 312          */
 313         rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
 314         if (rc != 0)  /* Found */
 315                 goto found;
 316
 317         /*
 318          * Not in the device-tree, let's fallback on known size
 319          * list for 16M capable GP & GR
 320          */
 321         if (cpu_has_feature(CPU_FTR_16M_PAGE))
 322                 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
 323                        sizeof(mmu_psize_defaults_gp));
 324  found:
 325 #ifndef CONFIG_DEBUG_PAGEALLOC
 326         /*
 327          * Pick a size for the linear mapping. Currently, we only support
 328          * 16M, 1M and 4K which is the default
 329          */
 330         if (mmu_psize_defs[MMU_PAGE_16M].shift)
 331                 mmu_linear_psize = MMU_PAGE_16M;
 332         else if (mmu_psize_defs[MMU_PAGE_1M].shift)
 333                 mmu_linear_psize = MMU_PAGE_1M;
 334 #endif /* CONFIG_DEBUG_PAGEALLOC */
 335
 336 #ifdef CONFIG_PPC_64K_PAGES
 337         /*
 338          * Pick a size for the ordinary pages. Default is 4K, we support
 339          * 64K for user mappings and vmalloc if supported by the processor.
 340          * We only use 64k for ioremap if the processor
 341          * (and firmware) support cache-inhibited large pages.
 342          * If not, we use 4k and set mmu_ci_restrictions so that
 343          * hash_page knows to switch processes that use cache-inhibited
 344          * mappings to 4k pages.
 345          */
 346         if (mmu_psize_defs[MMU_PAGE_64K].shift) {
 347                 mmu_virtual_psize = MMU_PAGE_64K;
 348                 mmu_vmalloc_psize = MMU_PAGE_64K;
 349                 if (mmu_linear_psize == MMU_PAGE_4K)
 350                         mmu_linear_psize = MMU_PAGE_64K;
 351                 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE))
 352                         mmu_io_psize = MMU_PAGE_64K;
 353                 else
 354                         mmu_ci_restrictions = 1;
 355         }
 356 #endif /* CONFIG_PPC_64K_PAGES */
 357
 358         printk(KERN_DEBUG "Page orders: linear mapping = %d, "
 359                "virtual = %d, io = %d\n",
 360                mmu_psize_defs[mmu_linear_psize].shift,
 361                mmu_psize_defs[mmu_virtual_psize].shift,
 362                mmu_psize_defs[mmu_io_psize].shift);
 363
 364 #ifdef CONFIG_HUGETLB_PAGE
 365         /* Init large page size. Currently, we pick 16M or 1M depending
 366          * on what is available
 367          */
 368         if (mmu_psize_defs[MMU_PAGE_16M].shift)
 369                 mmu_huge_psize = MMU_PAGE_16M;
 370         /* With 4k/4level pagetables, we can't (for now) cope with a
 371          * huge page size < PMD_SIZE */
 372         else if (mmu_psize_defs[MMU_PAGE_1M].shift)
 373                 mmu_huge_psize = MMU_PAGE_1M;
 374
 375         /* Calculate HPAGE_SHIFT and sanity check it */
 376         if (mmu_psize_defs[mmu_huge_psize].shift > MIN_HUGEPTE_SHIFT &&
 377             mmu_psize_defs[mmu_huge_psize].shift < SID_SHIFT)
 378                 HPAGE_SHIFT = mmu_psize_defs[mmu_huge_psize].shift;
 379         else
 380                 HPAGE_SHIFT = 0; /* No huge pages dude ! */
 381 #endif /* CONFIG_HUGETLB_PAGE */
 382 }
 383
 384 static int __init htab_dt_scan_pftsize(unsigned long node,
 385                                        const char *uname, int depth,
 386                                        void *data)
 387 {
 388         char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 389         u32 *prop;
 390
 391         /* We are scanning "cpu" nodes only */
 392         if (type == NULL || strcmp(type, "cpu") != 0)
 393                 return 0;
 394
 395         prop = (u32 *)of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
 396         if (prop != NULL) {
 397                 /* pft_size[0] is the NUMA CEC cookie */
 398                 ppc64_pft_size = prop[1];
 399                 return 1;
 400         }
 401         return 0;
 402 }
 403
 404 static unsigned long __init htab_get_table_size(void)
 405 {
 406         unsigned long mem_size, rnd_mem_size, pteg_count;
 407
 408         /* If hash size isn't already provided by the platform, we try to
 409          * retrieve it from the device-tree. If it's not there neither, we
 410          * calculate it now based on the total RAM size
 411          */
 412         if (ppc64_pft_size == 0)
 413                 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
 414         if (ppc64_pft_size)
 415                 return 1UL << ppc64_pft_size;
 416
 417         /* round mem_size up to next power of 2 */
 418         mem_size = lmb_phys_mem_size();
 419         rnd_mem_size = 1UL << __ilog2(mem_size);
 420         if (rnd_mem_size < mem_size)
 421                 rnd_mem_size <<= 1;
 422
 423         /* # pages / 2 */
 424         pteg_count = max(rnd_mem_size >> (12 + 1), 1UL << 11);
 425
 426         return pteg_count << 7;
 427 }
 428
 429 #ifdef CONFIG_MEMORY_HOTPLUG
 430 void create_section_mapping(unsigned long start, unsigned long end)
 431 {
 432                 BUG_ON(htab_bolt_mapping(start, end, __pa(start),
 433                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX,
 434                         mmu_linear_psize, mmu_kernel_ssize));
 435 }
 436 #endif /* CONFIG_MEMORY_HOTPLUG */
 437
 438 static inline void make_bl(unsigned int *insn_addr, void *func)
 439 {
 440         unsigned long funcp = *((unsigned long *)func);
 441         int offset = funcp - (unsigned long)insn_addr;
 442
 443         *insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
 444         flush_icache_range((unsigned long)insn_addr, 4+
 445                            (unsigned long)insn_addr);
 446 }
 447
 448 static void __init htab_finish_init(void)
 449 {
 450         extern unsigned int *htab_call_hpte_insert1;
 451         extern unsigned int *htab_call_hpte_insert2;
 452         extern unsigned int *htab_call_hpte_remove;
 453         extern unsigned int *htab_call_hpte_updatepp;
 454
 455 #ifdef CONFIG_PPC_HAS_HASH_64K
 456         extern unsigned int *ht64_call_hpte_insert1;
 457         extern unsigned int *ht64_call_hpte_insert2;
 458         extern unsigned int *ht64_call_hpte_remove;
 459         extern unsigned int *ht64_call_hpte_updatepp;
 460
 461         make_bl(ht64_call_hpte_insert1, ppc_md.hpte_insert);
 462         make_bl(ht64_call_hpte_insert2, ppc_md.hpte_insert);
 463         make_bl(ht64_call_hpte_remove, ppc_md.hpte_remove);
 464         make_bl(ht64_call_hpte_updatepp, ppc_md.hpte_updatepp);
 465 #endif /* CONFIG_PPC_HAS_HASH_64K */
 466
 467         make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
 468         make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
 469         make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
 470         make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
 471 }
 472
 473 void __init htab_initialize(void)
 474 {
 475         unsigned long table;
 476         unsigned long pteg_count;
 477         unsigned long mode_rw;
 478         unsigned long base = 0, size = 0;
 479         int i;
 480
 481         extern unsigned long tce_alloc_start, tce_alloc_end;
 482
 483         DBG(" -> htab_initialize()\n");
 484
 485         /* Initialize segment sizes */
 486         htab_init_seg_sizes();
 487
 488         /* Initialize page sizes */
 489         htab_init_page_sizes();
 490
 491         if (cpu_has_feature(CPU_FTR_1T_SEGMENT)) {
 492                 mmu_kernel_ssize = MMU_SEGSIZE_1T;
 493                 mmu_highuser_ssize = MMU_SEGSIZE_1T;
 494                 printk(KERN_INFO "Using 1TB segments\n");
 495         }
 496
 497         /*
 498          * Calculate the required size of the htab.  We want the number of
 499          * PTEGs to equal one half the number of real pages.
 500          */
 501         htab_size_bytes = htab_get_table_size();
 502         pteg_count = htab_size_bytes >> 7;
 503
 504         htab_hash_mask = pteg_count - 1;
 505
 506         if (firmware_has_feature(FW_FEATURE_LPAR)) {
 507                 /* Using a hypervisor which owns the htab */
 508                 htab_address = NULL;
 509                 _SDR1 = 0;
 510         } else {
 511                 /* Find storage for the HPT.  Must be contiguous in
 512                  * the absolute address space.
 513                  */
 514                 table = lmb_alloc(htab_size_bytes, htab_size_bytes);
 515
 516                 DBG("Hash table allocated at %lx, size: %lx\n", table,
 517                     htab_size_bytes);
 518
 519                 htab_address = abs_to_virt(table);
 520
 521                 /* htab absolute addr + encoded htabsize */
 522                 _SDR1 = table + __ilog2(pteg_count) - 11;
 523
 524                 /* Initialize the HPT with no entries */
 525                 memset((void *)table, 0, htab_size_bytes);
 526
 527                 /* Set SDR1 */
 528                 mtspr(SPRN_SDR1, _SDR1);
 529         }
 530
 531         mode_rw = _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_COHERENT | PP_RWXX;
 532
 533 #ifdef CONFIG_DEBUG_PAGEALLOC
 534         linear_map_hash_count = lmb_end_of_DRAM() >> PAGE_SHIFT;
 535         linear_map_hash_slots = __va(lmb_alloc_base(linear_map_hash_count,
 536                                                     1, lmb.rmo_size));
 537         memset(linear_map_hash_slots, 0, linear_map_hash_count);
 538 #endif /* CONFIG_DEBUG_PAGEALLOC */
 539
 540         /* On U3 based machines, we need to reserve the DART area and
 541          * _NOT_ map it to avoid cache paradoxes as it's remapped non
 542          * cacheable later on
 543          */
 544
 545         /* create bolted the linear mapping in the hash table */
 546         for (i=0; i < lmb.memory.cnt; i++) {
 547                 base = (unsigned long)__va(lmb.memory.region[i].base);
 548                 size = lmb.memory.region[i].size;
 549
 550                 DBG("creating mapping for region: %lx : %lx\n", base, size);
 551
 552 #ifdef CONFIG_U3_DART
 553                 /* Do not map the DART space. Fortunately, it will be aligned
 554                  * in such a way that it will not cross two lmb regions and
 555                  * will fit within a single 16Mb page.
 556                  * The DART space is assumed to be a full 16Mb region even if
 557                  * we only use 2Mb of that space. We will use more of it later
 558                  * for AGP GART. We have to use a full 16Mb large page.
 559                  */
 560                 DBG("DART base: %lx\n", dart_tablebase);
 561
 562                 if (dart_tablebase != 0 && dart_tablebase >= base
 563                     && dart_tablebase < (base + size)) {
 564                         unsigned long dart_table_end = dart_tablebase + 16 * MB;
 565                         if (base != dart_tablebase)
 566                                 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
 567                                                         __pa(base), mode_rw,
 568                                                         mmu_linear_psize,
 569                                                         mmu_kernel_ssize));
 570                         if ((base + size) > dart_table_end)
 571                                 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
 572                                                         base + size,
 573                                                         __pa(dart_table_end),
 574                                                          mode_rw,
 575                                                          mmu_linear_psize,
 576                                                          mmu_kernel_ssize));
 577                         continue;
 578                 }
 579 #endif /* CONFIG_U3_DART */
 580                 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
 581                                 mode_rw, mmu_linear_psize, mmu_kernel_ssize));
 582        }
 583
 584         /*
 585          * If we have a memory_limit and we've allocated TCEs then we need to
 586          * explicitly map the TCE area at the top of RAM. We also cope with the
 587          * case that the TCEs start below memory_limit.
 588          * tce_alloc_start/end are 16MB aligned so the mapping should work
 589          * for either 4K or 16MB pages.
 590          */
 591         if (tce_alloc_start) {
 592                 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
 593                 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
 594
 595                 if (base + size >= tce_alloc_start)
 596                         tce_alloc_start = base + size + 1;
 597
 598                 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
 599                                          __pa(tce_alloc_start), mode_rw,
 600                                          mmu_linear_psize, mmu_kernel_ssize));
 601         }
 602
 603         htab_finish_init();
 604
 605         DBG(" <- htab_initialize()\n");
 606 }
 607 #undef KB
 608 #undef MB
 609
 610 void htab_initialize_secondary(void)
 611 {
 612         if (!firmware_has_feature(FW_FEATURE_LPAR))
 613                 mtspr(SPRN_SDR1, _SDR1);
 614 }
 615
 616 /*
 617  * Called by asm hashtable.S for doing lazy icache flush
 618  */
 619 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
 620 {
 621         struct page *page;
 622
 623         if (!pfn_valid(pte_pfn(pte)))
 624                 return pp;
 625
 626         page = pte_page(pte);
 627
 628         /* page is dirty */
 629         if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
 630                 if (trap == 0x400) {
 631                         __flush_dcache_icache(page_address(page));
 632                         set_bit(PG_arch_1, &page->flags);
 633                 } else
 634                         pp |= HPTE_R_N;
 635         }
 636         return pp;
 637 }
 638
 639 /*
 640  * Demote a segment to using 4k pages.
 641  * For now this makes the whole process use 4k pages.
 642  */
 643 #ifdef CONFIG_PPC_64K_PAGES
 644 static void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
 645 {
 646         if (mm->context.user_psize == MMU_PAGE_4K)
 647                 return;
 648         slice_set_user_psize(mm, MMU_PAGE_4K);
 649 #ifdef CONFIG_SPU_BASE
 650         spu_flush_all_slbs(mm);
 651 #endif
 652 }
 653 #endif /* CONFIG_PPC_64K_PAGES */
 654
 655 /* Result code is:
 656  *  0 - handled
 657  *  1 - normal page fault
 658  * -1 - critical hash insertion error
 659  */
 660 int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 661 {
 662         void *pgdir;
 663         unsigned long vsid;
 664         struct mm_struct *mm;
 665         pte_t *ptep;
 666         cpumask_t tmp;
 667         int rc, user_region = 0, local = 0;
 668         int psize, ssize;
 669
 670         DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
 671                 ea, access, trap);
 672
 673         if ((ea & ~REGION_MASK) >= PGTABLE_RANGE) {
 674                 DBG_LOW(" out of pgtable range !\n");
 675                 return 1;
 676         }
 677
 678         /* Get region & vsid */
 679         switch (REGION_ID(ea)) {
 680         case USER_REGION_ID:
 681                 user_region = 1;
 682                 mm = current->mm;
 683                 if (! mm) {
 684                         DBG_LOW(" user region with no mm !\n");
 685                         return 1;
 686                 }
 687 #ifdef CONFIG_PPC_MM_SLICES
 688                 psize = get_slice_psize(mm, ea);
 689 #else
 690                 psize = mm->context.user_psize;
 691 #endif
 692                 ssize = user_segment_size(ea);
 693                 vsid = get_vsid(mm->context.id, ea, ssize);
 694                 break;
 695         case VMALLOC_REGION_ID:
 696                 mm = &init_mm;
 697                 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
 698                 if (ea < VMALLOC_END)
 699                         psize = mmu_vmalloc_psize;
 700                 else
 701                         psize = mmu_io_psize;
 702                 ssize = mmu_kernel_ssize;
 703                 break;
 704         default:
 705                 /* Not a valid range
 706                  * Send the problem up to do_page_fault
 707                  */
 708                 return 1;
 709         }
 710         DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
 711
 712         /* Get pgdir */
 713         pgdir = mm->pgd;
 714         if (pgdir == NULL)
 715                 return 1;
 716
 717         /* Check CPU locality */
 718         tmp = cpumask_of_cpu(smp_processor_id());
 719         if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
 720                 local = 1;
 721
 722 #ifdef CONFIG_HUGETLB_PAGE
 723         /* Handle hugepage regions */
 724         if (HPAGE_SHIFT && psize == mmu_huge_psize) {
 725                 DBG_LOW(" -> huge page !\n");
 726                 return hash_huge_page(mm, access, ea, vsid, local, trap);
 727         }
 728 #endif /* CONFIG_HUGETLB_PAGE */
 729
 730 #ifndef CONFIG_PPC_64K_PAGES
 731         /* If we use 4K pages and our psize is not 4K, then we are hitting
 732          * a special driver mapping, we need to align the address before
 733          * we fetch the PTE
 734          */
 735         if (psize != MMU_PAGE_4K)
 736                 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
 737 #endif /* CONFIG_PPC_64K_PAGES */
 738
 739         /* Get PTE and page size from page tables */
 740         ptep = find_linux_pte(pgdir, ea);
 741         if (ptep == NULL || !pte_present(*ptep)) {
 742                 DBG_LOW(" no PTE !\n");
 743                 return 1;
 744         }
 745
 746 #ifndef CONFIG_PPC_64K_PAGES
 747         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
 748 #else
 749         DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
 750                 pte_val(*(ptep + PTRS_PER_PTE)));
 751 #endif
 752         /* Pre-check access permissions (will be re-checked atomically
 753          * in __hash_page_XX but this pre-check is a fast path
 754          */
 755         if (access & ~pte_val(*ptep)) {
 756                 DBG_LOW(" no access !\n");
 757                 return 1;
 758         }
 759
 760         /* Do actual hashing */
 761 #ifdef CONFIG_PPC_64K_PAGES
 762         /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
 763         if (pte_val(*ptep) & _PAGE_4K_PFN) {
 764                 demote_segment_4k(mm, ea);
 765                 psize = MMU_PAGE_4K;
 766         }
 767
 768         /* If this PTE is non-cacheable and we have restrictions on
 769          * using non cacheable large pages, then we switch to 4k
 770          */
 771         if (mmu_ci_restrictions && psize == MMU_PAGE_64K &&
 772             (pte_val(*ptep) & _PAGE_NO_CACHE)) {
 773                 if (user_region) {
 774                         demote_segment_4k(mm, ea);
 775                         psize = MMU_PAGE_4K;
 776                 } else if (ea < VMALLOC_END) {
 777                         /*
 778                          * some driver did a non-cacheable mapping
 779                          * in vmalloc space, so switch vmalloc
 780                          * to 4k pages
 781                          */
 782                         printk(KERN_ALERT "Reducing vmalloc segment "
 783                                "to 4kB pages because of "
 784                                "non-cacheable mapping\n");
 785                         psize = mmu_vmalloc_psize = MMU_PAGE_4K;
 786 #ifdef CONFIG_SPU_BASE
 787                         spu_flush_all_slbs(mm);
 788 #endif
 789                 }
 790         }
 791         if (user_region) {
 792                 if (psize != get_paca()->context.user_psize) {
 793                         get_paca()->context.user_psize =
 794                                 mm->context.user_psize;
 795                         slb_flush_and_rebolt();
 796                 }
 797         } else if (get_paca()->vmalloc_sllp !=
 798                    mmu_psize_defs[mmu_vmalloc_psize].sllp) {
 799                 get_paca()->vmalloc_sllp =
 800                         mmu_psize_defs[mmu_vmalloc_psize].sllp;
 801                 slb_vmalloc_update();
 802         }
 803 #endif /* CONFIG_PPC_64K_PAGES */
 804
 805 #ifdef CONFIG_PPC_HAS_HASH_64K
 806         if (psize == MMU_PAGE_64K)
 807                 rc = __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
 808         else
 809 #endif /* CONFIG_PPC_HAS_HASH_64K */
 810                 rc = __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize);
 811
 812 #ifndef CONFIG_PPC_64K_PAGES
 813         DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
 814 #else
 815         DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
 816                 pte_val(*(ptep + PTRS_PER_PTE)));
 817 #endif
 818         DBG_LOW(" -> rc=%d\n", rc);
 819         return rc;
 820 }
 821 EXPORT_SYMBOL_GPL(hash_page);
 822
 823 void hash_preload(struct mm_struct *mm, unsigned long ea,
 824                   unsigned long access, unsigned long trap)
 825 {
 826         unsigned long vsid;
 827         void *pgdir;
 828         pte_t *ptep;
 829         cpumask_t mask;
 830         unsigned long flags;
 831         int local = 0;
 832         int ssize;
 833
 834         BUG_ON(REGION_ID(ea) != USER_REGION_ID);
 835
 836 #ifdef CONFIG_PPC_MM_SLICES
 837         /* We only prefault standard pages for now */
 838         if (unlikely(get_slice_psize(mm, ea) != mm->context.user_psize))
 839                 return;
 840 #endif
 841
 842         DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
 843                 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
 844
 845         /* Get Linux PTE if available */
 846         pgdir = mm->pgd;
 847         if (pgdir == NULL)
 848                 return;
 849         ptep = find_linux_pte(pgdir, ea);
 850         if (!ptep)
 851                 return;
 852
 853 #ifdef CONFIG_PPC_64K_PAGES
 854         /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
 855          * a 64K kernel), then we don't preload, hash_page() will take
 856          * care of it once we actually try to access the page.
 857          * That way we don't have to duplicate all of the logic for segment
 858          * page size demotion here
 859          */
 860         if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
 861                 return;
 862 #endif /* CONFIG_PPC_64K_PAGES */
 863
 864         /* Get VSID */
 865         ssize = user_segment_size(ea);
 866         vsid = get_vsid(mm->context.id, ea, ssize);
 867
 868         /* Hash doesn't like irqs */
 869         local_irq_save(flags);
 870
 871         /* Is that local to this CPU ? */
 872         mask = cpumask_of_cpu(smp_processor_id());
 873         if (cpus_equal(mm->cpu_vm_mask, mask))
 874                 local = 1;
 875
 876         /* Hash it in */
 877 #ifdef CONFIG_PPC_HAS_HASH_64K
 878         if (mm->context.user_psize == MMU_PAGE_64K)
 879                 __hash_page_64K(ea, access, vsid, ptep, trap, local, ssize);
 880         else
 881 #endif /* CONFIG_PPC_HAS_HASH_64K */
 882                 __hash_page_4K(ea, access, vsid, ptep, trap, local, ssize);
 883
 884         local_irq_restore(flags);
 885 }
 886
 887 void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
 888                      int local)
 889 {
 890         unsigned long hash, index, shift, hidx, slot;
 891
 892         DBG_LOW("flush_hash_page(va=%016x)\n", va);
 893         pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
 894                 hash = hpt_hash(va, shift, ssize);
 895                 hidx = __rpte_to_hidx(pte, index);
 896                 if (hidx & _PTEIDX_SECONDARY)
 897                         hash = ~hash;
 898                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
 899                 slot += hidx & _PTEIDX_GROUP_IX;
 900                 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
 901                 ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
 902         } pte_iterate_hashed_end();
 903 }
 904
 905 void flush_hash_range(unsigned long number, int local)
 906 {
 907         if (ppc_md.flush_hash_range)
 908                 ppc_md.flush_hash_range(number, local);
 909         else {
 910                 int i;
 911                 struct ppc64_tlb_batch *batch =
 912                         &__get_cpu_var(ppc64_tlb_batch);
 913
 914                 for (i = 0; i < number; i++)
 915                         flush_hash_page(batch->vaddr[i], batch->pte[i],
 916                                         batch->psize, batch->ssize, local);
 917         }
 918 }
 919
 920 /*
 921  * low_hash_fault is called when we the low level hash code failed
 922  * to instert a PTE due to an hypervisor error
 923  */
 924 void low_hash_fault(struct pt_regs *regs, unsigned long address)
 925 {
 926         if (user_mode(regs)) {
 927                 siginfo_t info;
 928
 929                 info.si_signo = SIGBUS;
 930                 info.si_errno = 0;
 931                 info.si_code = BUS_ADRERR;
 932                 info.si_addr = (void __user *)address;
 933                 force_sig_info(SIGBUS, &info, current);
 934                 return;
 935         }
 936         bad_page_fault(regs, address, SIGBUS);
 937 }
 938
 939 #ifdef CONFIG_DEBUG_PAGEALLOC
 940 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
 941 {
 942         unsigned long hash, hpteg;
 943         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
 944         unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
 945         unsigned long mode = _PAGE_ACCESSED | _PAGE_DIRTY |
 946                 _PAGE_COHERENT | PP_RWXX | HPTE_R_N;
 947         int ret;
 948
 949         hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
 950         hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
 951
 952         ret = ppc_md.hpte_insert(hpteg, va, __pa(vaddr),
 953                                  mode, HPTE_V_BOLTED,
 954                                  mmu_linear_psize, mmu_kernel_ssize);
 955         BUG_ON (ret < 0);
 956         spin_lock(&linear_map_hash_lock);
 957         BUG_ON(linear_map_hash_slots[lmi] & 0x80);
 958         linear_map_hash_slots[lmi] = ret | 0x80;
 959         spin_unlock(&linear_map_hash_lock);
 960 }
 961
 962 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
 963 {
 964         unsigned long hash, hidx, slot;
 965         unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
 966         unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
 967
 968         hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
 969         spin_lock(&linear_map_hash_lock);
 970         BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
 971         hidx = linear_map_hash_slots[lmi] & 0x7f;
 972         linear_map_hash_slots[lmi] = 0;
 973         spin_unlock(&linear_map_hash_lock);
 974         if (hidx & _PTEIDX_SECONDARY)
 975                 hash = ~hash;
 976         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
 977         slot += hidx & _PTEIDX_GROUP_IX;
 978         ppc_md.hpte_invalidate(slot, va, mmu_linear_psize, mmu_kernel_ssize, 0);
 979 }
 980
 981 void kernel_map_pages(struct page *page, int numpages, int enable)
 982 {
 983         unsigned long flags, vaddr, lmi;
 984         int i;
 985
 986         local_irq_save(flags);
 987         for (i = 0; i < numpages; i++, page++) {
 988                 vaddr = (unsigned long)page_address(page);
 989                 lmi = __pa(vaddr) >> PAGE_SHIFT;
 990                 if (lmi >= linear_map_hash_count)
 991                         continue;
 992                 if (enable)
 993                         kernel_map_linear_page(vaddr, lmi);
 994                 else
 995                         kernel_unmap_linear_page(vaddr, lmi);
 996         }
 997         local_irq_restore(flags);
 998 }
 999 #endif /* CONFIG_DEBUG_PAGEALLOC */