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1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
7 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
8 * Copyright (C) 1996 Paul Mackerras
9 * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com)
11 * Derived from "arch/i386/mm/init.c"
12 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
15 #include <linux/export.h>
16 #include <linux/sched.h>
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/string.h>
20 #include <linux/gfp.h>
21 #include <linux/types.h>
23 #include <linux/stddef.h>
24 #include <linux/init.h>
25 #include <linux/memblock.h>
26 #include <linux/highmem.h>
27 #include <linux/initrd.h>
28 #include <linux/pagemap.h>
29 #include <linux/suspend.h>
30 #include <linux/hugetlb.h>
31 #include <linux/slab.h>
32 #include <linux/vmalloc.h>
33 #include <linux/memremap.h>
34 #include <linux/dma-direct.h>
36 #include <asm/pgalloc.h>
39 #include <asm/mmu_context.h>
40 #include <asm/pgtable.h>
43 #include <asm/machdep.h>
44 #include <asm/btext.h>
46 #include <asm/sections.h>
47 #include <asm/sparsemem.h>
49 #include <asm/fixmap.h>
50 #include <asm/swiotlb.h>
52 #include <asm/kasan.h>
54 #include <mm/mmu_decl.h>
56 #ifndef CPU_FTR_COHERENT_ICACHE
57 #define CPU_FTR_COHERENT_ICACHE 0 /* XXX for now */
58 #define CPU_FTR_NOEXECUTE 0
61 unsigned long long memory_limit
;
62 bool init_mem_is_free
;
66 EXPORT_SYMBOL(kmap_pte
);
68 EXPORT_SYMBOL(kmap_prot
);
71 pgprot_t
phys_mem_access_prot(struct file
*file
, unsigned long pfn
,
72 unsigned long size
, pgprot_t vma_prot
)
74 if (ppc_md
.phys_mem_access_prot
)
75 return ppc_md
.phys_mem_access_prot(file
, pfn
, size
, vma_prot
);
77 if (!page_is_ram(pfn
))
78 vma_prot
= pgprot_noncached(vma_prot
);
82 EXPORT_SYMBOL(phys_mem_access_prot
);
84 #ifdef CONFIG_MEMORY_HOTPLUG
87 int memory_add_physaddr_to_nid(u64 start
)
89 return hot_add_scn_to_nid(start
);
93 int __weak
create_section_mapping(unsigned long start
, unsigned long end
,
94 int nid
, pgprot_t prot
)
99 int __weak
remove_section_mapping(unsigned long start
, unsigned long end
)
104 #define FLUSH_CHUNK_SIZE SZ_1G
106 * flush_dcache_range_chunked(): Write any modified data cache blocks out to
107 * memory and invalidate them, in chunks of up to FLUSH_CHUNK_SIZE
108 * Does not invalidate the corresponding instruction cache blocks.
110 * @start: the start address
111 * @stop: the stop address (exclusive)
112 * @chunk: the max size of the chunks
114 static void flush_dcache_range_chunked(unsigned long start
, unsigned long stop
,
119 for (i
= start
; i
< stop
; i
+= chunk
) {
120 flush_dcache_range(i
, min(stop
, i
+ chunk
));
125 int __ref
arch_add_memory(int nid
, u64 start
, u64 size
,
126 struct mhp_params
*params
)
128 unsigned long start_pfn
= start
>> PAGE_SHIFT
;
129 unsigned long nr_pages
= size
>> PAGE_SHIFT
;
132 resize_hpt_for_hotplug(memblock_phys_mem_size());
134 start
= (unsigned long)__va(start
);
135 rc
= create_section_mapping(start
, start
+ size
, nid
,
138 pr_warn("Unable to create mapping for hot added memory 0x%llx..0x%llx: %d\n",
139 start
, start
+ size
, rc
);
143 return __add_pages(nid
, start_pfn
, nr_pages
, params
);
146 void __ref
arch_remove_memory(int nid
, u64 start
, u64 size
,
147 struct vmem_altmap
*altmap
)
149 unsigned long start_pfn
= start
>> PAGE_SHIFT
;
150 unsigned long nr_pages
= size
>> PAGE_SHIFT
;
153 __remove_pages(start_pfn
, nr_pages
, altmap
);
155 /* Remove htab bolted mappings for this section of memory */
156 start
= (unsigned long)__va(start
);
157 flush_dcache_range_chunked(start
, start
+ size
, FLUSH_CHUNK_SIZE
);
159 ret
= remove_section_mapping(start
, start
+ size
);
162 /* Ensure all vmalloc mappings are flushed in case they also
163 * hit that section of memory
167 if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC
)
168 pr_warn("Hash collision while resizing HPT\n");
172 #ifndef CONFIG_NEED_MULTIPLE_NODES
173 void __init
mem_topology_setup(void)
175 max_low_pfn
= max_pfn
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
176 min_low_pfn
= MEMORY_START
>> PAGE_SHIFT
;
177 #ifdef CONFIG_HIGHMEM
178 max_low_pfn
= lowmem_end_addr
>> PAGE_SHIFT
;
181 /* Place all memblock_regions in the same node and merge contiguous
184 memblock_set_node(0, PHYS_ADDR_MAX
, &memblock
.memory
, 0);
187 void __init
initmem_init(void)
189 /* XXX need to clip this if using highmem? */
190 sparse_memory_present_with_active_regions(0);
194 /* mark pages that don't exist as nosave */
195 static int __init
mark_nonram_nosave(void)
197 struct memblock_region
*reg
, *prev
= NULL
;
199 for_each_memblock(memory
, reg
) {
201 memblock_region_memory_end_pfn(prev
) < memblock_region_memory_base_pfn(reg
))
202 register_nosave_region(memblock_region_memory_end_pfn(prev
),
203 memblock_region_memory_base_pfn(reg
));
208 #else /* CONFIG_NEED_MULTIPLE_NODES */
209 static int __init
mark_nonram_nosave(void)
218 * We setup ZONE_DMA to be 31-bits on all platforms and ZONE_NORMAL to be
219 * everything else. GFP_DMA32 page allocations automatically fall back to
222 * By using 31-bit unconditionally, we can exploit zone_dma_bits to inform the
223 * generic DMA mapping code. 32-bit only devices (if not handled by an IOMMU
224 * anyway) will take a first dip into ZONE_NORMAL and get otherwise served by
227 static unsigned long max_zone_pfns
[MAX_NR_ZONES
];
230 * paging_init() sets up the page tables - in fact we've already done this.
232 void __init
paging_init(void)
234 unsigned long long total_ram
= memblock_phys_mem_size();
235 phys_addr_t top_of_ram
= memblock_end_of_DRAM();
237 #ifdef CONFIG_HIGHMEM
238 unsigned long v
= __fix_to_virt(FIX_KMAP_END
);
239 unsigned long end
= __fix_to_virt(FIX_KMAP_BEGIN
);
241 for (; v
< end
; v
+= PAGE_SIZE
)
242 map_kernel_page(v
, 0, __pgprot(0)); /* XXX gross */
244 map_kernel_page(PKMAP_BASE
, 0, __pgprot(0)); /* XXX gross */
245 pkmap_page_table
= virt_to_kpte(PKMAP_BASE
);
247 kmap_pte
= virt_to_kpte(__fix_to_virt(FIX_KMAP_BEGIN
));
248 kmap_prot
= PAGE_KERNEL
;
249 #endif /* CONFIG_HIGHMEM */
251 printk(KERN_DEBUG
"Top of RAM: 0x%llx, Total RAM: 0x%llx\n",
252 (unsigned long long)top_of_ram
, total_ram
);
253 printk(KERN_DEBUG
"Memory hole size: %ldMB\n",
254 (long int)((top_of_ram
- total_ram
) >> 20));
257 * Allow 30-bit DMA for very limited Broadcom wifi chips on many
260 if (IS_ENABLED(CONFIG_PPC32
))
265 #ifdef CONFIG_ZONE_DMA
266 max_zone_pfns
[ZONE_DMA
] = min(max_low_pfn
,
267 1UL << (zone_dma_bits
- PAGE_SHIFT
));
269 max_zone_pfns
[ZONE_NORMAL
] = max_low_pfn
;
270 #ifdef CONFIG_HIGHMEM
271 max_zone_pfns
[ZONE_HIGHMEM
] = max_pfn
;
274 free_area_init_nodes(max_zone_pfns
);
276 mark_nonram_nosave();
279 void __init
mem_init(void)
282 * book3s is limited to 16 page sizes due to encoding this in
283 * a 4-bit field for slices.
285 BUILD_BUG_ON(MMU_PAGE_COUNT
> 16);
287 #ifdef CONFIG_SWIOTLB
289 * Some platforms (e.g. 85xx) limit DMA-able memory way below
290 * 4G. We force memblock to bottom-up mode to ensure that the
291 * memory allocated in swiotlb_init() is DMA-able.
292 * As it's the last memblock allocation, no need to reset it
295 memblock_set_bottom_up(true);
299 high_memory
= (void *) __va(max_low_pfn
* PAGE_SIZE
);
300 set_max_mapnr(max_pfn
);
306 #ifdef CONFIG_HIGHMEM
308 unsigned long pfn
, highmem_mapnr
;
310 highmem_mapnr
= lowmem_end_addr
>> PAGE_SHIFT
;
311 for (pfn
= highmem_mapnr
; pfn
< max_mapnr
; ++pfn
) {
312 phys_addr_t paddr
= (phys_addr_t
)pfn
<< PAGE_SHIFT
;
313 struct page
*page
= pfn_to_page(pfn
);
314 if (!memblock_is_reserved(paddr
))
315 free_highmem_page(page
);
318 #endif /* CONFIG_HIGHMEM */
320 #if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP)
322 * If smp is enabled, next_tlbcam_idx is initialized in the cpu up
323 * functions.... do it here for the non-smp case.
325 per_cpu(next_tlbcam_idx
, smp_processor_id()) =
326 (mfspr(SPRN_TLB1CFG
) & TLBnCFG_N_ENTRY
) - 1;
329 mem_init_print_info(NULL
);
331 pr_info("Kernel virtual memory layout:\n");
333 pr_info(" * 0x%08lx..0x%08lx : kasan shadow mem\n",
334 KASAN_SHADOW_START
, KASAN_SHADOW_END
);
336 pr_info(" * 0x%08lx..0x%08lx : fixmap\n", FIXADDR_START
, FIXADDR_TOP
);
337 #ifdef CONFIG_HIGHMEM
338 pr_info(" * 0x%08lx..0x%08lx : highmem PTEs\n",
339 PKMAP_BASE
, PKMAP_ADDR(LAST_PKMAP
));
340 #endif /* CONFIG_HIGHMEM */
341 if (ioremap_bot
!= IOREMAP_TOP
)
342 pr_info(" * 0x%08lx..0x%08lx : early ioremap\n",
343 ioremap_bot
, IOREMAP_TOP
);
344 pr_info(" * 0x%08lx..0x%08lx : vmalloc & ioremap\n",
345 VMALLOC_START
, VMALLOC_END
);
346 #endif /* CONFIG_PPC32 */
349 void free_initmem(void)
351 ppc_md
.progress
= ppc_printk_progress
;
353 init_mem_is_free
= true;
354 free_initmem_default(POISON_FREE_INITMEM
);
358 * flush_coherent_icache() - if a CPU has a coherent icache, flush it
359 * @addr: The base address to use (can be any valid address, the whole cache will be flushed)
360 * Return true if the cache was flushed, false otherwise
362 static inline bool flush_coherent_icache(unsigned long addr
)
365 * For a snooping icache, we still need a dummy icbi to purge all the
366 * prefetched instructions from the ifetch buffers. We also need a sync
367 * before the icbi to order the the actual stores to memory that might
368 * have modified instructions with the icbi.
370 if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE
)) {
372 allow_read_from_user((const void __user
*)addr
, L1_CACHE_BYTES
);
374 prevent_read_from_user((const void __user
*)addr
, L1_CACHE_BYTES
);
384 * invalidate_icache_range() - Flush the icache by issuing icbi across an address range
385 * @start: the start address
386 * @stop: the stop address (exclusive)
388 static void invalidate_icache_range(unsigned long start
, unsigned long stop
)
390 unsigned long shift
= l1_icache_shift();
391 unsigned long bytes
= l1_icache_bytes();
392 char *addr
= (char *)(start
& ~(bytes
- 1));
393 unsigned long size
= stop
- (unsigned long)addr
+ (bytes
- 1);
396 for (i
= 0; i
< size
>> shift
; i
++, addr
+= bytes
)
404 * flush_icache_range: Write any modified data cache blocks out to memory
405 * and invalidate the corresponding blocks in the instruction cache
407 * Generic code will call this after writing memory, before executing from it.
409 * @start: the start address
410 * @stop: the stop address (exclusive)
412 void flush_icache_range(unsigned long start
, unsigned long stop
)
414 if (flush_coherent_icache(start
))
417 clean_dcache_range(start
, stop
);
419 if (IS_ENABLED(CONFIG_44x
)) {
421 * Flash invalidate on 44x because we are passed kmapped
422 * addresses and this doesn't work for userspace pages due to
423 * the virtually tagged icache.
425 iccci((void *)start
);
429 invalidate_icache_range(start
, stop
);
431 EXPORT_SYMBOL(flush_icache_range
);
433 #if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
435 * flush_dcache_icache_phys() - Flush a page by it's physical address
436 * @physaddr: the physical address of the page
438 static void flush_dcache_icache_phys(unsigned long physaddr
)
440 unsigned long bytes
= l1_dcache_bytes();
441 unsigned long nb
= PAGE_SIZE
/ bytes
;
442 unsigned long addr
= physaddr
& PAGE_MASK
;
443 unsigned long msr
, msr0
;
444 unsigned long loop1
= addr
, loop2
= addr
;
447 msr
= msr0
& ~MSR_DR
;
449 * This must remain as ASM to prevent potential memory accesses
450 * while the data MMU is disabled
457 " addi %0, %0, %4;\n"
462 " addi %1, %1, %4;\n"
467 : "+&r" (loop1
), "+&r" (loop2
)
468 : "r" (nb
), "r" (msr
), "i" (bytes
), "r" (msr0
)
471 #endif // !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
474 * This is called when a page has been modified by the kernel.
475 * It just marks the page as not i-cache clean. We do the i-cache
476 * flush later when the page is given to a user process, if necessary.
478 void flush_dcache_page(struct page
*page
)
480 if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE
))
482 /* avoid an atomic op if possible */
483 if (test_bit(PG_arch_1
, &page
->flags
))
484 clear_bit(PG_arch_1
, &page
->flags
);
486 EXPORT_SYMBOL(flush_dcache_page
);
488 void flush_dcache_icache_page(struct page
*page
)
490 #ifdef CONFIG_HUGETLB_PAGE
491 if (PageCompound(page
)) {
492 flush_dcache_icache_hugepage(page
);
496 #if defined(CONFIG_PPC_8xx) || defined(CONFIG_PPC64)
497 /* On 8xx there is no need to kmap since highmem is not supported */
498 __flush_dcache_icache(page_address(page
));
500 if (IS_ENABLED(CONFIG_BOOKE
) || sizeof(phys_addr_t
) > sizeof(void *)) {
501 void *start
= kmap_atomic(page
);
502 __flush_dcache_icache(start
);
503 kunmap_atomic(start
);
505 unsigned long addr
= page_to_pfn(page
) << PAGE_SHIFT
;
507 if (flush_coherent_icache(addr
))
509 flush_dcache_icache_phys(addr
);
513 EXPORT_SYMBOL(flush_dcache_icache_page
);
516 * __flush_dcache_icache(): Flush a particular page from the data cache to RAM.
517 * Note: this is necessary because the instruction cache does *not*
518 * snoop from the data cache.
520 * @page: the address of the page to flush
522 void __flush_dcache_icache(void *p
)
524 unsigned long addr
= (unsigned long)p
;
526 if (flush_coherent_icache(addr
))
529 clean_dcache_range(addr
, addr
+ PAGE_SIZE
);
532 * We don't flush the icache on 44x. Those have a virtual icache and we
533 * don't have access to the virtual address here (it's not the page
534 * vaddr but where it's mapped in user space). The flushing of the
535 * icache on these is handled elsewhere, when a change in the address
536 * space occurs, before returning to user space.
539 if (cpu_has_feature(MMU_FTR_TYPE_44x
))
542 invalidate_icache_range(addr
, addr
+ PAGE_SIZE
);
545 void clear_user_page(void *page
, unsigned long vaddr
, struct page
*pg
)
550 * We shouldn't have to do this, but some versions of glibc
551 * require it (ld.so assumes zero filled pages are icache clean)
554 flush_dcache_page(pg
);
556 EXPORT_SYMBOL(clear_user_page
);
558 void copy_user_page(void *vto
, void *vfrom
, unsigned long vaddr
,
561 copy_page(vto
, vfrom
);
564 * We should be able to use the following optimisation, however
565 * there are two problems.
566 * Firstly a bug in some versions of binutils meant PLT sections
567 * were not marked executable.
568 * Secondly the first word in the GOT section is blrl, used
569 * to establish the GOT address. Until recently the GOT was
570 * not marked executable.
574 if (!vma
->vm_file
&& ((vma
->vm_flags
& VM_EXEC
) == 0))
578 flush_dcache_page(pg
);
581 void flush_icache_user_range(struct vm_area_struct
*vma
, struct page
*page
,
582 unsigned long addr
, int len
)
586 maddr
= (unsigned long) kmap(page
) + (addr
& ~PAGE_MASK
);
587 flush_icache_range(maddr
, maddr
+ len
);
590 EXPORT_SYMBOL(flush_icache_user_range
);
593 * System memory should not be in /proc/iomem but various tools expect it
596 static int __init
add_system_ram_resources(void)
598 struct memblock_region
*reg
;
600 for_each_memblock(memory
, reg
) {
601 struct resource
*res
;
602 unsigned long base
= reg
->base
;
603 unsigned long size
= reg
->size
;
605 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
609 res
->name
= "System RAM";
611 res
->end
= base
+ size
- 1;
612 res
->flags
= IORESOURCE_SYSTEM_RAM
| IORESOURCE_BUSY
;
613 WARN_ON(request_resource(&iomem_resource
, res
) < 0);
619 subsys_initcall(add_system_ram_resources
);
621 #ifdef CONFIG_STRICT_DEVMEM
623 * devmem_is_allowed(): check to see if /dev/mem access to a certain address
624 * is valid. The argument is a physical page number.
626 * Access has to be given to non-kernel-ram areas as well, these contain the
627 * PCI mmio resources as well as potential bios/acpi data regions.
629 int devmem_is_allowed(unsigned long pfn
)
631 if (page_is_rtas_user_buf(pfn
))
633 if (iomem_is_exclusive(PFN_PHYS(pfn
)))
635 if (!page_is_ram(pfn
))
639 #endif /* CONFIG_STRICT_DEVMEM */
642 * This is defined in kernel/resource.c but only powerpc needs to export it, for
643 * the EHEA driver. Drop this when drivers/net/ethernet/ibm/ehea is removed.
645 EXPORT_SYMBOL_GPL(walk_system_ram_range
);