arch/powerpc/mm/pgtable-radix.c

   1 /*
   2  * Page table handling routines for radix page table.
   3  *
   4  * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/sched/mm.h>
  12 #include <linux/memblock.h>
  13 #include <linux/of_fdt.h>
  14 #include <linux/mm.h>
  15
  16 #include <asm/pgtable.h>
  17 #include <asm/pgalloc.h>
  18 #include <asm/dma.h>
  19 #include <asm/machdep.h>
  20 #include <asm/mmu.h>
  21 #include <asm/firmware.h>
  22 #include <asm/powernv.h>
  23 #include <asm/sections.h>
  24 #include <asm/trace.h>
  25
  26 #include <trace/events/thp.h>
  27
  28 unsigned int mmu_pid_bits;
  29 unsigned int mmu_base_pid;
  30
  31 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
  32                                          unsigned long table_size)
  33 {
  34         unsigned long patb1 = base | table_size | PATB_GR;
  35
  36         partition_tb->patb1 = cpu_to_be64(patb1);
  37         return 0;
  38 }
  39
  40 static __ref void *early_alloc_pgtable(unsigned long size)
  41 {
  42         void *pt;
  43
  44         pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
  45         memset(pt, 0, size);
  46
  47         return pt;
  48 }
  49
  50 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
  51                           pgprot_t flags,
  52                           unsigned int map_page_size)
  53 {
  54         pgd_t *pgdp;
  55         pud_t *pudp;
  56         pmd_t *pmdp;
  57         pte_t *ptep;
  58         /*
  59          * Make sure task size is correct as per the max adddr
  60          */
  61         BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
  62         if (slab_is_available()) {
  63                 pgdp = pgd_offset_k(ea);
  64                 pudp = pud_alloc(&init_mm, pgdp, ea);
  65                 if (!pudp)
  66                         return -ENOMEM;
  67                 if (map_page_size == PUD_SIZE) {
  68                         ptep = (pte_t *)pudp;
  69                         goto set_the_pte;
  70                 }
  71                 pmdp = pmd_alloc(&init_mm, pudp, ea);
  72                 if (!pmdp)
  73                         return -ENOMEM;
  74                 if (map_page_size == PMD_SIZE) {
  75                         ptep = pmdp_ptep(pmdp);
  76                         goto set_the_pte;
  77                 }
  78                 ptep = pte_alloc_kernel(pmdp, ea);
  79                 if (!ptep)
  80                         return -ENOMEM;
  81         } else {
  82                 pgdp = pgd_offset_k(ea);
  83                 if (pgd_none(*pgdp)) {
  84                         pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
  85                         BUG_ON(pudp == NULL);
  86                         pgd_populate(&init_mm, pgdp, pudp);
  87                 }
  88                 pudp = pud_offset(pgdp, ea);
  89                 if (map_page_size == PUD_SIZE) {
  90                         ptep = (pte_t *)pudp;
  91                         goto set_the_pte;
  92                 }
  93                 if (pud_none(*pudp)) {
  94                         pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
  95                         BUG_ON(pmdp == NULL);
  96                         pud_populate(&init_mm, pudp, pmdp);
  97                 }
  98                 pmdp = pmd_offset(pudp, ea);
  99                 if (map_page_size == PMD_SIZE) {
 100                         ptep = pmdp_ptep(pmdp);
 101                         goto set_the_pte;
 102                 }
 103                 if (!pmd_present(*pmdp)) {
 104                         ptep = early_alloc_pgtable(PAGE_SIZE);
 105                         BUG_ON(ptep == NULL);
 106                         pmd_populate_kernel(&init_mm, pmdp, ptep);
 107                 }
 108                 ptep = pte_offset_kernel(pmdp, ea);
 109         }
 110
 111 set_the_pte:
 112         set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
 113         smp_wmb();
 114         return 0;
 115 }
 116
 117 #ifdef CONFIG_STRICT_KERNEL_RWX
 118 void radix__change_memory_range(unsigned long start, unsigned long end,
 119                                 unsigned long clear)
 120 {
 121         unsigned long idx;
 122         pgd_t *pgdp;
 123         pud_t *pudp;
 124         pmd_t *pmdp;
 125         pte_t *ptep;
 126
 127         start = ALIGN_DOWN(start, PAGE_SIZE);
 128         end = PAGE_ALIGN(end); // aligns up
 129
 130         pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
 131                  start, end, clear);
 132
 133         for (idx = start; idx < end; idx += PAGE_SIZE) {
 134                 pgdp = pgd_offset_k(idx);
 135                 pudp = pud_alloc(&init_mm, pgdp, idx);
 136                 if (!pudp)
 137                         continue;
 138                 if (pud_huge(*pudp)) {
 139                         ptep = (pte_t *)pudp;
 140                         goto update_the_pte;
 141                 }
 142                 pmdp = pmd_alloc(&init_mm, pudp, idx);
 143                 if (!pmdp)
 144                         continue;
 145                 if (pmd_huge(*pmdp)) {
 146                         ptep = pmdp_ptep(pmdp);
 147                         goto update_the_pte;
 148                 }
 149                 ptep = pte_alloc_kernel(pmdp, idx);
 150                 if (!ptep)
 151                         continue;
 152 update_the_pte:
 153                 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
 154         }
 155
 156         radix__flush_tlb_kernel_range(start, end);
 157 }
 158
 159 void radix__mark_rodata_ro(void)
 160 {
 161         unsigned long start, end;
 162
 163         start = (unsigned long)_stext;
 164         end = (unsigned long)__init_begin;
 165
 166         radix__change_memory_range(start, end, _PAGE_WRITE);
 167 }
 168
 169 void radix__mark_initmem_nx(void)
 170 {
 171         unsigned long start = (unsigned long)__init_begin;
 172         unsigned long end = (unsigned long)__init_end;
 173
 174         radix__change_memory_range(start, end, _PAGE_EXEC);
 175 }
 176 #endif /* CONFIG_STRICT_KERNEL_RWX */
 177
 178 static inline void __meminit print_mapping(unsigned long start,
 179                                            unsigned long end,
 180                                            unsigned long size)
 181 {
 182         if (end <= start)
 183                 return;
 184
 185         pr_info("Mapped range 0x%lx - 0x%lx with 0x%lx\n", start, end, size);
 186 }
 187
 188 static int __meminit create_physical_mapping(unsigned long start,
 189                                              unsigned long end)
 190 {
 191         unsigned long vaddr, addr, mapping_size = 0;
 192         pgprot_t prot;
 193         unsigned long max_mapping_size;
 194 #ifdef CONFIG_STRICT_KERNEL_RWX
 195         int split_text_mapping = 1;
 196 #else
 197         int split_text_mapping = 0;
 198 #endif
 199
 200         start = _ALIGN_UP(start, PAGE_SIZE);
 201         for (addr = start; addr < end; addr += mapping_size) {
 202                 unsigned long gap, previous_size;
 203                 int rc;
 204
 205                 gap = end - addr;
 206                 previous_size = mapping_size;
 207                 max_mapping_size = PUD_SIZE;
 208
 209 retry:
 210                 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
 211                     mmu_psize_defs[MMU_PAGE_1G].shift &&
 212                     PUD_SIZE <= max_mapping_size)
 213                         mapping_size = PUD_SIZE;
 214                 else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
 215                          mmu_psize_defs[MMU_PAGE_2M].shift)
 216                         mapping_size = PMD_SIZE;
 217                 else
 218                         mapping_size = PAGE_SIZE;
 219
 220                 if (split_text_mapping && (mapping_size == PUD_SIZE) &&
 221                         (addr <= __pa_symbol(__init_begin)) &&
 222                         (addr + mapping_size) >= __pa_symbol(_stext)) {
 223                         max_mapping_size = PMD_SIZE;
 224                         goto retry;
 225                 }
 226
 227                 if (split_text_mapping && (mapping_size == PMD_SIZE) &&
 228                     (addr <= __pa_symbol(__init_begin)) &&
 229                     (addr + mapping_size) >= __pa_symbol(_stext))
 230                         mapping_size = PAGE_SIZE;
 231
 232                 if (mapping_size != previous_size) {
 233                         print_mapping(start, addr, previous_size);
 234                         start = addr;
 235                 }
 236
 237                 vaddr = (unsigned long)__va(addr);
 238
 239                 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
 240                     overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size))
 241                         prot = PAGE_KERNEL_X;
 242                 else
 243                         prot = PAGE_KERNEL;
 244
 245                 rc = radix__map_kernel_page(vaddr, addr, prot, mapping_size);
 246                 if (rc)
 247                         return rc;
 248         }
 249
 250         print_mapping(start, addr, mapping_size);
 251         return 0;
 252 }
 253
 254 static void __init radix_init_pgtable(void)
 255 {
 256         unsigned long rts_field;
 257         struct memblock_region *reg;
 258
 259         /* We don't support slb for radix */
 260         mmu_slb_size = 0;
 261         /*
 262          * Create the linear mapping, using standard page size for now
 263          */
 264         for_each_memblock(memory, reg)
 265                 WARN_ON(create_physical_mapping(reg->base,
 266                                                 reg->base + reg->size));
 267
 268         /* Find out how many PID bits are supported */
 269         if (cpu_has_feature(CPU_FTR_HVMODE)) {
 270                 if (!mmu_pid_bits)
 271                         mmu_pid_bits = 20;
 272 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 273                 /*
 274                  * When KVM is possible, we only use the top half of the
 275                  * PID space to avoid collisions between host and guest PIDs
 276                  * which can cause problems due to prefetch when exiting the
 277                  * guest with AIL=3
 278                  */
 279                 mmu_base_pid = 1 << (mmu_pid_bits - 1);
 280 #else
 281                 mmu_base_pid = 1;
 282 #endif
 283         } else {
 284                 /* The guest uses the bottom half of the PID space */
 285                 if (!mmu_pid_bits)
 286                         mmu_pid_bits = 19;
 287                 mmu_base_pid = 1;
 288         }
 289
 290         /*
 291          * Allocate Partition table and process table for the
 292          * host.
 293          */
 294         BUG_ON(PRTB_SIZE_SHIFT > 36);
 295         process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
 296         /*
 297          * Fill in the process table.
 298          */
 299         rts_field = radix__get_tree_size();
 300         process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
 301         /*
 302          * Fill in the partition table. We are suppose to use effective address
 303          * of process table here. But our linear mapping also enable us to use
 304          * physical address here.
 305          */
 306         register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
 307         pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
 308         asm volatile("ptesync" : : : "memory");
 309         asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
 310                      "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
 311         asm volatile("eieio; tlbsync; ptesync" : : : "memory");
 312         trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
 313 }
 314
 315 static void __init radix_init_partition_table(void)
 316 {
 317         unsigned long rts_field, dw0;
 318
 319         mmu_partition_table_init();
 320         rts_field = radix__get_tree_size();
 321         dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
 322         mmu_partition_table_set_entry(0, dw0, 0);
 323
 324         pr_info("Initializing Radix MMU\n");
 325         pr_info("Partition table %p\n", partition_tb);
 326 }
 327
 328 void __init radix_init_native(void)
 329 {
 330         register_process_table = native_register_process_table;
 331 }
 332
 333 static int __init get_idx_from_shift(unsigned int shift)
 334 {
 335         int idx = -1;
 336
 337         switch (shift) {
 338         case 0xc:
 339                 idx = MMU_PAGE_4K;
 340                 break;
 341         case 0x10:
 342                 idx = MMU_PAGE_64K;
 343                 break;
 344         case 0x15:
 345                 idx = MMU_PAGE_2M;
 346                 break;
 347         case 0x1e:
 348                 idx = MMU_PAGE_1G;
 349                 break;
 350         }
 351         return idx;
 352 }
 353
 354 static int __init radix_dt_scan_page_sizes(unsigned long node,
 355                                            const char *uname, int depth,
 356                                            void *data)
 357 {
 358         int size = 0;
 359         int shift, idx;
 360         unsigned int ap;
 361         const __be32 *prop;
 362         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 363
 364         /* We are scanning "cpu" nodes only */
 365         if (type == NULL || strcmp(type, "cpu") != 0)
 366                 return 0;
 367
 368         /* Find MMU PID size */
 369         prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
 370         if (prop && size == 4)
 371                 mmu_pid_bits = be32_to_cpup(prop);
 372
 373         /* Grab page size encodings */
 374         prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
 375         if (!prop)
 376                 return 0;
 377
 378         pr_info("Page sizes from device-tree:\n");
 379         for (; size >= 4; size -= 4, ++prop) {
 380
 381                 struct mmu_psize_def *def;
 382
 383                 /* top 3 bit is AP encoding */
 384                 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
 385                 ap = be32_to_cpu(prop[0]) >> 29;
 386                 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
 387
 388                 idx = get_idx_from_shift(shift);
 389                 if (idx < 0)
 390                         continue;
 391
 392                 def = &mmu_psize_defs[idx];
 393                 def->shift = shift;
 394                 def->ap  = ap;
 395         }
 396
 397         /* needed ? */
 398         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
 399         return 1;
 400 }
 401
 402 void __init radix__early_init_devtree(void)
 403 {
 404         int rc;
 405
 406         /*
 407          * Try to find the available page sizes in the device-tree
 408          */
 409         rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
 410         if (rc != 0)  /* Found */
 411                 goto found;
 412         /*
 413          * let's assume we have page 4k and 64k support
 414          */
 415         mmu_psize_defs[MMU_PAGE_4K].shift = 12;
 416         mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
 417
 418         mmu_psize_defs[MMU_PAGE_64K].shift = 16;
 419         mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
 420 found:
 421 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 422         if (mmu_psize_defs[MMU_PAGE_2M].shift) {
 423                 /*
 424                  * map vmemmap using 2M if available
 425                  */
 426                 mmu_vmemmap_psize = MMU_PAGE_2M;
 427         }
 428 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
 429         return;
 430 }
 431
 432 static void update_hid_for_radix(void)
 433 {
 434         unsigned long hid0;
 435         unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
 436
 437         asm volatile("ptesync": : :"memory");
 438         /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
 439         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 440                      : : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
 441         /* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
 442         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 443                      : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
 444         asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
 445         trace_tlbie(0, 0, rb, 0, 2, 0, 1);
 446         trace_tlbie(0, 0, rb, 0, 2, 1, 1);
 447
 448         /*
 449          * now switch the HID
 450          */
 451         hid0  = mfspr(SPRN_HID0);
 452         hid0 |= HID0_POWER9_RADIX;
 453         mtspr(SPRN_HID0, hid0);
 454         asm volatile("isync": : :"memory");
 455
 456         /* Wait for it to happen */
 457         while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
 458                 cpu_relax();
 459 }
 460
 461 static void radix_init_amor(void)
 462 {
 463         /*
 464         * In HV mode, we init AMOR (Authority Mask Override Register) so that
 465         * the hypervisor and guest can setup IAMR (Instruction Authority Mask
 466         * Register), enable key 0 and set it to 1.
 467         *
 468         * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
 469         */
 470         mtspr(SPRN_AMOR, (3ul << 62));
 471 }
 472
 473 static void radix_init_iamr(void)
 474 {
 475         unsigned long iamr;
 476
 477         /*
 478          * The IAMR should set to 0 on DD1.
 479          */
 480         if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 481                 iamr = 0;
 482         else
 483                 iamr = (1ul << 62);
 484
 485         /*
 486          * Radix always uses key0 of the IAMR to determine if an access is
 487          * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
 488          * fetch.
 489          */
 490         mtspr(SPRN_IAMR, iamr);
 491 }
 492
 493 void __init radix__early_init_mmu(void)
 494 {
 495         unsigned long lpcr;
 496
 497 #ifdef CONFIG_PPC_64K_PAGES
 498         /* PAGE_SIZE mappings */
 499         mmu_virtual_psize = MMU_PAGE_64K;
 500 #else
 501         mmu_virtual_psize = MMU_PAGE_4K;
 502 #endif
 503
 504 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 505         /* vmemmap mapping */
 506         mmu_vmemmap_psize = mmu_virtual_psize;
 507 #endif
 508         /*
 509          * initialize page table size
 510          */
 511         __pte_index_size = RADIX_PTE_INDEX_SIZE;
 512         __pmd_index_size = RADIX_PMD_INDEX_SIZE;
 513         __pud_index_size = RADIX_PUD_INDEX_SIZE;
 514         __pgd_index_size = RADIX_PGD_INDEX_SIZE;
 515         __pmd_cache_index = RADIX_PMD_INDEX_SIZE;
 516         __pte_table_size = RADIX_PTE_TABLE_SIZE;
 517         __pmd_table_size = RADIX_PMD_TABLE_SIZE;
 518         __pud_table_size = RADIX_PUD_TABLE_SIZE;
 519         __pgd_table_size = RADIX_PGD_TABLE_SIZE;
 520
 521         __pmd_val_bits = RADIX_PMD_VAL_BITS;
 522         __pud_val_bits = RADIX_PUD_VAL_BITS;
 523         __pgd_val_bits = RADIX_PGD_VAL_BITS;
 524
 525         __kernel_virt_start = RADIX_KERN_VIRT_START;
 526         __kernel_virt_size = RADIX_KERN_VIRT_SIZE;
 527         __vmalloc_start = RADIX_VMALLOC_START;
 528         __vmalloc_end = RADIX_VMALLOC_END;
 529         vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
 530         ioremap_bot = IOREMAP_BASE;
 531
 532 #ifdef CONFIG_PCI
 533         pci_io_base = ISA_IO_BASE;
 534 #endif
 535
 536         /*
 537          * For now radix also use the same frag size
 538          */
 539         __pte_frag_nr = H_PTE_FRAG_NR;
 540         __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
 541
 542         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 543                 radix_init_native();
 544                 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 545                         update_hid_for_radix();
 546                 lpcr = mfspr(SPRN_LPCR);
 547                 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
 548                 radix_init_partition_table();
 549                 radix_init_amor();
 550         } else {
 551                 radix_init_pseries();
 552         }
 553
 554         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 555
 556         radix_init_iamr();
 557         radix_init_pgtable();
 558 }
 559
 560 void radix__early_init_mmu_secondary(void)
 561 {
 562         unsigned long lpcr;
 563         /*
 564          * update partition table control register and UPRT
 565          */
 566         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 567
 568                 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 569                         update_hid_for_radix();
 570
 571                 lpcr = mfspr(SPRN_LPCR);
 572                 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
 573
 574                 mtspr(SPRN_PTCR,
 575                       __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
 576                 radix_init_amor();
 577         }
 578         radix_init_iamr();
 579 }
 580
 581 void radix__mmu_cleanup_all(void)
 582 {
 583         unsigned long lpcr;
 584
 585         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 586                 lpcr = mfspr(SPRN_LPCR);
 587                 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
 588                 mtspr(SPRN_PTCR, 0);
 589                 powernv_set_nmmu_ptcr(0);
 590                 radix__flush_tlb_all();
 591         }
 592 }
 593
 594 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 595                                 phys_addr_t first_memblock_size)
 596 {
 597         /* We don't currently support the first MEMBLOCK not mapping 0
 598          * physical on those processors
 599          */
 600         BUG_ON(first_memblock_base != 0);
 601         /*
 602          * We limit the allocation that depend on ppc64_rma_size
 603          * to first_memblock_size. We also clamp it to 1GB to
 604          * avoid some funky things such as RTAS bugs.
 605          *
 606          * On radix config we really don't have a limitation
 607          * on real mode access. But keeping it as above works
 608          * well enough.
 609          */
 610         ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
 611         /*
 612          * Finally limit subsequent allocations. We really don't want
 613          * to limit the memblock allocations to rma_size. FIXME!! should
 614          * we even limit at all ?
 615          */
 616         memblock_set_current_limit(first_memblock_base + first_memblock_size);
 617 }
 618
 619 #ifdef CONFIG_MEMORY_HOTPLUG
 620 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
 621 {
 622         pte_t *pte;
 623         int i;
 624
 625         for (i = 0; i < PTRS_PER_PTE; i++) {
 626                 pte = pte_start + i;
 627                 if (!pte_none(*pte))
 628                         return;
 629         }
 630
 631         pte_free_kernel(&init_mm, pte_start);
 632         pmd_clear(pmd);
 633 }
 634
 635 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
 636 {
 637         pmd_t *pmd;
 638         int i;
 639
 640         for (i = 0; i < PTRS_PER_PMD; i++) {
 641                 pmd = pmd_start + i;
 642                 if (!pmd_none(*pmd))
 643                         return;
 644         }
 645
 646         pmd_free(&init_mm, pmd_start);
 647         pud_clear(pud);
 648 }
 649
 650 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
 651                              unsigned long end)
 652 {
 653         unsigned long next;
 654         pte_t *pte;
 655
 656         pte = pte_start + pte_index(addr);
 657         for (; addr < end; addr = next, pte++) {
 658                 next = (addr + PAGE_SIZE) & PAGE_MASK;
 659                 if (next > end)
 660                         next = end;
 661
 662                 if (!pte_present(*pte))
 663                         continue;
 664
 665                 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
 666                         /*
 667                          * The vmemmap_free() and remove_section_mapping()
 668                          * codepaths call us with aligned addresses.
 669                          */
 670                         WARN_ONCE(1, "%s: unaligned range\n", __func__);
 671                         continue;
 672                 }
 673
 674                 pte_clear(&init_mm, addr, pte);
 675         }
 676 }
 677
 678 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
 679                              unsigned long end)
 680 {
 681         unsigned long next;
 682         pte_t *pte_base;
 683         pmd_t *pmd;
 684
 685         pmd = pmd_start + pmd_index(addr);
 686         for (; addr < end; addr = next, pmd++) {
 687                 next = pmd_addr_end(addr, end);
 688
 689                 if (!pmd_present(*pmd))
 690                         continue;
 691
 692                 if (pmd_huge(*pmd)) {
 693                         if (!IS_ALIGNED(addr, PMD_SIZE) ||
 694                             !IS_ALIGNED(next, PMD_SIZE)) {
 695                                 WARN_ONCE(1, "%s: unaligned range\n", __func__);
 696                                 continue;
 697                         }
 698
 699                         pte_clear(&init_mm, addr, (pte_t *)pmd);
 700                         continue;
 701                 }
 702
 703                 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
 704                 remove_pte_table(pte_base, addr, next);
 705                 free_pte_table(pte_base, pmd);
 706         }
 707 }
 708
 709 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
 710                              unsigned long end)
 711 {
 712         unsigned long next;
 713         pmd_t *pmd_base;
 714         pud_t *pud;
 715
 716         pud = pud_start + pud_index(addr);
 717         for (; addr < end; addr = next, pud++) {
 718                 next = pud_addr_end(addr, end);
 719
 720                 if (!pud_present(*pud))
 721                         continue;
 722
 723                 if (pud_huge(*pud)) {
 724                         if (!IS_ALIGNED(addr, PUD_SIZE) ||
 725                             !IS_ALIGNED(next, PUD_SIZE)) {
 726                                 WARN_ONCE(1, "%s: unaligned range\n", __func__);
 727                                 continue;
 728                         }
 729
 730                         pte_clear(&init_mm, addr, (pte_t *)pud);
 731                         continue;
 732                 }
 733
 734                 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
 735                 remove_pmd_table(pmd_base, addr, next);
 736                 free_pmd_table(pmd_base, pud);
 737         }
 738 }
 739
 740 static void remove_pagetable(unsigned long start, unsigned long end)
 741 {
 742         unsigned long addr, next;
 743         pud_t *pud_base;
 744         pgd_t *pgd;
 745
 746         spin_lock(&init_mm.page_table_lock);
 747
 748         for (addr = start; addr < end; addr = next) {
 749                 next = pgd_addr_end(addr, end);
 750
 751                 pgd = pgd_offset_k(addr);
 752                 if (!pgd_present(*pgd))
 753                         continue;
 754
 755                 if (pgd_huge(*pgd)) {
 756                         if (!IS_ALIGNED(addr, PGDIR_SIZE) ||
 757                             !IS_ALIGNED(next, PGDIR_SIZE)) {
 758                                 WARN_ONCE(1, "%s: unaligned range\n", __func__);
 759                                 continue;
 760                         }
 761
 762                         pte_clear(&init_mm, addr, (pte_t *)pgd);
 763                         continue;
 764                 }
 765
 766                 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
 767                 remove_pud_table(pud_base, addr, next);
 768         }
 769
 770         spin_unlock(&init_mm.page_table_lock);
 771         radix__flush_tlb_kernel_range(start, end);
 772 }
 773
 774 int __ref radix__create_section_mapping(unsigned long start, unsigned long end)
 775 {
 776         return create_physical_mapping(start, end);
 777 }
 778
 779 int radix__remove_section_mapping(unsigned long start, unsigned long end)
 780 {
 781         remove_pagetable(start, end);
 782         return 0;
 783 }
 784 #endif /* CONFIG_MEMORY_HOTPLUG */
 785
 786 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 787 int __meminit radix__vmemmap_create_mapping(unsigned long start,
 788                                       unsigned long page_size,
 789                                       unsigned long phys)
 790 {
 791         /* Create a PTE encoding */
 792         unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
 793
 794         BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
 795         return 0;
 796 }
 797
 798 #ifdef CONFIG_MEMORY_HOTPLUG
 799 void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
 800 {
 801         remove_pagetable(start, start + page_size);
 802 }
 803 #endif
 804 #endif
 805
 806 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 807
 808 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
 809                                   pmd_t *pmdp, unsigned long clr,
 810                                   unsigned long set)
 811 {
 812         unsigned long old;
 813
 814 #ifdef CONFIG_DEBUG_VM
 815         WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
 816         assert_spin_locked(&mm->page_table_lock);
 817 #endif
 818
 819         old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
 820         trace_hugepage_update(addr, old, clr, set);
 821
 822         return old;
 823 }
 824
 825 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
 826                         pmd_t *pmdp)
 827
 828 {
 829         pmd_t pmd;
 830
 831         VM_BUG_ON(address & ~HPAGE_PMD_MASK);
 832         VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
 833         VM_BUG_ON(pmd_devmap(*pmdp));
 834         /*
 835          * khugepaged calls this for normal pmd
 836          */
 837         pmd = *pmdp;
 838         pmd_clear(pmdp);
 839         /*FIXME!!  Verify whether we need this kick below */
 840         kick_all_cpus_sync();
 841         flush_tlb_range(vma, address, address + HPAGE_PMD_SIZE);
 842         return pmd;
 843 }
 844
 845 /*
 846  * For us pgtable_t is pte_t *. Inorder to save the deposisted
 847  * page table, we consider the allocated page table as a list
 848  * head. On withdraw we need to make sure we zero out the used
 849  * list_head memory area.
 850  */
 851 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
 852                                  pgtable_t pgtable)
 853 {
 854         struct list_head *lh = (struct list_head *) pgtable;
 855
 856         assert_spin_locked(pmd_lockptr(mm, pmdp));
 857
 858         /* FIFO */
 859         if (!pmd_huge_pte(mm, pmdp))
 860                 INIT_LIST_HEAD(lh);
 861         else
 862                 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
 863         pmd_huge_pte(mm, pmdp) = pgtable;
 864 }
 865
 866 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
 867 {
 868         pte_t *ptep;
 869         pgtable_t pgtable;
 870         struct list_head *lh;
 871
 872         assert_spin_locked(pmd_lockptr(mm, pmdp));
 873
 874         /* FIFO */
 875         pgtable = pmd_huge_pte(mm, pmdp);
 876         lh = (struct list_head *) pgtable;
 877         if (list_empty(lh))
 878                 pmd_huge_pte(mm, pmdp) = NULL;
 879         else {
 880                 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
 881                 list_del(lh);
 882         }
 883         ptep = (pte_t *) pgtable;
 884         *ptep = __pte(0);
 885         ptep++;
 886         *ptep = __pte(0);
 887         return pgtable;
 888 }
 889
 890
 891 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
 892                                unsigned long addr, pmd_t *pmdp)
 893 {
 894         pmd_t old_pmd;
 895         unsigned long old;
 896
 897         old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
 898         old_pmd = __pmd(old);
 899         /*
 900          * Serialize against find_linux_pte_or_hugepte which does lock-less
 901          * lookup in page tables with local interrupts disabled. For huge pages
 902          * it casts pmd_t to pte_t. Since format of pte_t is different from
 903          * pmd_t we want to prevent transit from pmd pointing to page table
 904          * to pmd pointing to huge page (and back) while interrupts are disabled.
 905          * We clear pmd to possibly replace it with page table pointer in
 906          * different code paths. So make sure we wait for the parallel
 907          * find_linux_pte_or_hugepage to finish.
 908          */
 909         kick_all_cpus_sync();
 910         return old_pmd;
 911 }
 912
 913 int radix__has_transparent_hugepage(void)
 914 {
 915         /* For radix 2M at PMD level means thp */
 916         if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
 917                 return 1;
 918         return 0;
 919 }
 920 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */