arch/powerpc/mm/slb.c

   1 /*
   2  * PowerPC64 SLB support.
   3  *
   4  * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
   5  * Based on earlier code written by:
   6  * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
   7  *    Copyright (c) 2001 Dave Engebretsen
   8  * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
   9  *
  10  *
  11  *      This program is free software; you can redistribute it and/or
  12  *      modify it under the terms of the GNU General Public License
  13  *      as published by the Free Software Foundation; either version
  14  *      2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <asm/pgtable.h>
  18 #include <asm/mmu.h>
  19 #include <asm/mmu_context.h>
  20 #include <asm/paca.h>
  21 #include <asm/cputable.h>
  22 #include <asm/cacheflush.h>
  23 #include <asm/smp.h>
  24 #include <linux/compiler.h>
  25 #include <linux/mm_types.h>
  26
  27 #include <asm/udbg.h>
  28 #include <asm/code-patching.h>
  29
  30 enum slb_index {
  31         LINEAR_INDEX    = 0, /* Kernel linear map  (0xc000000000000000) */
  32         VMALLOC_INDEX   = 1, /* Kernel virtual map (0xd000000000000000) */
  33         KSTACK_INDEX    = 2, /* Kernel stack map */
  34 };
  35
  36 extern void slb_allocate_realmode(unsigned long ea);
  37
  38 static void slb_allocate(unsigned long ea)
  39 {
  40         /* Currently, we do real mode for all SLBs including user, but
  41          * that will change if we bring back dynamic VSIDs
  42          */
  43         slb_allocate_realmode(ea);
  44 }
  45
  46 #define slb_esid_mask(ssize)    \
  47         (((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
  48
  49 static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
  50                                          enum slb_index index)
  51 {
  52         return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index;
  53 }
  54
  55 static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
  56                                          unsigned long flags)
  57 {
  58         return (get_kernel_vsid(ea, ssize) << slb_vsid_shift(ssize)) | flags |
  59                 ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
  60 }
  61
  62 static inline void slb_shadow_update(unsigned long ea, int ssize,
  63                                      unsigned long flags,
  64                                      enum slb_index index)
  65 {
  66         struct slb_shadow *p = get_slb_shadow();
  67
  68         /*
  69          * Clear the ESID first so the entry is not valid while we are
  70          * updating it.  No write barriers are needed here, provided
  71          * we only update the current CPU's SLB shadow buffer.
  72          */
  73         p->save_area[index].esid = 0;
  74         p->save_area[index].vsid = cpu_to_be64(mk_vsid_data(ea, ssize, flags));
  75         p->save_area[index].esid = cpu_to_be64(mk_esid_data(ea, ssize, index));
  76 }
  77
  78 static inline void slb_shadow_clear(enum slb_index index)
  79 {
  80         get_slb_shadow()->save_area[index].esid = 0;
  81 }
  82
  83 static inline void create_shadowed_slbe(unsigned long ea, int ssize,
  84                                         unsigned long flags,
  85                                         enum slb_index index)
  86 {
  87         /*
  88          * Updating the shadow buffer before writing the SLB ensures
  89          * we don't get a stale entry here if we get preempted by PHYP
  90          * between these two statements.
  91          */
  92         slb_shadow_update(ea, ssize, flags, index);
  93
  94         asm volatile("slbmte  %0,%1" :
  95                      : "r" (mk_vsid_data(ea, ssize, flags)),
  96                        "r" (mk_esid_data(ea, ssize, index))
  97                      : "memory" );
  98 }
  99
 100 static void __slb_flush_and_rebolt(void)
 101 {
 102         /* If you change this make sure you change SLB_NUM_BOLTED
 103          * and PR KVM appropriately too. */
 104         unsigned long linear_llp, vmalloc_llp, lflags, vflags;
 105         unsigned long ksp_esid_data, ksp_vsid_data;
 106
 107         linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
 108         vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
 109         lflags = SLB_VSID_KERNEL | linear_llp;
 110         vflags = SLB_VSID_KERNEL | vmalloc_llp;
 111
 112         ksp_esid_data = mk_esid_data(get_paca()->kstack, mmu_kernel_ssize, KSTACK_INDEX);
 113         if ((ksp_esid_data & ~0xfffffffUL) <= PAGE_OFFSET) {
 114                 ksp_esid_data &= ~SLB_ESID_V;
 115                 ksp_vsid_data = 0;
 116                 slb_shadow_clear(KSTACK_INDEX);
 117         } else {
 118                 /* Update stack entry; others don't change */
 119                 slb_shadow_update(get_paca()->kstack, mmu_kernel_ssize, lflags, KSTACK_INDEX);
 120                 ksp_vsid_data =
 121                         be64_to_cpu(get_slb_shadow()->save_area[KSTACK_INDEX].vsid);
 122         }
 123
 124         /* We need to do this all in asm, so we're sure we don't touch
 125          * the stack between the slbia and rebolting it. */
 126         asm volatile("isync\n"
 127                      "slbia\n"
 128                      /* Slot 1 - first VMALLOC segment */
 129                      "slbmte    %0,%1\n"
 130                      /* Slot 2 - kernel stack */
 131                      "slbmte    %2,%3\n"
 132                      "isync"
 133                      :: "r"(mk_vsid_data(VMALLOC_START, mmu_kernel_ssize, vflags)),
 134                         "r"(mk_esid_data(VMALLOC_START, mmu_kernel_ssize, 1)),
 135                         "r"(ksp_vsid_data),
 136                         "r"(ksp_esid_data)
 137                      : "memory");
 138 }
 139
 140 void slb_flush_and_rebolt(void)
 141 {
 142
 143         WARN_ON(!irqs_disabled());
 144
 145         /*
 146          * We can't take a PMU exception in the following code, so hard
 147          * disable interrupts.
 148          */
 149         hard_irq_disable();
 150
 151         __slb_flush_and_rebolt();
 152         get_paca()->slb_cache_ptr = 0;
 153 }
 154
 155 void slb_vmalloc_update(void)
 156 {
 157         unsigned long vflags;
 158
 159         vflags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmalloc_psize].sllp;
 160         slb_shadow_update(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX);
 161         slb_flush_and_rebolt();
 162 }
 163
 164 /* Helper function to compare esids.  There are four cases to handle.
 165  * 1. The system is not 1T segment size capable.  Use the GET_ESID compare.
 166  * 2. The system is 1T capable, both addresses are < 1T, use the GET_ESID compare.
 167  * 3. The system is 1T capable, only one of the two addresses is > 1T.  This is not a match.
 168  * 4. The system is 1T capable, both addresses are > 1T, use the GET_ESID_1T macro to compare.
 169  */
 170 static inline int esids_match(unsigned long addr1, unsigned long addr2)
 171 {
 172         int esid_1t_count;
 173
 174         /* System is not 1T segment size capable. */
 175         if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
 176                 return (GET_ESID(addr1) == GET_ESID(addr2));
 177
 178         esid_1t_count = (((addr1 >> SID_SHIFT_1T) != 0) +
 179                                 ((addr2 >> SID_SHIFT_1T) != 0));
 180
 181         /* both addresses are < 1T */
 182         if (esid_1t_count == 0)
 183                 return (GET_ESID(addr1) == GET_ESID(addr2));
 184
 185         /* One address < 1T, the other > 1T.  Not a match */
 186         if (esid_1t_count == 1)
 187                 return 0;
 188
 189         /* Both addresses are > 1T. */
 190         return (GET_ESID_1T(addr1) == GET_ESID_1T(addr2));
 191 }
 192
 193 /* Flush all user entries from the segment table of the current processor. */
 194 void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
 195 {
 196         unsigned long offset;
 197         unsigned long slbie_data = 0;
 198         unsigned long pc = KSTK_EIP(tsk);
 199         unsigned long stack = KSTK_ESP(tsk);
 200         unsigned long exec_base;
 201
 202         /*
 203          * We need interrupts hard-disabled here, not just soft-disabled,
 204          * so that a PMU interrupt can't occur, which might try to access
 205          * user memory (to get a stack trace) and possible cause an SLB miss
 206          * which would update the slb_cache/slb_cache_ptr fields in the PACA.
 207          */
 208         hard_irq_disable();
 209         offset = get_paca()->slb_cache_ptr;
 210         if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
 211             offset <= SLB_CACHE_ENTRIES) {
 212                 int i;
 213                 asm volatile("isync" : : : "memory");
 214                 for (i = 0; i < offset; i++) {
 215                         slbie_data = (unsigned long)get_paca()->slb_cache[i]
 216                                 << SID_SHIFT; /* EA */
 217                         slbie_data |= user_segment_size(slbie_data)
 218                                 << SLBIE_SSIZE_SHIFT;
 219                         slbie_data |= SLBIE_C; /* C set for user addresses */
 220                         asm volatile("slbie %0" : : "r" (slbie_data));
 221                 }
 222                 asm volatile("isync" : : : "memory");
 223         } else {
 224                 __slb_flush_and_rebolt();
 225         }
 226
 227         /* Workaround POWER5 < DD2.1 issue */
 228         if (offset == 1 || offset > SLB_CACHE_ENTRIES)
 229                 asm volatile("slbie %0" : : "r" (slbie_data));
 230
 231         get_paca()->slb_cache_ptr = 0;
 232         copy_mm_to_paca(&mm->context);
 233
 234         /*
 235          * preload some userspace segments into the SLB.
 236          * Almost all 32 and 64bit PowerPC executables are linked at
 237          * 0x10000000 so it makes sense to preload this segment.
 238          */
 239         exec_base = 0x10000000;
 240
 241         if (is_kernel_addr(pc) || is_kernel_addr(stack) ||
 242             is_kernel_addr(exec_base))
 243                 return;
 244
 245         slb_allocate(pc);
 246
 247         if (!esids_match(pc, stack))
 248                 slb_allocate(stack);
 249
 250         if (!esids_match(pc, exec_base) &&
 251             !esids_match(stack, exec_base))
 252                 slb_allocate(exec_base);
 253 }
 254
 255 static inline void patch_slb_encoding(unsigned int *insn_addr,
 256                                       unsigned int immed)
 257 {
 258
 259         /*
 260          * This function patches either an li or a cmpldi instruction with
 261          * a new immediate value. This relies on the fact that both li
 262          * (which is actually addi) and cmpldi both take a 16-bit immediate
 263          * value, and it is situated in the same location in the instruction,
 264          * ie. bits 16-31 (Big endian bit order) or the lower 16 bits.
 265          * The signedness of the immediate operand differs between the two
 266          * instructions however this code is only ever patching a small value,
 267          * much less than 1 << 15, so we can get away with it.
 268          * To patch the value we read the existing instruction, clear the
 269          * immediate value, and or in our new value, then write the instruction
 270          * back.
 271          */
 272         unsigned int insn = (*insn_addr & 0xffff0000) | immed;
 273         patch_instruction(insn_addr, insn);
 274 }
 275
 276 extern u32 slb_miss_kernel_load_linear[];
 277 extern u32 slb_miss_kernel_load_io[];
 278 extern u32 slb_compare_rr_to_size[];
 279 extern u32 slb_miss_kernel_load_vmemmap[];
 280
 281 void slb_set_size(u16 size)
 282 {
 283         if (mmu_slb_size == size)
 284                 return;
 285
 286         mmu_slb_size = size;
 287         patch_slb_encoding(slb_compare_rr_to_size, mmu_slb_size);
 288 }
 289
 290 void slb_initialize(void)
 291 {
 292         unsigned long linear_llp, vmalloc_llp, io_llp;
 293         unsigned long lflags, vflags;
 294         static int slb_encoding_inited;
 295 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 296         unsigned long vmemmap_llp;
 297 #endif
 298
 299         /* Prepare our SLB miss handler based on our page size */
 300         linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
 301         io_llp = mmu_psize_defs[mmu_io_psize].sllp;
 302         vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
 303         get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
 304 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 305         vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp;
 306 #endif
 307         if (!slb_encoding_inited) {
 308                 slb_encoding_inited = 1;
 309                 patch_slb_encoding(slb_miss_kernel_load_linear,
 310                                    SLB_VSID_KERNEL | linear_llp);
 311                 patch_slb_encoding(slb_miss_kernel_load_io,
 312                                    SLB_VSID_KERNEL | io_llp);
 313                 patch_slb_encoding(slb_compare_rr_to_size,
 314                                    mmu_slb_size);
 315
 316                 pr_devel("SLB: linear  LLP = %04lx\n", linear_llp);
 317                 pr_devel("SLB: io      LLP = %04lx\n", io_llp);
 318
 319 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 320                 patch_slb_encoding(slb_miss_kernel_load_vmemmap,
 321                                    SLB_VSID_KERNEL | vmemmap_llp);
 322                 pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp);
 323 #endif
 324         }
 325
 326         get_paca()->stab_rr = SLB_NUM_BOLTED;
 327
 328         lflags = SLB_VSID_KERNEL | linear_llp;
 329         vflags = SLB_VSID_KERNEL | vmalloc_llp;
 330
 331         /* Invalidate the entire SLB (even entry 0) & all the ERATS */
 332         asm volatile("isync":::"memory");
 333         asm volatile("slbmte  %0,%0"::"r" (0) : "memory");
 334         asm volatile("isync; slbia; isync":::"memory");
 335         create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, LINEAR_INDEX);
 336         create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, VMALLOC_INDEX);
 337
 338         /* For the boot cpu, we're running on the stack in init_thread_union,
 339          * which is in the first segment of the linear mapping, and also
 340          * get_paca()->kstack hasn't been initialized yet.
 341          * For secondary cpus, we need to bolt the kernel stack entry now.
 342          */
 343         slb_shadow_clear(KSTACK_INDEX);
 344         if (raw_smp_processor_id() != boot_cpuid &&
 345             (get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET)
 346                 create_shadowed_slbe(get_paca()->kstack,
 347                                      mmu_kernel_ssize, lflags, KSTACK_INDEX);
 348
 349         asm volatile("isync":::"memory");
 350 }