arch/powerpc/mm/tlb-radix.c

   1 /*
   2  * TLB flush routines for radix kernels.
   3  *
   4  * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/mm.h>
  13 #include <linux/hugetlb.h>
  14 #include <linux/memblock.h>
  15 #include <asm/ppc-opcode.h>
  16
  17 #include <asm/tlb.h>
  18 #include <asm/tlbflush.h>
  19 #include <asm/trace.h>
  20
  21
  22 #define RIC_FLUSH_TLB 0
  23 #define RIC_FLUSH_PWC 1
  24 #define RIC_FLUSH_ALL 2
  25
  26 static inline void __tlbiel_pid(unsigned long pid, int set,
  27                                 unsigned long ric)
  28 {
  29         unsigned long rb,rs,prs,r;
  30
  31         rb = PPC_BIT(53); /* IS = 1 */
  32         rb |= set << PPC_BITLSHIFT(51);
  33         rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
  34         prs = 1; /* process scoped */
  35         r = 1;   /* raidx format */
  36
  37         asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
  38                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  39         trace_tlbie(0, 1, rb, rs, ric, prs, r);
  40 }
  41
  42 /*
  43  * We use 128 set in radix mode and 256 set in hpt mode.
  44  */
  45 static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
  46 {
  47         int set;
  48
  49         asm volatile("ptesync": : :"memory");
  50
  51         /*
  52          * Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL,
  53          * also flush the entire Page Walk Cache.
  54          */
  55         __tlbiel_pid(pid, 0, ric);
  56
  57         if (ric == RIC_FLUSH_ALL)
  58                 /* For the remaining sets, just flush the TLB */
  59                 ric = RIC_FLUSH_TLB;
  60
  61         for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
  62                 __tlbiel_pid(pid, set, ric);
  63
  64         asm volatile("ptesync": : :"memory");
  65         asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
  66 }
  67
  68 static inline void tlbiel_pwc(unsigned long pid)
  69 {
  70         asm volatile("ptesync": : :"memory");
  71
  72         /* For PWC flush, we don't look at set number */
  73         __tlbiel_pid(pid, 0, RIC_FLUSH_PWC);
  74
  75         asm volatile("ptesync": : :"memory");
  76         asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
  77 }
  78
  79 static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
  80 {
  81         unsigned long rb,rs,prs,r;
  82
  83         rb = PPC_BIT(53); /* IS = 1 */
  84         rs = pid << PPC_BITLSHIFT(31);
  85         prs = 1; /* process scoped */
  86         r = 1;   /* raidx format */
  87
  88         asm volatile("ptesync": : :"memory");
  89         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
  90                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  91         asm volatile("eieio; tlbsync; ptesync": : :"memory");
  92         trace_tlbie(0, 0, rb, rs, ric, prs, r);
  93 }
  94
  95 static inline void _tlbiel_va(unsigned long va, unsigned long pid,
  96                               unsigned long ap, unsigned long ric)
  97 {
  98         unsigned long rb,rs,prs,r;
  99
 100         rb = va & ~(PPC_BITMASK(52, 63));
 101         rb |= ap << PPC_BITLSHIFT(58);
 102         rs = pid << PPC_BITLSHIFT(31);
 103         prs = 1; /* process scoped */
 104         r = 1;   /* raidx format */
 105
 106         asm volatile("ptesync": : :"memory");
 107         asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
 108                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 109         asm volatile("ptesync": : :"memory");
 110         trace_tlbie(0, 1, rb, rs, ric, prs, r);
 111 }
 112
 113 static inline void _tlbie_va(unsigned long va, unsigned long pid,
 114                              unsigned long ap, unsigned long ric)
 115 {
 116         unsigned long rb,rs,prs,r;
 117
 118         rb = va & ~(PPC_BITMASK(52, 63));
 119         rb |= ap << PPC_BITLSHIFT(58);
 120         rs = pid << PPC_BITLSHIFT(31);
 121         prs = 1; /* process scoped */
 122         r = 1;   /* raidx format */
 123
 124         asm volatile("ptesync": : :"memory");
 125         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 126                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 127         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 128         trace_tlbie(0, 0, rb, rs, ric, prs, r);
 129 }
 130
 131 /*
 132  * Base TLB flushing operations:
 133  *
 134  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 135  *  - flush_tlb_page(vma, vmaddr) flushes one page
 136  *  - flush_tlb_range(vma, start, end) flushes a range of pages
 137  *  - flush_tlb_kernel_range(start, end) flushes kernel pages
 138  *
 139  *  - local_* variants of page and mm only apply to the current
 140  *    processor
 141  */
 142 void radix__local_flush_tlb_mm(struct mm_struct *mm)
 143 {
 144         unsigned long pid;
 145
 146         preempt_disable();
 147         pid = mm->context.id;
 148         if (pid != MMU_NO_CONTEXT)
 149                 _tlbiel_pid(pid, RIC_FLUSH_ALL);
 150         preempt_enable();
 151 }
 152 EXPORT_SYMBOL(radix__local_flush_tlb_mm);
 153
 154 void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 155 {
 156         unsigned long pid;
 157         struct mm_struct *mm = tlb->mm;
 158         /*
 159          * If we are doing a full mm flush, we will do a tlb flush
 160          * with RIC_FLUSH_ALL later.
 161          */
 162         if (tlb->fullmm)
 163                 return;
 164
 165         preempt_disable();
 166
 167         pid = mm->context.id;
 168         if (pid != MMU_NO_CONTEXT)
 169                 tlbiel_pwc(pid);
 170
 171         preempt_enable();
 172 }
 173 EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
 174
 175 void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
 176                                        int psize)
 177 {
 178         unsigned long pid;
 179         unsigned long ap = mmu_get_ap(psize);
 180
 181         preempt_disable();
 182         pid = mm ? mm->context.id : 0;
 183         if (pid != MMU_NO_CONTEXT)
 184                 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 185         preempt_enable();
 186 }
 187
 188 void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 189 {
 190 #ifdef CONFIG_HUGETLB_PAGE
 191         /* need the return fix for nohash.c */
 192         if (vma && is_vm_hugetlb_page(vma))
 193                 return __local_flush_hugetlb_page(vma, vmaddr);
 194 #endif
 195         radix__local_flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
 196                                           mmu_virtual_psize);
 197 }
 198 EXPORT_SYMBOL(radix__local_flush_tlb_page);
 199
 200 #ifdef CONFIG_SMP
 201 void radix__flush_tlb_mm(struct mm_struct *mm)
 202 {
 203         unsigned long pid;
 204
 205         preempt_disable();
 206         pid = mm->context.id;
 207         if (unlikely(pid == MMU_NO_CONTEXT))
 208                 goto no_context;
 209
 210         if (!mm_is_thread_local(mm))
 211                 _tlbie_pid(pid, RIC_FLUSH_ALL);
 212         else
 213                 _tlbiel_pid(pid, RIC_FLUSH_ALL);
 214 no_context:
 215         preempt_enable();
 216 }
 217 EXPORT_SYMBOL(radix__flush_tlb_mm);
 218
 219 void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 220 {
 221         unsigned long pid;
 222         struct mm_struct *mm = tlb->mm;
 223
 224         /*
 225          * If we are doing a full mm flush, we will do a tlb flush
 226          * with RIC_FLUSH_ALL later.
 227          */
 228         if (tlb->fullmm)
 229                 return;
 230         preempt_disable();
 231
 232         pid = mm->context.id;
 233         if (unlikely(pid == MMU_NO_CONTEXT))
 234                 goto no_context;
 235
 236         if (!mm_is_thread_local(mm))
 237                 _tlbie_pid(pid, RIC_FLUSH_PWC);
 238         else
 239                 tlbiel_pwc(pid);
 240 no_context:
 241         preempt_enable();
 242 }
 243 EXPORT_SYMBOL(radix__flush_tlb_pwc);
 244
 245 void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
 246                                  int psize)
 247 {
 248         unsigned long pid;
 249         unsigned long ap = mmu_get_ap(psize);
 250
 251         preempt_disable();
 252         pid = mm ? mm->context.id : 0;
 253         if (unlikely(pid == MMU_NO_CONTEXT))
 254                 goto bail;
 255         if (!mm_is_thread_local(mm))
 256                 _tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 257         else
 258                 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 259 bail:
 260         preempt_enable();
 261 }
 262
 263 void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 264 {
 265 #ifdef CONFIG_HUGETLB_PAGE
 266         if (vma && is_vm_hugetlb_page(vma))
 267                 return flush_hugetlb_page(vma, vmaddr);
 268 #endif
 269         radix__flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
 270                                     mmu_virtual_psize);
 271 }
 272 EXPORT_SYMBOL(radix__flush_tlb_page);
 273
 274 #endif /* CONFIG_SMP */
 275
 276 void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
 277 {
 278         _tlbie_pid(0, RIC_FLUSH_ALL);
 279 }
 280 EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
 281
 282 /*
 283  * Currently, for range flushing, we just do a full mm flush. Because
 284  * we use this in code path where we don' track the page size.
 285  */
 286 void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 287                      unsigned long end)
 288
 289 {
 290         struct mm_struct *mm = vma->vm_mm;
 291         radix__flush_tlb_mm(mm);
 292 }
 293 EXPORT_SYMBOL(radix__flush_tlb_range);
 294
 295 static int radix_get_mmu_psize(int page_size)
 296 {
 297         int psize;
 298
 299         if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
 300                 psize = mmu_virtual_psize;
 301         else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
 302                 psize = MMU_PAGE_2M;
 303         else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
 304                 psize = MMU_PAGE_1G;
 305         else
 306                 return -1;
 307         return psize;
 308 }
 309
 310 void radix__tlb_flush(struct mmu_gather *tlb)
 311 {
 312         int psize = 0;
 313         struct mm_struct *mm = tlb->mm;
 314         int page_size = tlb->page_size;
 315
 316         psize = radix_get_mmu_psize(page_size);
 317         /*
 318          * if page size is not something we understand, do a full mm flush
 319          */
 320         if (psize != -1 && !tlb->fullmm && !tlb->need_flush_all)
 321                 radix__flush_tlb_range_psize(mm, tlb->start, tlb->end, psize);
 322         else
 323                 radix__flush_tlb_mm(mm);
 324 }
 325
 326 #define TLB_FLUSH_ALL -1UL
 327 /*
 328  * Number of pages above which we will do a bcast tlbie. Just a
 329  * number at this point copied from x86
 330  */
 331 static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
 332
 333 void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
 334                                   unsigned long end, int psize)
 335 {
 336         unsigned long pid;
 337         unsigned long addr;
 338         int local = mm_is_thread_local(mm);
 339         unsigned long ap = mmu_get_ap(psize);
 340         unsigned long page_size = 1UL << mmu_psize_defs[psize].shift;
 341
 342
 343         preempt_disable();
 344         pid = mm ? mm->context.id : 0;
 345         if (unlikely(pid == MMU_NO_CONTEXT))
 346                 goto err_out;
 347
 348         if (end == TLB_FLUSH_ALL ||
 349             (end - start) > tlb_single_page_flush_ceiling * page_size) {
 350                 if (local)
 351                         _tlbiel_pid(pid, RIC_FLUSH_TLB);
 352                 else
 353                         _tlbie_pid(pid, RIC_FLUSH_TLB);
 354                 goto err_out;
 355         }
 356         for (addr = start; addr < end; addr += page_size) {
 357
 358                 if (local)
 359                         _tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
 360                 else
 361                         _tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
 362         }
 363 err_out:
 364         preempt_enable();
 365 }
 366
 367 void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
 368                               unsigned long page_size)
 369 {
 370         unsigned long rb,rs,prs,r;
 371         unsigned long ap;
 372         unsigned long ric = RIC_FLUSH_TLB;
 373
 374         ap = mmu_get_ap(radix_get_mmu_psize(page_size));
 375         rb = gpa & ~(PPC_BITMASK(52, 63));
 376         rb |= ap << PPC_BITLSHIFT(58);
 377         rs = lpid & ((1UL << 32) - 1);
 378         prs = 0; /* process scoped */
 379         r = 1;   /* raidx format */
 380
 381         asm volatile("ptesync": : :"memory");
 382         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 383                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 384         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 385         trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
 386 }
 387 EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
 388
 389 void radix__flush_tlb_lpid(unsigned long lpid)
 390 {
 391         unsigned long rb,rs,prs,r;
 392         unsigned long ric = RIC_FLUSH_ALL;
 393
 394         rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
 395         rs = lpid & ((1UL << 32) - 1);
 396         prs = 0; /* partition scoped */
 397         r = 1;   /* raidx format */
 398
 399         asm volatile("ptesync": : :"memory");
 400         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 401                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 402         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 403         trace_tlbie(lpid, 0, rb, rs, ric, prs, r);
 404 }
 405 EXPORT_SYMBOL(radix__flush_tlb_lpid);
 406
 407 void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
 408                                 unsigned long start, unsigned long end)
 409 {
 410         radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
 411 }
 412 EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
 413
 414 void radix__flush_tlb_all(void)
 415 {
 416         unsigned long rb,prs,r,rs;
 417         unsigned long ric = RIC_FLUSH_ALL;
 418
 419         rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
 420         prs = 0; /* partition scoped */
 421         r = 1;   /* raidx format */
 422         rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */
 423
 424         asm volatile("ptesync": : :"memory");
 425         /*
 426          * now flush guest entries by passing PRS = 1 and LPID != 0
 427          */
 428         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 429                      : : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
 430         trace_tlbie(0, 0, rb, rs, ric, prs, r);
 431         /*
 432          * now flush host entires by passing PRS = 0 and LPID == 0
 433          */
 434         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 435                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
 436         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 437         trace_tlbie(0, 0, rb, 0, ric, prs, r);
 438 }
 439
 440 void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
 441                                  unsigned long address)
 442 {
 443         /*
 444          * We track page size in pte only for DD1, So we can
 445          * call this only on DD1.
 446          */
 447         if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 448                 VM_WARN_ON(1);
 449                 return;
 450         }
 451
 452         if (old_pte & R_PAGE_LARGE)
 453                 radix__flush_tlb_page_psize(mm, address, MMU_PAGE_2M);
 454         else
 455                 radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);
 456 }