arch/powerpc/mm/tlb-radix.c

   1 /*
   2  * TLB flush routines for radix kernels.
   3  *
   4  * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/mm.h>
  13 #include <linux/hugetlb.h>
  14 #include <linux/memblock.h>
  15 #include <asm/ppc-opcode.h>
  16
  17 #include <asm/tlb.h>
  18 #include <asm/tlbflush.h>
  19
  20 static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
  21
  22 #define RIC_FLUSH_TLB 0
  23 #define RIC_FLUSH_PWC 1
  24 #define RIC_FLUSH_ALL 2
  25
  26 static inline void __tlbiel_pid(unsigned long pid, int set,
  27                                 unsigned long ric)
  28 {
  29         unsigned long rb,rs,prs,r;
  30
  31         rb = PPC_BIT(53); /* IS = 1 */
  32         rb |= set << PPC_BITLSHIFT(51);
  33         rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
  34         prs = 1; /* process scoped */
  35         r = 1;   /* raidx format */
  36
  37         asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
  38                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  39 }
  40
  41 /*
  42  * We use 128 set in radix mode and 256 set in hpt mode.
  43  */
  44 static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
  45 {
  46         int set;
  47
  48         asm volatile("ptesync": : :"memory");
  49         for (set = 0; set < POWER9_TLB_SETS_RADIX ; set++) {
  50                 __tlbiel_pid(pid, set, ric);
  51         }
  52         asm volatile("ptesync": : :"memory");
  53         asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
  54 }
  55
  56 static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
  57 {
  58         unsigned long rb,rs,prs,r;
  59
  60         rb = PPC_BIT(53); /* IS = 1 */
  61         rs = pid << PPC_BITLSHIFT(31);
  62         prs = 1; /* process scoped */
  63         r = 1;   /* raidx format */
  64
  65         asm volatile("ptesync": : :"memory");
  66         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
  67                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  68         asm volatile("eieio; tlbsync; ptesync": : :"memory");
  69 }
  70
  71 static inline void _tlbiel_va(unsigned long va, unsigned long pid,
  72                               unsigned long ap, unsigned long ric)
  73 {
  74         unsigned long rb,rs,prs,r;
  75
  76         rb = va & ~(PPC_BITMASK(52, 63));
  77         rb |= ap << PPC_BITLSHIFT(58);
  78         rs = pid << PPC_BITLSHIFT(31);
  79         prs = 1; /* process scoped */
  80         r = 1;   /* raidx format */
  81
  82         asm volatile("ptesync": : :"memory");
  83         asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
  84                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
  85         asm volatile("ptesync": : :"memory");
  86 }
  87
  88 static inline void _tlbie_va(unsigned long va, unsigned long pid,
  89                              unsigned long ap, unsigned long ric)
  90 {
  91         unsigned long rb,rs,prs,r;
  92
  93         rb = va & ~(PPC_BITMASK(52, 63));
  94         rb |= ap << PPC_BITLSHIFT(58);
  95         rs = pid << PPC_BITLSHIFT(31);
  96         prs = 1; /* process scoped */
  97         r = 1;   /* raidx format */
  98
  99         asm volatile("ptesync": : :"memory");
 100         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 101                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 102         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 103 }
 104
 105 /*
 106  * Base TLB flushing operations:
 107  *
 108  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 109  *  - flush_tlb_page(vma, vmaddr) flushes one page
 110  *  - flush_tlb_range(vma, start, end) flushes a range of pages
 111  *  - flush_tlb_kernel_range(start, end) flushes kernel pages
 112  *
 113  *  - local_* variants of page and mm only apply to the current
 114  *    processor
 115  */
 116 void radix__local_flush_tlb_mm(struct mm_struct *mm)
 117 {
 118         unsigned long pid;
 119
 120         preempt_disable();
 121         pid = mm->context.id;
 122         if (pid != MMU_NO_CONTEXT)
 123                 _tlbiel_pid(pid, RIC_FLUSH_ALL);
 124         preempt_enable();
 125 }
 126 EXPORT_SYMBOL(radix__local_flush_tlb_mm);
 127
 128 void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 129 {
 130         unsigned long pid;
 131         struct mm_struct *mm = tlb->mm;
 132         /*
 133          * If we are doing a full mm flush, we will do a tlb flush
 134          * with RIC_FLUSH_ALL later.
 135          */
 136         if (tlb->fullmm)
 137                 return;
 138
 139         preempt_disable();
 140
 141         pid = mm->context.id;
 142         if (pid != MMU_NO_CONTEXT)
 143                 _tlbiel_pid(pid, RIC_FLUSH_PWC);
 144
 145         preempt_enable();
 146 }
 147 EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
 148
 149 void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
 150                                        int psize)
 151 {
 152         unsigned long pid;
 153         unsigned long ap = mmu_get_ap(psize);
 154
 155         preempt_disable();
 156         pid = mm ? mm->context.id : 0;
 157         if (pid != MMU_NO_CONTEXT)
 158                 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 159         preempt_enable();
 160 }
 161
 162 void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 163 {
 164 #ifdef CONFIG_HUGETLB_PAGE
 165         /* need the return fix for nohash.c */
 166         if (vma && is_vm_hugetlb_page(vma))
 167                 return __local_flush_hugetlb_page(vma, vmaddr);
 168 #endif
 169         radix__local_flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
 170                                           mmu_virtual_psize);
 171 }
 172 EXPORT_SYMBOL(radix__local_flush_tlb_page);
 173
 174 #ifdef CONFIG_SMP
 175 void radix__flush_tlb_mm(struct mm_struct *mm)
 176 {
 177         unsigned long pid;
 178
 179         preempt_disable();
 180         pid = mm->context.id;
 181         if (unlikely(pid == MMU_NO_CONTEXT))
 182                 goto no_context;
 183
 184         if (!mm_is_thread_local(mm)) {
 185                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 186
 187                 if (lock_tlbie)
 188                         raw_spin_lock(&native_tlbie_lock);
 189                 _tlbie_pid(pid, RIC_FLUSH_ALL);
 190                 if (lock_tlbie)
 191                         raw_spin_unlock(&native_tlbie_lock);
 192         } else
 193                 _tlbiel_pid(pid, RIC_FLUSH_ALL);
 194 no_context:
 195         preempt_enable();
 196 }
 197 EXPORT_SYMBOL(radix__flush_tlb_mm);
 198
 199 void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
 200 {
 201         unsigned long pid;
 202         struct mm_struct *mm = tlb->mm;
 203
 204         /*
 205          * If we are doing a full mm flush, we will do a tlb flush
 206          * with RIC_FLUSH_ALL later.
 207          */
 208         if (tlb->fullmm)
 209                 return;
 210         preempt_disable();
 211
 212         pid = mm->context.id;
 213         if (unlikely(pid == MMU_NO_CONTEXT))
 214                 goto no_context;
 215
 216         if (!mm_is_thread_local(mm)) {
 217                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 218
 219                 if (lock_tlbie)
 220                         raw_spin_lock(&native_tlbie_lock);
 221                 _tlbie_pid(pid, RIC_FLUSH_PWC);
 222                 if (lock_tlbie)
 223                         raw_spin_unlock(&native_tlbie_lock);
 224         } else
 225                 _tlbiel_pid(pid, RIC_FLUSH_PWC);
 226 no_context:
 227         preempt_enable();
 228 }
 229 EXPORT_SYMBOL(radix__flush_tlb_pwc);
 230
 231 void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
 232                                  int psize)
 233 {
 234         unsigned long pid;
 235         unsigned long ap = mmu_get_ap(psize);
 236
 237         preempt_disable();
 238         pid = mm ? mm->context.id : 0;
 239         if (unlikely(pid == MMU_NO_CONTEXT))
 240                 goto bail;
 241         if (!mm_is_thread_local(mm)) {
 242                 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 243
 244                 if (lock_tlbie)
 245                         raw_spin_lock(&native_tlbie_lock);
 246                 _tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 247                 if (lock_tlbie)
 248                         raw_spin_unlock(&native_tlbie_lock);
 249         } else
 250                 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
 251 bail:
 252         preempt_enable();
 253 }
 254
 255 void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 256 {
 257 #ifdef CONFIG_HUGETLB_PAGE
 258         if (vma && is_vm_hugetlb_page(vma))
 259                 return flush_hugetlb_page(vma, vmaddr);
 260 #endif
 261         radix__flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
 262                                     mmu_virtual_psize);
 263 }
 264 EXPORT_SYMBOL(radix__flush_tlb_page);
 265
 266 #endif /* CONFIG_SMP */
 267
 268 void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
 269 {
 270         int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 271
 272         if (lock_tlbie)
 273                 raw_spin_lock(&native_tlbie_lock);
 274         _tlbie_pid(0, RIC_FLUSH_ALL);
 275         if (lock_tlbie)
 276                 raw_spin_unlock(&native_tlbie_lock);
 277 }
 278 EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
 279
 280 /*
 281  * Currently, for range flushing, we just do a full mm flush. Because
 282  * we use this in code path where we don' track the page size.
 283  */
 284 void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 285                      unsigned long end)
 286
 287 {
 288         struct mm_struct *mm = vma->vm_mm;
 289         radix__flush_tlb_mm(mm);
 290 }
 291 EXPORT_SYMBOL(radix__flush_tlb_range);
 292
 293 static int radix_get_mmu_psize(int page_size)
 294 {
 295         int psize;
 296
 297         if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
 298                 psize = mmu_virtual_psize;
 299         else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
 300                 psize = MMU_PAGE_2M;
 301         else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
 302                 psize = MMU_PAGE_1G;
 303         else
 304                 return -1;
 305         return psize;
 306 }
 307
 308 void radix__tlb_flush(struct mmu_gather *tlb)
 309 {
 310         int psize = 0;
 311         struct mm_struct *mm = tlb->mm;
 312         int page_size = tlb->page_size;
 313
 314         psize = radix_get_mmu_psize(page_size);
 315         /*
 316          * if page size is not something we understand, do a full mm flush
 317          */
 318         if (psize != -1 && !tlb->fullmm && !tlb->need_flush_all)
 319                 radix__flush_tlb_range_psize(mm, tlb->start, tlb->end, psize);
 320         else
 321                 radix__flush_tlb_mm(mm);
 322 }
 323
 324 #define TLB_FLUSH_ALL -1UL
 325 /*
 326  * Number of pages above which we will do a bcast tlbie. Just a
 327  * number at this point copied from x86
 328  */
 329 static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
 330
 331 void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
 332                                   unsigned long end, int psize)
 333 {
 334         unsigned long pid;
 335         unsigned long addr;
 336         int local = mm_is_thread_local(mm);
 337         unsigned long ap = mmu_get_ap(psize);
 338         int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
 339         unsigned long page_size = 1UL << mmu_psize_defs[psize].shift;
 340
 341
 342         preempt_disable();
 343         pid = mm ? mm->context.id : 0;
 344         if (unlikely(pid == MMU_NO_CONTEXT))
 345                 goto err_out;
 346
 347         if (end == TLB_FLUSH_ALL ||
 348             (end - start) > tlb_single_page_flush_ceiling * page_size) {
 349                 if (local)
 350                         _tlbiel_pid(pid, RIC_FLUSH_TLB);
 351                 else
 352                         _tlbie_pid(pid, RIC_FLUSH_TLB);
 353                 goto err_out;
 354         }
 355         for (addr = start; addr < end; addr += page_size) {
 356
 357                 if (local)
 358                         _tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
 359                 else {
 360                         if (lock_tlbie)
 361                                 raw_spin_lock(&native_tlbie_lock);
 362                         _tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
 363                         if (lock_tlbie)
 364                                 raw_spin_unlock(&native_tlbie_lock);
 365                 }
 366         }
 367 err_out:
 368         preempt_enable();
 369 }
 370
 371 void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
 372                               unsigned long page_size)
 373 {
 374         unsigned long rb,rs,prs,r;
 375         unsigned long ap;
 376         unsigned long ric = RIC_FLUSH_TLB;
 377
 378         ap = mmu_get_ap(radix_get_mmu_psize(page_size));
 379         rb = gpa & ~(PPC_BITMASK(52, 63));
 380         rb |= ap << PPC_BITLSHIFT(58);
 381         rs = lpid & ((1UL << 32) - 1);
 382         prs = 0; /* process scoped */
 383         r = 1;   /* raidx format */
 384
 385         asm volatile("ptesync": : :"memory");
 386         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 387                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 388         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 389 }
 390 EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
 391
 392 void radix__flush_tlb_lpid(unsigned long lpid)
 393 {
 394         unsigned long rb,rs,prs,r;
 395         unsigned long ric = RIC_FLUSH_ALL;
 396
 397         rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
 398         rs = lpid & ((1UL << 32) - 1);
 399         prs = 0; /* partition scoped */
 400         r = 1;   /* raidx format */
 401
 402         asm volatile("ptesync": : :"memory");
 403         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 404                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 405         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 406 }
 407 EXPORT_SYMBOL(radix__flush_tlb_lpid);
 408
 409 void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
 410                                 unsigned long start, unsigned long end)
 411 {
 412         radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
 413 }
 414 EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
 415
 416 void radix__flush_tlb_all(void)
 417 {
 418         unsigned long rb,prs,r,rs;
 419         unsigned long ric = RIC_FLUSH_ALL;
 420
 421         rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
 422         prs = 0; /* partition scoped */
 423         r = 1;   /* raidx format */
 424         rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */
 425
 426         asm volatile("ptesync": : :"memory");
 427         /*
 428          * now flush guest entries by passing PRS = 1 and LPID != 0
 429          */
 430         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 431                      : : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
 432         /*
 433          * now flush host entires by passing PRS = 0 and LPID == 0
 434          */
 435         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 436                      : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
 437         asm volatile("eieio; tlbsync; ptesync": : :"memory");
 438 }
 439
 440 void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
 441                                  unsigned long address)
 442 {
 443         /*
 444          * We track page size in pte only for DD1, So we can
 445          * call this only on DD1.
 446          */
 447         if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 448                 VM_WARN_ON(1);
 449                 return;
 450         }
 451
 452         if (old_pte & _PAGE_LARGE)
 453                 radix__flush_tlb_page_psize(mm, address, MMU_PAGE_2M);
 454         else
 455                 radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);
 456 }