arch/powerpc/mm/tlb_64.c

   1 /*
   2  * This file contains the routines for flushing entries from the
   3  * TLB and MMU hash table.
   4  *
   5  *  Derived from arch/ppc64/mm/init.c:
   6  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   7  *
   8  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
   9  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  10  *    Copyright (C) 1996 Paul Mackerras
  11  *
  12  *  Derived from "arch/i386/mm/init.c"
  13  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  14  *
  15  *  Dave Engebretsen <engebret@us.ibm.com>
  16  *      Rework for PPC64 port.
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/init.h>
  27 #include <linux/percpu.h>
  28 #include <linux/hardirq.h>
  29 #include <asm/pgalloc.h>
  30 #include <asm/tlbflush.h>
  31 #include <asm/tlb.h>
  32 #include <asm/bug.h>
  33
  34 DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
  35
  36 /* This is declared as we are using the more or less generic
  37  * include/asm-powerpc/tlb.h file -- tgall
  38  */
  39 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  40 DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
  41 unsigned long pte_freelist_forced_free;
  42
  43 struct pte_freelist_batch
  44 {
  45         struct rcu_head rcu;
  46         unsigned int    index;
  47         pgtable_free_t  tables[0];
  48 };
  49
  50 DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
  51 unsigned long pte_freelist_forced_free;
  52
  53 #define PTE_FREELIST_SIZE \
  54         ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
  55           / sizeof(pgtable_free_t))
  56
  57 #ifdef CONFIG_SMP
  58 static void pte_free_smp_sync(void *arg)
  59 {
  60         /* Do nothing, just ensure we sync with all CPUs */
  61 }
  62 #endif
  63
  64 /* This is only called when we are critically out of memory
  65  * (and fail to get a page in pte_free_tlb).
  66  */
  67 static void pgtable_free_now(pgtable_free_t pgf)
  68 {
  69         pte_freelist_forced_free++;
  70
  71         smp_call_function(pte_free_smp_sync, NULL, 0, 1);
  72
  73         pgtable_free(pgf);
  74 }
  75
  76 static void pte_free_rcu_callback(struct rcu_head *head)
  77 {
  78         struct pte_freelist_batch *batch =
  79                 container_of(head, struct pte_freelist_batch, rcu);
  80         unsigned int i;
  81
  82         for (i = 0; i < batch->index; i++)
  83                 pgtable_free(batch->tables[i]);
  84
  85         free_page((unsigned long)batch);
  86 }
  87
  88 static void pte_free_submit(struct pte_freelist_batch *batch)
  89 {
  90         INIT_RCU_HEAD(&batch->rcu);
  91         call_rcu(&batch->rcu, pte_free_rcu_callback);
  92 }
  93
  94 void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
  95 {
  96         /* This is safe since tlb_gather_mmu has disabled preemption */
  97         cpumask_t local_cpumask = cpumask_of_cpu(smp_processor_id());
  98         struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
  99
 100         if (atomic_read(&tlb->mm->mm_users) < 2 ||
 101             cpus_equal(tlb->mm->cpu_vm_mask, local_cpumask)) {
 102                 pgtable_free(pgf);
 103                 return;
 104         }
 105
 106         if (*batchp == NULL) {
 107                 *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
 108                 if (*batchp == NULL) {
 109                         pgtable_free_now(pgf);
 110                         return;
 111                 }
 112                 (*batchp)->index = 0;
 113         }
 114         (*batchp)->tables[(*batchp)->index++] = pgf;
 115         if ((*batchp)->index == PTE_FREELIST_SIZE) {
 116                 pte_free_submit(*batchp);
 117                 *batchp = NULL;
 118         }
 119 }
 120
 121 /*
 122  * A linux PTE was changed and the corresponding hash table entry
 123  * neesd to be flushed. This function will either perform the flush
 124  * immediately or will batch it up if the current CPU has an active
 125  * batch on it.
 126  *
 127  * Must be called from within some kind of spinlock/non-preempt region...
 128  */
 129 void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
 130                      pte_t *ptep, unsigned long pte, int huge)
 131 {
 132         struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
 133         unsigned long vsid, vaddr;
 134         unsigned int psize;
 135         int ssize;
 136         real_pte_t rpte;
 137         int i;
 138
 139         i = batch->index;
 140
 141         /* We mask the address for the base page size. Huge pages will
 142          * have applied their own masking already
 143          */
 144         addr &= PAGE_MASK;
 145
 146         /* Get page size (maybe move back to caller).
 147          *
 148          * NOTE: when using special 64K mappings in 4K environment like
 149          * for SPEs, we obtain the page size from the slice, which thus
 150          * must still exist (and thus the VMA not reused) at the time
 151          * of this call
 152          */
 153         if (huge) {
 154 #ifdef CONFIG_HUGETLB_PAGE
 155                 psize = mmu_huge_psize;
 156 #else
 157                 BUG();
 158                 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
 159 #endif
 160         } else
 161                 psize = pte_pagesize_index(mm, addr, pte);
 162
 163         /* Build full vaddr */
 164         if (!is_kernel_addr(addr)) {
 165                 ssize = user_segment_size(addr);
 166                 vsid = get_vsid(mm->context.id, addr, ssize);
 167                 WARN_ON(vsid == 0);
 168         } else {
 169                 vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
 170                 ssize = mmu_kernel_ssize;
 171         }
 172         vaddr = hpt_va(addr, vsid, ssize);
 173         rpte = __real_pte(__pte(pte), ptep);
 174
 175         /*
 176          * Check if we have an active batch on this CPU. If not, just
 177          * flush now and return. For now, we don global invalidates
 178          * in that case, might be worth testing the mm cpu mask though
 179          * and decide to use local invalidates instead...
 180          */
 181         if (!batch->active) {
 182                 flush_hash_page(vaddr, rpte, psize, ssize, 0);
 183                 return;
 184         }
 185
 186         /*
 187          * This can happen when we are in the middle of a TLB batch and
 188          * we encounter memory pressure (eg copy_page_range when it tries
 189          * to allocate a new pte). If we have to reclaim memory and end
 190          * up scanning and resetting referenced bits then our batch context
 191          * will change mid stream.
 192          *
 193          * We also need to ensure only one page size is present in a given
 194          * batch
 195          */
 196         if (i != 0 && (mm != batch->mm || batch->psize != psize ||
 197                        batch->ssize != ssize)) {
 198                 __flush_tlb_pending(batch);
 199                 i = 0;
 200         }
 201         if (i == 0) {
 202                 batch->mm = mm;
 203                 batch->psize = psize;
 204                 batch->ssize = ssize;
 205         }
 206         batch->pte[i] = rpte;
 207         batch->vaddr[i] = vaddr;
 208         batch->index = ++i;
 209         if (i >= PPC64_TLB_BATCH_NR)
 210                 __flush_tlb_pending(batch);
 211 }
 212
 213 /*
 214  * This function is called when terminating an mmu batch or when a batch
 215  * is full. It will perform the flush of all the entries currently stored
 216  * in a batch.
 217  *
 218  * Must be called from within some kind of spinlock/non-preempt region...
 219  */
 220 void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
 221 {
 222         cpumask_t tmp;
 223         int i, local = 0;
 224
 225         i = batch->index;
 226         tmp = cpumask_of_cpu(smp_processor_id());
 227         if (cpus_equal(batch->mm->cpu_vm_mask, tmp))
 228                 local = 1;
 229         if (i == 1)
 230                 flush_hash_page(batch->vaddr[0], batch->pte[0],
 231                                 batch->psize, batch->ssize, local);
 232         else
 233                 flush_hash_range(i, local);
 234         batch->index = 0;
 235 }
 236
 237 void pte_free_finish(void)
 238 {
 239         /* This is safe since tlb_gather_mmu has disabled preemption */
 240         struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
 241
 242         if (*batchp == NULL)
 243                 return;
 244         pte_free_submit(*batchp);
 245         *batchp = NULL;
 246 }
 247
 248 /**
 249  * __flush_hash_table_range - Flush all HPTEs for a given address range
 250  *                            from the hash table (and the TLB). But keeps
 251  *                            the linux PTEs intact.
 252  *
 253  * @mm          : mm_struct of the target address space (generally init_mm)
 254  * @start       : starting address
 255  * @end         : ending address (not included in the flush)
 256  *
 257  * This function is mostly to be used by some IO hotplug code in order
 258  * to remove all hash entries from a given address range used to map IO
 259  * space on a removed PCI-PCI bidge without tearing down the full mapping
 260  * since 64K pages may overlap with other bridges when using 64K pages
 261  * with 4K HW pages on IO space.
 262  *
 263  * Because of that usage pattern, it's only available with CONFIG_HOTPLUG
 264  * and is implemented for small size rather than speed.
 265  */
 266 #ifdef CONFIG_HOTPLUG
 267
 268 void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
 269                               unsigned long end)
 270 {
 271         unsigned long flags;
 272
 273         start = _ALIGN_DOWN(start, PAGE_SIZE);
 274         end = _ALIGN_UP(end, PAGE_SIZE);
 275
 276         BUG_ON(!mm->pgd);
 277
 278         /* Note: Normally, we should only ever use a batch within a
 279          * PTE locked section. This violates the rule, but will work
 280          * since we don't actually modify the PTEs, we just flush the
 281          * hash while leaving the PTEs intact (including their reference
 282          * to being hashed). This is not the most performance oriented
 283          * way to do things but is fine for our needs here.
 284          */
 285         local_irq_save(flags);
 286         arch_enter_lazy_mmu_mode();
 287         for (; start < end; start += PAGE_SIZE) {
 288                 pte_t *ptep = find_linux_pte(mm->pgd, start);
 289                 unsigned long pte;
 290
 291                 if (ptep == NULL)
 292                         continue;
 293                 pte = pte_val(*ptep);
 294                 if (!(pte & _PAGE_HASHPTE))
 295                         continue;
 296                 hpte_need_flush(mm, start, ptep, pte, 0);
 297         }
 298         arch_leave_lazy_mmu_mode();
 299         local_irq_restore(flags);
 300 }
 301
 302 #endif /* CONFIG_HOTPLUG */