arch/powerpc/mm/tlb_nohash_low.S

   1 /*
   2  * This file contains low-level functions for performing various
   3  * types of TLB invalidations on various processors with no hash
   4  * table.
   5  *
   6  * This file implements the following functions for all no-hash
   7  * processors. Some aren't implemented for some variants. Some
   8  * are inline in tlbflush.h
   9  *
  10  *      - tlbil_va
  11  *      - tlbil_pid
  12  *      - tlbil_all
  13  *      - tlbivax_bcast
  14  *
  15  * Code mostly moved over from misc_32.S
  16  *
  17  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  18  *
  19  * Partially rewritten by Cort Dougan (cort@cs.nmt.edu)
  20  * Paul Mackerras, Kumar Gala and Benjamin Herrenschmidt.
  21  *
  22  * This program is free software; you can redistribute it and/or
  23  * modify it under the terms of the GNU General Public License
  24  * as published by the Free Software Foundation; either version
  25  * 2 of the License, or (at your option) any later version.
  26  *
  27  */
  28
  29 #include <asm/reg.h>
  30 #include <asm/page.h>
  31 #include <asm/cputable.h>
  32 #include <asm/mmu.h>
  33 #include <asm/ppc_asm.h>
  34 #include <asm/asm-offsets.h>
  35 #include <asm/processor.h>
  36 #include <asm/bug.h>
  37
  38 #if defined(CONFIG_40x)
  39
  40 /*
  41  * 40x implementation needs only tlbil_va
  42  */
  43 _GLOBAL(__tlbil_va)
  44         /* We run the search with interrupts disabled because we have to change
  45          * the PID and I don't want to preempt when that happens.
  46          */
  47         mfmsr   r5
  48         mfspr   r6,SPRN_PID
  49         wrteei  0
  50         mtspr   SPRN_PID,r4
  51         tlbsx.  r3, 0, r3
  52         mtspr   SPRN_PID,r6
  53         wrtee   r5
  54         bne     1f
  55         sync
  56         /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is
  57          * clear. Since 25 is the V bit in the TLB_TAG, loading this value
  58          * will invalidate the TLB entry. */
  59         tlbwe   r3, r3, TLB_TAG
  60         isync
  61 1:      blr
  62
  63 #elif defined(CONFIG_8xx)
  64
  65 /*
  66  * Nothing to do for 8xx, everything is inline
  67  */
  68
  69 #elif defined(CONFIG_44x) /* Includes 47x */
  70
  71 /*
  72  * 440 implementation uses tlbsx/we for tlbil_va and a full sweep
  73  * of the TLB for everything else.
  74  */
  75 _GLOBAL(__tlbil_va)
  76         mfspr   r5,SPRN_MMUCR
  77         mfmsr   r10
  78
  79         /*
  80          * We write 16 bits of STID since 47x supports that much, we
  81          * will never be passed out of bounds values on 440 (hopefully)
  82          */
  83         rlwimi  r5,r4,0,16,31
  84
  85         /* We have to run the search with interrupts disabled, otherwise
  86          * an interrupt which causes a TLB miss can clobber the MMUCR
  87          * between the mtspr and the tlbsx.
  88          *
  89          * Critical and Machine Check interrupts take care of saving
  90          * and restoring MMUCR, so only normal interrupts have to be
  91          * taken care of.
  92          */
  93         wrteei  0
  94         mtspr   SPRN_MMUCR,r5
  95         tlbsx.  r6,0,r3
  96         bne     10f
  97         sync
  98 BEGIN_MMU_FTR_SECTION
  99         b       2f
 100 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
 101         /* On 440 There are only 64 TLB entries, so r3 < 64, which means bit
 102          * 22, is clear.  Since 22 is the V bit in the TLB_PAGEID, loading this
 103          * value will invalidate the TLB entry.
 104          */
 105         tlbwe   r6,r6,PPC44x_TLB_PAGEID
 106         isync
 107 10:     wrtee   r10
 108         blr
 109 2:
 110 #ifdef CONFIG_PPC_47x
 111         oris    r7,r6,0x8000    /* specify way explicitely */
 112         clrrwi  r4,r3,12        /* get an EPN for the hashing with V = 0 */
 113         ori     r4,r4,PPC47x_TLBE_SIZE
 114         tlbwe   r4,r7,0         /* write it */
 115         isync
 116         wrtee   r10
 117         blr
 118 #else /* CONFIG_PPC_47x */
 119 1:      trap
 120         EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
 121 #endif /* !CONFIG_PPC_47x */
 122
 123 _GLOBAL(_tlbil_all)
 124 _GLOBAL(_tlbil_pid)
 125 BEGIN_MMU_FTR_SECTION
 126         b       2f
 127 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x)
 128         li      r3,0
 129         sync
 130
 131         /* Load high watermark */
 132         lis     r4,tlb_44x_hwater@ha
 133         lwz     r5,tlb_44x_hwater@l(r4)
 134
 135 1:      tlbwe   r3,r3,PPC44x_TLB_PAGEID
 136         addi    r3,r3,1
 137         cmpw    0,r3,r5
 138         ble     1b
 139
 140         isync
 141         blr
 142 2:
 143 #ifdef CONFIG_PPC_47x
 144         /* 476 variant. There's not simple way to do this, hopefully we'll
 145          * try to limit the amount of such full invalidates
 146          */
 147         mfmsr   r11             /* Interrupts off */
 148         wrteei  0
 149         li      r3,-1           /* Current set */
 150         lis     r10,tlb_47x_boltmap@h
 151         ori     r10,r10,tlb_47x_boltmap@l
 152         lis     r7,0x8000       /* Specify way explicitely */
 153
 154         b       9f              /* For each set */
 155
 156 1:      li      r9,4            /* Number of ways */
 157         li      r4,0            /* Current way */
 158         li      r6,0            /* Default entry value 0 */
 159         andi.   r0,r8,1         /* Check if way 0 is bolted */
 160         mtctr   r9              /* Load way counter */
 161         bne-    3f              /* Bolted, skip loading it */
 162
 163 2:      /* For each way */
 164         or      r5,r3,r4        /* Make way|index for tlbre */
 165         rlwimi  r5,r5,16,8,15   /* Copy index into position */
 166         tlbre   r6,r5,0         /* Read entry */
 167 3:      addis   r4,r4,0x2000    /* Next way */
 168         andi.   r0,r6,PPC47x_TLB0_VALID /* Valid entry ? */
 169         beq     4f              /* Nope, skip it */
 170         rlwimi  r7,r5,0,1,2     /* Insert way number */
 171         rlwinm  r6,r6,0,21,19   /* Clear V */
 172         tlbwe   r6,r7,0         /* Write it */
 173 4:      bdnz    2b              /* Loop for each way */
 174         srwi    r8,r8,1         /* Next boltmap bit */
 175 9:      cmpwi   cr1,r3,255      /* Last set done ? */
 176         addi    r3,r3,1         /* Next set */
 177         beq     cr1,1f          /* End of loop */
 178         andi.   r0,r3,0x1f      /* Need to load a new boltmap word ? */
 179         bne     1b              /* No, loop */
 180         lwz     r8,0(r10)       /* Load boltmap entry */
 181         addi    r10,r10,4       /* Next word */
 182         b       1b              /* Then loop */
 183 1:      isync                   /* Sync shadows */
 184         wrtee   r11
 185 #else /* CONFIG_PPC_47x */
 186 1:      trap
 187         EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0;
 188 #endif /* !CONFIG_PPC_47x */
 189         blr
 190
 191 #ifdef CONFIG_PPC_47x
 192 /*
 193  * _tlbivax_bcast is only on 47x. We don't bother doing a runtime
 194  * check though, it will blow up soon enough if we mistakenly try
 195  * to use it on a 440.
 196  */
 197 _GLOBAL(_tlbivax_bcast)
 198         mfspr   r5,SPRN_MMUCR
 199         mfmsr   r10
 200         rlwimi  r5,r4,0,16,31
 201         wrteei  0
 202         mtspr   SPRN_MMUCR,r5
 203 /*      tlbivax 0,r3 - use .long to avoid binutils deps */
 204         .long 0x7c000624 | (r3 << 11)
 205         isync
 206         eieio
 207         tlbsync
 208         sync
 209         wrtee   r10
 210         blr
 211 #endif /* CONFIG_PPC_47x */
 212
 213 #elif defined(CONFIG_FSL_BOOKE)
 214 /*
 215  * FSL BookE implementations.
 216  *
 217  * Since feature sections are using _SECTION_ELSE we need
 218  * to have the larger code path before the _SECTION_ELSE
 219  */
 220
 221 /*
 222  * Flush MMU TLB on the local processor
 223  */
 224 _GLOBAL(_tlbil_all)
 225 BEGIN_MMU_FTR_SECTION
 226         li      r3,(MMUCSR0_TLBFI)@l
 227         mtspr   SPRN_MMUCSR0, r3
 228 1:
 229         mfspr   r3,SPRN_MMUCSR0
 230         andi.   r3,r3,MMUCSR0_TLBFI@l
 231         bne     1b
 232 MMU_FTR_SECTION_ELSE
 233         PPC_TLBILX_ALL(0,0)
 234 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
 235         msync
 236         isync
 237         blr
 238
 239 _GLOBAL(_tlbil_pid)
 240 BEGIN_MMU_FTR_SECTION
 241         slwi    r3,r3,16
 242         mfmsr   r10
 243         wrteei  0
 244         mfspr   r4,SPRN_MAS6    /* save MAS6 */
 245         mtspr   SPRN_MAS6,r3
 246         PPC_TLBILX_PID(0,0)
 247         mtspr   SPRN_MAS6,r4    /* restore MAS6 */
 248         wrtee   r10
 249 MMU_FTR_SECTION_ELSE
 250         li      r3,(MMUCSR0_TLBFI)@l
 251         mtspr   SPRN_MMUCSR0, r3
 252 1:
 253         mfspr   r3,SPRN_MMUCSR0
 254         andi.   r3,r3,MMUCSR0_TLBFI@l
 255         bne     1b
 256 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBILX)
 257         msync
 258         isync
 259         blr
 260
 261 /*
 262  * Flush MMU TLB for a particular address, but only on the local processor
 263  * (no broadcast)
 264  */
 265 _GLOBAL(__tlbil_va)
 266         mfmsr   r10
 267         wrteei  0
 268         slwi    r4,r4,16
 269         ori     r4,r4,(MAS6_ISIZE(BOOK3E_PAGESZ_4K))@l
 270         mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
 271 BEGIN_MMU_FTR_SECTION
 272         tlbsx   0,r3
 273         mfspr   r4,SPRN_MAS1            /* check valid */
 274         andis.  r3,r4,MAS1_VALID@h
 275         beq     1f
 276         rlwinm  r4,r4,0,1,31
 277         mtspr   SPRN_MAS1,r4
 278         tlbwe
 279 MMU_FTR_SECTION_ELSE
 280         PPC_TLBILX_VA(0,r3)
 281 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
 282         msync
 283         isync
 284 1:      wrtee   r10
 285         blr
 286 #elif defined(CONFIG_PPC_BOOK3E)
 287 /*
 288  * New Book3E (>= 2.06) implementation
 289  *
 290  * Note: We may be able to get away without the interrupt masking stuff
 291  * if we save/restore MAS6 on exceptions that might modify it
 292  */
 293 _GLOBAL(_tlbil_pid)
 294         slwi    r4,r3,MAS6_SPID_SHIFT
 295         mfmsr   r10
 296         wrteei  0
 297         mtspr   SPRN_MAS6,r4
 298         PPC_TLBILX_PID(0,0)
 299         wrtee   r10
 300         msync
 301         isync
 302         blr
 303
 304 _GLOBAL(_tlbil_pid_noind)
 305         slwi    r4,r3,MAS6_SPID_SHIFT
 306         mfmsr   r10
 307         ori     r4,r4,MAS6_SIND
 308         wrteei  0
 309         mtspr   SPRN_MAS6,r4
 310         PPC_TLBILX_PID(0,0)
 311         wrtee   r10
 312         msync
 313         isync
 314         blr
 315
 316 _GLOBAL(_tlbil_all)
 317         PPC_TLBILX_ALL(0,0)
 318         msync
 319         isync
 320         blr
 321
 322 _GLOBAL(_tlbil_va)
 323         mfmsr   r10
 324         wrteei  0
 325         cmpwi   cr0,r6,0
 326         slwi    r4,r4,MAS6_SPID_SHIFT
 327         rlwimi  r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
 328         beq     1f
 329         rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
 330 1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
 331         PPC_TLBILX_VA(0,r3)
 332         msync
 333         isync
 334         wrtee   r10
 335         blr
 336
 337 _GLOBAL(_tlbivax_bcast)
 338         mfmsr   r10
 339         wrteei  0
 340         cmpwi   cr0,r6,0
 341         slwi    r4,r4,MAS6_SPID_SHIFT
 342         rlwimi  r4,r5,MAS6_ISIZE_SHIFT,MAS6_ISIZE_MASK
 343         beq     1f
 344         rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
 345 1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
 346         PPC_TLBIVAX(0,r3)
 347         eieio
 348         tlbsync
 349         sync
 350         wrtee   r10
 351         blr
 352
 353 _GLOBAL(set_context)
 354 #ifdef CONFIG_BDI_SWITCH
 355         /* Context switch the PTE pointer for the Abatron BDI2000.
 356          * The PGDIR is the second parameter.
 357          */
 358         lis     r5, abatron_pteptrs@h
 359         ori     r5, r5, abatron_pteptrs@l
 360         stw     r4, 0x4(r5)
 361 #endif
 362         mtspr   SPRN_PID,r3
 363         isync                   /* Force context change */
 364         blr
 365 #else
 366 #error Unsupported processor type !
 367 #endif