2 * Corenet based SoC DS Setup
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * Copyright 2009-2011 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/kdev_t.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
21 #include <asm/machdep.h>
22 #include <asm/pci-bridge.h>
23 #include <asm/pgtable.h>
24 #include <asm/ppc-pci.h>
25 #include <mm/mmu_decl.h>
29 #include <asm/ehv_pic.h>
30 #include <asm/swiotlb.h>
31 #include <soc/fsl/qe/qe_ic.h>
33 #include <linux/of_platform.h>
34 #include <sysdev/fsl_soc.h>
35 #include <sysdev/fsl_pci.h>
39 void __init
corenet_gen_pic_init(void)
42 unsigned int flags
= MPIC_BIG_ENDIAN
| MPIC_SINGLE_DEST_CPU
|
45 struct device_node
*np
;
47 if (ppc_md
.get_irq
== mpic_get_coreint_irq
)
48 flags
|= MPIC_ENABLE_COREINT
;
50 mpic
= mpic_alloc(NULL
, 0, flags
, 0, 512, " OpenPIC ");
55 np
= of_find_compatible_node(NULL
, NULL
, "fsl,qe-ic");
57 qe_ic_init(np
, 0, qe_ic_cascade_low_mpic
,
58 qe_ic_cascade_high_mpic
);
64 * Setup the architecture
66 void __init
corenet_gen_setup_arch(void)
72 pr_info("%s board\n", ppc_md
.name
);
77 static const struct of_device_id of_device_ids
[] = {
79 .compatible
= "simple-bus"
82 .compatible
= "mdio-mux-gpio"
85 .compatible
= "fsl,fpga-ngpixis"
88 .compatible
= "fsl,fpga-qixis"
91 .compatible
= "fsl,srio",
94 .compatible
= "fsl,p4080-pcie",
97 .compatible
= "fsl,qoriq-pcie-v2.2",
100 .compatible
= "fsl,qoriq-pcie-v2.3",
103 .compatible
= "fsl,qoriq-pcie-v2.4",
106 .compatible
= "fsl,qoriq-pcie-v3.0",
109 .compatible
= "fsl,qe",
111 /* The following two are for the Freescale hypervisor */
113 .name
= "hypervisor",
121 int __init
corenet_gen_publish_devices(void)
123 return of_platform_bus_probe(NULL
, of_device_ids
, NULL
);
126 static const char * const boards
[] __initconst
= {
158 * Called very early, device-tree isn't unflattened
160 static int __init
corenet_generic_probe(void)
165 extern struct smp_ops_t smp_85xx_ops
;
168 if (of_device_compatible_match(of_root
, boards
))
171 /* Check if we're running under the Freescale hypervisor */
172 for (i
= 0; boards
[i
]; i
++) {
173 snprintf(hv_compat
, sizeof(hv_compat
), "%s-hv", boards
[i
]);
174 if (of_machine_is_compatible(hv_compat
)) {
175 ppc_md
.init_IRQ
= ehv_pic_init
;
177 ppc_md
.get_irq
= ehv_pic_get_irq
;
178 ppc_md
.restart
= fsl_hv_restart
;
179 pm_power_off
= fsl_hv_halt
;
180 ppc_md
.halt
= fsl_hv_halt
;
183 * Disable the timebase sync operations because we
184 * can't write to the timebase registers under the
187 smp_85xx_ops
.give_timebase
= NULL
;
188 smp_85xx_ops
.take_timebase
= NULL
;
197 define_machine(corenet_generic
) {
198 .name
= "CoreNet Generic",
199 .probe
= corenet_generic_probe
,
200 .setup_arch
= corenet_gen_setup_arch
,
201 .init_IRQ
= corenet_gen_pic_init
,
203 .pcibios_fixup_bus
= fsl_pcibios_fixup_bus
,
204 .pcibios_fixup_phb
= fsl_pcibios_fixup_phb
,
207 * Core reset may cause issues if using the proxy mode of MPIC.
208 * So, use the mixed mode of MPIC if enabling CPU hotplug.
210 * Likewise, problems have been seen with kexec when coreint is enabled.
212 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
213 .get_irq
= mpic_get_irq
,
215 .get_irq
= mpic_get_coreint_irq
,
217 .calibrate_decr
= generic_calibrate_decr
,
218 .progress
= udbg_progress
,
220 .power_save
= book3e_idle
,
222 .power_save
= e500_idle
,
226 machine_arch_initcall(corenet_generic
, corenet_gen_publish_devices
);