arch/powerpc/platforms/85xx/corenet_generic.c

   1 /*
   2  * Corenet based SoC DS Setup
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2009-2011 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/kdev_t.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <asm/time.h>
  21 #include <asm/machdep.h>
  22 #include <asm/pci-bridge.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/ppc-pci.h>
  25 #include <mm/mmu_decl.h>
  26 #include <asm/prom.h>
  27 #include <asm/udbg.h>
  28 #include <asm/mpic.h>
  29 #include <asm/ehv_pic.h>
  30 #include <asm/swiotlb.h>
  31 #include <soc/fsl/qe/qe_ic.h>
  32
  33 #include <linux/of_platform.h>
  34 #include <sysdev/fsl_soc.h>
  35 #include <sysdev/fsl_pci.h>
  36 #include "smp.h"
  37 #include "mpc85xx.h"
  38
  39 void __init corenet_gen_pic_init(void)
  40 {
  41         struct mpic *mpic;
  42         unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
  43                 MPIC_NO_RESET;
  44
  45         struct device_node *np;
  46
  47         if (ppc_md.get_irq == mpic_get_coreint_irq)
  48                 flags |= MPIC_ENABLE_COREINT;
  49
  50         mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC  ");
  51         BUG_ON(mpic == NULL);
  52
  53         mpic_init(mpic);
  54
  55         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  56         if (np) {
  57                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
  58                                 qe_ic_cascade_high_mpic);
  59                 of_node_put(np);
  60         }
  61 }
  62
  63 /*
  64  * Setup the architecture
  65  */
  66 void __init corenet_gen_setup_arch(void)
  67 {
  68         mpc85xx_smp_init();
  69
  70         swiotlb_detect_4g();
  71
  72         pr_info("%s board\n", ppc_md.name);
  73
  74         mpc85xx_qe_init();
  75 }
  76
  77 static const struct of_device_id of_device_ids[] = {
  78         {
  79                 .compatible     = "simple-bus"
  80         },
  81         {
  82                 .compatible     = "mdio-mux-gpio"
  83         },
  84         {
  85                 .compatible     = "fsl,fpga-ngpixis"
  86         },
  87         {
  88                 .compatible     = "fsl,fpga-qixis"
  89         },
  90         {
  91                 .compatible     = "fsl,srio",
  92         },
  93         {
  94                 .compatible     = "fsl,p4080-pcie",
  95         },
  96         {
  97                 .compatible     = "fsl,qoriq-pcie-v2.2",
  98         },
  99         {
 100                 .compatible     = "fsl,qoriq-pcie-v2.3",
 101         },
 102         {
 103                 .compatible     = "fsl,qoriq-pcie-v2.4",
 104         },
 105         {
 106                 .compatible     = "fsl,qoriq-pcie-v3.0",
 107         },
 108         {
 109                 .compatible     = "fsl,qe",
 110         },
 111         /* The following two are for the Freescale hypervisor */
 112         {
 113                 .name           = "hypervisor",
 114         },
 115         {
 116                 .name           = "handles",
 117         },
 118         {}
 119 };
 120
 121 int __init corenet_gen_publish_devices(void)
 122 {
 123         return of_platform_bus_probe(NULL, of_device_ids, NULL);
 124 }
 125
 126 static const char * const boards[] __initconst = {
 127         "fsl,P2041RDB",
 128         "fsl,P3041DS",
 129         "fsl,OCA4080",
 130         "fsl,P4080DS",
 131         "fsl,P5020DS",
 132         "fsl,P5040DS",
 133         "fsl,T2080QDS",
 134         "fsl,T2080RDB",
 135         "fsl,T2081QDS",
 136         "fsl,T4240QDS",
 137         "fsl,T4240RDB",
 138         "fsl,B4860QDS",
 139         "fsl,B4420QDS",
 140         "fsl,B4220QDS",
 141         "fsl,T1023RDB",
 142         "fsl,T1024QDS",
 143         "fsl,T1024RDB",
 144         "fsl,T1040D4RDB",
 145         "fsl,T1042D4RDB",
 146         "fsl,T1040QDS",
 147         "fsl,T1042QDS",
 148         "fsl,T1040RDB",
 149         "fsl,T1042RDB",
 150         "fsl,T1042RDB_PI",
 151         "keymile,kmcent2",
 152         "keymile,kmcoge4",
 153         "varisys,CYRUS",
 154         NULL
 155 };
 156
 157 /*
 158  * Called very early, device-tree isn't unflattened
 159  */
 160 static int __init corenet_generic_probe(void)
 161 {
 162         char hv_compat[24];
 163         int i;
 164 #ifdef CONFIG_SMP
 165         extern struct smp_ops_t smp_85xx_ops;
 166 #endif
 167
 168         if (of_device_compatible_match(of_root, boards))
 169                 return 1;
 170
 171         /* Check if we're running under the Freescale hypervisor */
 172         for (i = 0; boards[i]; i++) {
 173                 snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]);
 174                 if (of_machine_is_compatible(hv_compat)) {
 175                         ppc_md.init_IRQ = ehv_pic_init;
 176
 177                         ppc_md.get_irq = ehv_pic_get_irq;
 178                         ppc_md.restart = fsl_hv_restart;
 179                         pm_power_off = fsl_hv_halt;
 180                         ppc_md.halt = fsl_hv_halt;
 181 #ifdef CONFIG_SMP
 182                         /*
 183                          * Disable the timebase sync operations because we
 184                          * can't write to the timebase registers under the
 185                          * hypervisor.
 186                          */
 187                         smp_85xx_ops.give_timebase = NULL;
 188                         smp_85xx_ops.take_timebase = NULL;
 189 #endif
 190                         return 1;
 191                 }
 192         }
 193
 194         return 0;
 195 }
 196
 197 define_machine(corenet_generic) {
 198         .name                   = "CoreNet Generic",
 199         .probe                  = corenet_generic_probe,
 200         .setup_arch             = corenet_gen_setup_arch,
 201         .init_IRQ               = corenet_gen_pic_init,
 202 #ifdef CONFIG_PCI
 203         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 204         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 205 #endif
 206 /*
 207  * Core reset may cause issues if using the proxy mode of MPIC.
 208  * So, use the mixed mode of MPIC if enabling CPU hotplug.
 209  *
 210  * Likewise, problems have been seen with kexec when coreint is enabled.
 211  */
 212 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
 213         .get_irq                = mpic_get_irq,
 214 #else
 215         .get_irq                = mpic_get_coreint_irq,
 216 #endif
 217         .calibrate_decr         = generic_calibrate_decr,
 218         .progress               = udbg_progress,
 219 #ifdef CONFIG_PPC64
 220         .power_save             = book3e_idle,
 221 #else
 222         .power_save             = e500_idle,
 223 #endif
 224 };
 225
 226 machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);