2 * MPC85xx setup and early boot code plus other random bits.
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 * Copyright 2005 Freescale Semiconductor Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/stddef.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/kdev_t.h>
18 #include <linux/delay.h>
19 #include <linux/seq_file.h>
20 #include <linux/of_platform.h>
23 #include <asm/machdep.h>
24 #include <asm/pci-bridge.h>
26 #include <mm/mmu_decl.h>
29 #include <sysdev/fsl_soc.h>
30 #include <sysdev/fsl_pci.h>
34 #include <sysdev/cpm2_pic.h>
39 static void __init
mpc85xx_ads_pic_init(void)
41 struct mpic
*mpic
= mpic_alloc(NULL
, 0, MPIC_BIG_ENDIAN
,
46 mpc85xx_cpm2_pic_init();
50 * Setup the architecture
57 static const struct cpm_pin mpc8560_ads_pins
[] = {
59 {3, 29, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
60 {3, 30, CPM_PIN_OUTPUT
| CPM_PIN_SECONDARY
},
61 {3, 31, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
64 {2, 12, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
65 {2, 13, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
66 {3, 26, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
67 {3, 27, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
68 {3, 28, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
71 {1, 18, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
72 {1, 19, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
73 {1, 20, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
74 {1, 21, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
75 {1, 22, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
76 {1, 23, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
77 {1, 24, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
78 {1, 25, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
79 {1, 26, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
80 {1, 27, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
81 {1, 28, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
82 {1, 29, CPM_PIN_OUTPUT
| CPM_PIN_SECONDARY
},
83 {1, 30, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
84 {1, 31, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
85 {2, 18, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
}, /* CLK14 */
86 {2, 19, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
}, /* CLK13 */
89 {1, 4, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
90 {1, 5, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
91 {1, 6, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
92 {1, 8, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
93 {1, 9, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
94 {1, 10, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
95 {1, 11, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
96 {1, 12, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
97 {1, 13, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
98 {1, 14, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
99 {1, 15, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
100 {1, 16, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
101 {1, 17, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
},
102 {2, 16, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
}, /* CLK16 */
103 {2, 17, CPM_PIN_INPUT
| CPM_PIN_PRIMARY
}, /* CLK15 */
104 {2, 27, CPM_PIN_OUTPUT
| CPM_PIN_PRIMARY
},
107 static void __init
init_ioports(void)
111 for (i
= 0; i
< ARRAY_SIZE(mpc8560_ads_pins
); i
++) {
112 const struct cpm_pin
*pin
= &mpc8560_ads_pins
[i
];
113 cpm2_set_pin(pin
->port
, pin
->pin
, pin
->flags
);
116 cpm2_clk_setup(CPM_CLK_SCC1
, CPM_BRG1
, CPM_CLK_RX
);
117 cpm2_clk_setup(CPM_CLK_SCC1
, CPM_BRG1
, CPM_CLK_TX
);
118 cpm2_clk_setup(CPM_CLK_SCC2
, CPM_BRG2
, CPM_CLK_RX
);
119 cpm2_clk_setup(CPM_CLK_SCC2
, CPM_BRG2
, CPM_CLK_TX
);
120 cpm2_clk_setup(CPM_CLK_FCC2
, CPM_CLK13
, CPM_CLK_RX
);
121 cpm2_clk_setup(CPM_CLK_FCC2
, CPM_CLK14
, CPM_CLK_TX
);
122 cpm2_clk_setup(CPM_CLK_FCC3
, CPM_CLK15
, CPM_CLK_RX
);
123 cpm2_clk_setup(CPM_CLK_FCC3
, CPM_CLK16
, CPM_CLK_TX
);
127 static void __init
mpc85xx_ads_setup_arch(void)
130 ppc_md
.progress("mpc85xx_ads_setup_arch()", 0);
137 fsl_pci_assign_primary();
140 static void mpc85xx_ads_show_cpuinfo(struct seq_file
*m
)
142 uint pvid
, svid
, phid1
;
144 pvid
= mfspr(SPRN_PVR
);
145 svid
= mfspr(SPRN_SVR
);
147 seq_printf(m
, "Vendor\t\t: Freescale Semiconductor\n");
148 seq_printf(m
, "PVR\t\t: 0x%x\n", pvid
);
149 seq_printf(m
, "SVR\t\t: 0x%x\n", svid
);
151 /* Display cpu Pll setting */
152 phid1
= mfspr(SPRN_HID1
);
153 seq_printf(m
, "PLL setting\t: 0x%x\n", ((phid1
>> 24) & 0x3f));
156 machine_arch_initcall(mpc85xx_ads
, mpc85xx_common_publish_devices
);
159 * Called very early, device-tree isn't unflattened
161 static int __init
mpc85xx_ads_probe(void)
163 return of_machine_is_compatible("MPC85xxADS");
166 define_machine(mpc85xx_ads
) {
167 .name
= "MPC85xx ADS",
168 .probe
= mpc85xx_ads_probe
,
169 .setup_arch
= mpc85xx_ads_setup_arch
,
170 .init_IRQ
= mpc85xx_ads_pic_init
,
171 .show_cpuinfo
= mpc85xx_ads_show_cpuinfo
,
172 .get_irq
= mpic_get_irq
,
173 .restart
= fsl_rstcr_restart
,
174 .calibrate_decr
= generic_calibrate_decr
,
175 .progress
= udbg_progress
,