arch/powerpc/platforms/85xx/mpc85xx_cds.c

   1 /*
   2  * MPC85xx setup and early boot code plus other random bits.
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/major.h>
  22 #include <linux/console.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/initrd.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/fsl_devices.h>
  28 #include <linux/of_platform.h>
  29
  30 #include <asm/pgtable.h>
  31 #include <asm/page.h>
  32 #include <linux/atomic.h>
  33 #include <asm/time.h>
  34 #include <asm/io.h>
  35 #include <asm/machdep.h>
  36 #include <asm/ipic.h>
  37 #include <asm/pci-bridge.h>
  38 #include <asm/irq.h>
  39 #include <mm/mmu_decl.h>
  40 #include <asm/prom.h>
  41 #include <asm/udbg.h>
  42 #include <asm/mpic.h>
  43 #include <asm/i8259.h>
  44
  45 #include <sysdev/fsl_soc.h>
  46 #include <sysdev/fsl_pci.h>
  47
  48 #include "mpc85xx.h"
  49
  50 /*
  51  * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
  52  * various logic and performs system control functions.
  53  * Here is the FPGA/CPLD register map.
  54  */
  55 struct cadmus_reg {
  56         u8 cm_ver;              /* Board version */
  57         u8 cm_csr;              /* General control/status */
  58         u8 cm_rst;              /* Reset control */
  59         u8 cm_hsclk;    /* High speed clock */
  60         u8 cm_hsxclk;   /* High speed clock extended */
  61         u8 cm_led;              /* LED data */
  62         u8 cm_pci;              /* PCI control/status */
  63         u8 cm_dma;              /* DMA control */
  64         u8 res[248];    /* Total 256 bytes */
  65 };
  66
  67 static struct cadmus_reg *cadmus;
  68
  69 #ifdef CONFIG_PCI
  70
  71 #define ARCADIA_HOST_BRIDGE_IDSEL       17
  72 #define ARCADIA_2ND_BRIDGE_IDSEL        3
  73
  74 static int mpc85xx_exclude_device(struct pci_controller *hose,
  75                                   u_char bus, u_char devfn)
  76 {
  77         /* We explicitly do not go past the Tundra 320 Bridge */
  78         if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  79                 return PCIBIOS_DEVICE_NOT_FOUND;
  80         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  81                 return PCIBIOS_DEVICE_NOT_FOUND;
  82         else
  83                 return PCIBIOS_SUCCESSFUL;
  84 }
  85
  86 static void mpc85xx_cds_restart(char *cmd)
  87 {
  88         struct pci_dev *dev;
  89         u_char tmp;
  90
  91         if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
  92                                         NULL))) {
  93
  94                 /* Use the VIA Super Southbridge to force a PCI reset */
  95                 pci_read_config_byte(dev, 0x47, &tmp);
  96                 pci_write_config_byte(dev, 0x47, tmp | 1);
  97
  98                 /* Flush the outbound PCI write queues */
  99                 pci_read_config_byte(dev, 0x47, &tmp);
 100
 101                 /*
 102                  *  At this point, the harware reset should have triggered.
 103                  *  However, if it doesn't work for some mysterious reason,
 104                  *  just fall through to the default reset below.
 105                  */
 106
 107                 pci_dev_put(dev);
 108         }
 109
 110         /*
 111          *  If we can't find the VIA chip (maybe the P2P bridge is disabled)
 112          *  or the VIA chip reset didn't work, just use the default reset.
 113          */
 114         fsl_rstcr_restart(NULL);
 115 }
 116
 117 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
 118 {
 119         u_char c;
 120         if (dev->vendor == PCI_VENDOR_ID_VIA) {
 121                 switch (dev->device) {
 122                 case PCI_DEVICE_ID_VIA_82C586_1:
 123                         /*
 124                          * U-Boot does not set the enable bits
 125                          * for the IDE device. Force them on here.
 126                          */
 127                         pci_read_config_byte(dev, 0x40, &c);
 128                         c |= 0x03; /* IDE: Chip Enable Bits */
 129                         pci_write_config_byte(dev, 0x40, c);
 130
 131                         /*
 132                          * Since only primary interface works, force the
 133                          * IDE function to standard primary IDE interrupt
 134                          * w/ 8259 offset
 135                          */
 136                         dev->irq = 14;
 137                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 138                         break;
 139                 /*
 140                  * Force legacy USB interrupt routing
 141                  */
 142                 case PCI_DEVICE_ID_VIA_82C586_2:
 143                 /* There are two USB controllers.
 144                  * Identify them by functon number
 145                  */
 146                         if (PCI_FUNC(dev->devfn) == 3)
 147                                 dev->irq = 11;
 148                         else
 149                                 dev->irq = 10;
 150                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 151                 default:
 152                         break;
 153                 }
 154         }
 155 }
 156
 157 static void skip_fake_bridge(struct pci_dev *dev)
 158 {
 159         /* Make it an error to skip the fake bridge
 160          * in pci_setup_device() in probe.c */
 161         dev->hdr_type = 0x7f;
 162 }
 163 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
 164 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
 165 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
 166
 167 #define PCI_DEVICE_ID_IDT_TSI310        0x01a7
 168
 169 /*
 170  * Fix Tsi310 PCI-X bridge resource.
 171  * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
 172  * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
 173  */
 174 void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
 175 {
 176         struct pci_dev *dev = bus->self;
 177         struct resource *res = bus->resource[0];
 178
 179         if (dev != NULL &&
 180             dev->vendor == PCI_VENDOR_ID_IBM &&
 181             dev->device == PCI_DEVICE_ID_IDT_TSI310) {
 182                 if (res) {
 183                         res->start = 0;
 184                         res->end   = 0x1fff;
 185                         res->flags = IORESOURCE_IO;
 186                         pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
 187                         pr_info("mpc85xx_cds: %pR\n", res);
 188                 }
 189         }
 190
 191         fsl_pcibios_fixup_bus(bus);
 192 }
 193
 194 #ifdef CONFIG_PPC_I8259
 195 static void mpc85xx_8259_cascade_handler(struct irq_desc *desc)
 196 {
 197         unsigned int cascade_irq = i8259_irq();
 198
 199         if (cascade_irq != NO_IRQ)
 200                 /* handle an interrupt from the 8259 */
 201                 generic_handle_irq(cascade_irq);
 202
 203         /* check for any interrupts from the shared IRQ line */
 204         handle_fasteoi_irq(desc);
 205 }
 206
 207 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
 208 {
 209         return IRQ_HANDLED;
 210 }
 211
 212 static struct irqaction mpc85xxcds_8259_irqaction = {
 213         .handler = mpc85xx_8259_cascade_action,
 214         .flags = IRQF_SHARED | IRQF_NO_THREAD,
 215         .name = "8259 cascade",
 216 };
 217 #endif /* PPC_I8259 */
 218 #endif /* CONFIG_PCI */
 219
 220 static void __init mpc85xx_cds_pic_init(void)
 221 {
 222         struct mpic *mpic;
 223         mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
 224                         0, 256, " OpenPIC  ");
 225         BUG_ON(mpic == NULL);
 226         mpic_init(mpic);
 227 }
 228
 229 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
 230 static int mpc85xx_cds_8259_attach(void)
 231 {
 232         int ret;
 233         struct device_node *np = NULL;
 234         struct device_node *cascade_node = NULL;
 235         int cascade_irq;
 236
 237         /* Initialize the i8259 controller */
 238         for_each_node_by_type(np, "interrupt-controller")
 239                 if (of_device_is_compatible(np, "chrp,iic")) {
 240                         cascade_node = np;
 241                         break;
 242                 }
 243
 244         if (cascade_node == NULL) {
 245                 printk(KERN_DEBUG "Could not find i8259 PIC\n");
 246                 return -ENODEV;
 247         }
 248
 249         cascade_irq = irq_of_parse_and_map(cascade_node, 0);
 250         if (cascade_irq == NO_IRQ) {
 251                 printk(KERN_ERR "Failed to map cascade interrupt\n");
 252                 return -ENXIO;
 253         }
 254
 255         i8259_init(cascade_node, 0);
 256         of_node_put(cascade_node);
 257
 258         /*
 259          *  Hook the interrupt to make sure desc->action is never NULL.
 260          *  This is required to ensure that the interrupt does not get
 261          *  disabled when the last user of the shared IRQ line frees their
 262          *  interrupt.
 263          */
 264         if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
 265                 printk(KERN_ERR "Failed to setup cascade interrupt\n");
 266                 return ret;
 267         }
 268
 269         /* Success. Connect our low-level cascade handler. */
 270         irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
 271
 272         return 0;
 273 }
 274 machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
 275
 276 #endif /* CONFIG_PPC_I8259 */
 277
 278 static void mpc85xx_cds_pci_assign_primary(void)
 279 {
 280 #ifdef CONFIG_PCI
 281         struct device_node *np;
 282
 283         if (fsl_pci_primary)
 284                 return;
 285
 286         /*
 287          * MPC85xx_CDS has ISA bridge but unfortunately there is no
 288          * isa node in device tree. We now looking for i8259 node as
 289          * a workaround for such a broken device tree. This routine
 290          * is for complying to all device trees.
 291          */
 292         np = of_find_node_by_name(NULL, "i8259");
 293         while ((fsl_pci_primary = of_get_parent(np))) {
 294                 of_node_put(np);
 295                 np = fsl_pci_primary;
 296
 297                 if ((of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 298                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) &&
 299                     of_device_is_available(np))
 300                         return;
 301         }
 302 #endif
 303 }
 304
 305 /*
 306  * Setup the architecture
 307  */
 308 static void __init mpc85xx_cds_setup_arch(void)
 309 {
 310         struct device_node *np;
 311         int cds_pci_slot;
 312
 313         if (ppc_md.progress)
 314                 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
 315
 316         np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
 317         if (!np) {
 318                 pr_err("Could not find FPGA node.\n");
 319                 return;
 320         }
 321
 322         cadmus = of_iomap(np, 0);
 323         of_node_put(np);
 324         if (!cadmus) {
 325                 pr_err("Fail to map FPGA area.\n");
 326                 return;
 327         }
 328
 329         if (ppc_md.progress) {
 330                 char buf[40];
 331                 cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
 332                 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
 333                                 in_8(&cadmus->cm_ver), cds_pci_slot);
 334                 ppc_md.progress(buf, 0);
 335         }
 336
 337 #ifdef CONFIG_PCI
 338         ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
 339         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 340 #endif
 341
 342         mpc85xx_cds_pci_assign_primary();
 343         fsl_pci_assign_primary();
 344 }
 345
 346 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
 347 {
 348         uint pvid, svid, phid1;
 349
 350         pvid = mfspr(SPRN_PVR);
 351         svid = mfspr(SPRN_SVR);
 352
 353         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 354         seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
 355                         in_8(&cadmus->cm_ver));
 356         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 357         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 358
 359         /* Display cpu Pll setting */
 360         phid1 = mfspr(SPRN_HID1);
 361         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 362 }
 363
 364
 365 /*
 366  * Called very early, device-tree isn't unflattened
 367  */
 368 static int __init mpc85xx_cds_probe(void)
 369 {
 370         unsigned long root = of_get_flat_dt_root();
 371
 372         return of_flat_dt_is_compatible(root, "MPC85xxCDS");
 373 }
 374
 375 machine_arch_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
 376
 377 define_machine(mpc85xx_cds) {
 378         .name           = "MPC85xx CDS",
 379         .probe          = mpc85xx_cds_probe,
 380         .setup_arch     = mpc85xx_cds_setup_arch,
 381         .init_IRQ       = mpc85xx_cds_pic_init,
 382         .show_cpuinfo   = mpc85xx_cds_show_cpuinfo,
 383         .get_irq        = mpic_get_irq,
 384 #ifdef CONFIG_PCI
 385         .restart        = mpc85xx_cds_restart,
 386         .pcibios_fixup_bus      = mpc85xx_cds_fixup_bus,
 387         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 388 #else
 389         .restart        = fsl_rstcr_restart,
 390 #endif
 391         .calibrate_decr = generic_calibrate_decr,
 392         .progress       = udbg_progress,
 393 };