arch/powerpc/platforms/85xx/mpc85xx_mds.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
   4  * All rights reserved.
   5  *
   6  * Author: Andy Fleming <afleming@freescale.com>
   7  *
   8  * Based on 83xx/mpc8360e_pb.c by:
   9  *         Li Yang <LeoLi@freescale.com>
  10  *         Yin Olivia <Hong-hua.Yin@freescale.com>
  11  *
  12  * Description:
  13  * MPC85xx MDS board specific routines.
  14  */
  15
  16 #include <linux/stddef.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/errno.h>
  20 #include <linux/reboot.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/major.h>
  24 #include <linux/console.h>
  25 #include <linux/delay.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/initrd.h>
  28 #include <linux/fsl_devices.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/of_device.h>
  31 #include <linux/phy.h>
  32 #include <linux/memblock.h>
  33 #include <linux/fsl/guts.h>
  34
  35 #include <linux/atomic.h>
  36 #include <asm/time.h>
  37 #include <asm/io.h>
  38 #include <asm/machdep.h>
  39 #include <asm/pci-bridge.h>
  40 #include <asm/irq.h>
  41 #include <mm/mmu_decl.h>
  42 #include <asm/prom.h>
  43 #include <asm/udbg.h>
  44 #include <sysdev/fsl_soc.h>
  45 #include <sysdev/fsl_pci.h>
  46 #include <sysdev/simple_gpio.h>
  47 #include <soc/fsl/qe/qe.h>
  48 #include <soc/fsl/qe/qe_ic.h>
  49 #include <asm/mpic.h>
  50 #include <asm/swiotlb.h>
  51 #include "smp.h"
  52
  53 #include "mpc85xx.h"
  54
  55 #undef DEBUG
  56 #ifdef DEBUG
  57 #define DBG(fmt...) udbg_printf(fmt)
  58 #else
  59 #define DBG(fmt...)
  60 #endif
  61
  62 #if IS_BUILTIN(CONFIG_PHYLIB)
  63
  64 #define MV88E1111_SCR   0x10
  65 #define MV88E1111_SCR_125CLK    0x0010
  66 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
  67 {
  68         int scr;
  69         int err;
  70
  71         /* Workaround for the 125 CLK Toggle */
  72         scr = phy_read(phydev, MV88E1111_SCR);
  73
  74         if (scr < 0)
  75                 return scr;
  76
  77         err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
  78
  79         if (err)
  80                 return err;
  81
  82         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  83
  84         if (err)
  85                 return err;
  86
  87         scr = phy_read(phydev, MV88E1111_SCR);
  88
  89         if (scr < 0)
  90                 return scr;
  91
  92         err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
  93
  94         return err;
  95 }
  96
  97 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
  98 {
  99         int temp;
 100         int err;
 101
 102         /* Errata */
 103         err = phy_write(phydev,29, 0x0006);
 104
 105         if (err)
 106                 return err;
 107
 108         temp = phy_read(phydev, 30);
 109
 110         if (temp < 0)
 111                 return temp;
 112
 113         temp = (temp & (~0x8000)) | 0x4000;
 114         err = phy_write(phydev,30, temp);
 115
 116         if (err)
 117                 return err;
 118
 119         err = phy_write(phydev,29, 0x000a);
 120
 121         if (err)
 122                 return err;
 123
 124         temp = phy_read(phydev, 30);
 125
 126         if (temp < 0)
 127                 return temp;
 128
 129         temp = phy_read(phydev, 30);
 130
 131         if (temp < 0)
 132                 return temp;
 133
 134         temp &= ~0x0020;
 135
 136         err = phy_write(phydev,30,temp);
 137
 138         if (err)
 139                 return err;
 140
 141         /* Disable automatic MDI/MDIX selection */
 142         temp = phy_read(phydev, 16);
 143
 144         if (temp < 0)
 145                 return temp;
 146
 147         temp &= ~0x0060;
 148         err = phy_write(phydev,16,temp);
 149
 150         return err;
 151 }
 152
 153 #endif
 154
 155 /* ************************************************************************
 156  *
 157  * Setup the architecture
 158  *
 159  */
 160 #ifdef CONFIG_QUICC_ENGINE
 161 static void __init mpc85xx_mds_reset_ucc_phys(void)
 162 {
 163         struct device_node *np;
 164         static u8 __iomem *bcsr_regs;
 165
 166         /* Map BCSR area */
 167         np = of_find_node_by_name(NULL, "bcsr");
 168         if (!np)
 169                 return;
 170
 171         bcsr_regs = of_iomap(np, 0);
 172         of_node_put(np);
 173         if (!bcsr_regs)
 174                 return;
 175
 176         if (machine_is(mpc8568_mds)) {
 177 #define BCSR_UCC1_GETH_EN       (0x1 << 7)
 178 #define BCSR_UCC2_GETH_EN       (0x1 << 7)
 179 #define BCSR_UCC1_MODE_MSK      (0x3 << 4)
 180 #define BCSR_UCC2_MODE_MSK      (0x3 << 0)
 181
 182                 /* Turn off UCC1 & UCC2 */
 183                 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 184                 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 185
 186                 /* Mode is RGMII, all bits clear */
 187                 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
 188                                          BCSR_UCC2_MODE_MSK);
 189
 190                 /* Turn UCC1 & UCC2 on */
 191                 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 192                 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 193         } else if (machine_is(mpc8569_mds)) {
 194 #define BCSR7_UCC12_GETHnRST    (0x1 << 2)
 195 #define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
 196 #define BCSR_UCC_RGMII          (0x1 << 6)
 197 #define BCSR_UCC_RTBI           (0x1 << 5)
 198                 /*
 199                  * U-Boot mangles interrupt polarity for Marvell PHYs,
 200                  * so reset built-in and UEM Marvell PHYs, this puts
 201                  * the PHYs into their normal state.
 202                  */
 203                 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
 204                 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 205
 206                 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
 207                 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 208
 209                 for_each_compatible_node(np, "network", "ucc_geth") {
 210                         const unsigned int *prop;
 211                         int ucc_num;
 212
 213                         prop = of_get_property(np, "cell-index", NULL);
 214                         if (prop == NULL)
 215                                 continue;
 216
 217                         ucc_num = *prop - 1;
 218
 219                         prop = of_get_property(np, "phy-connection-type", NULL);
 220                         if (prop == NULL)
 221                                 continue;
 222
 223                         if (strcmp("rtbi", (const char *)prop) == 0)
 224                                 clrsetbits_8(&bcsr_regs[7 + ucc_num],
 225                                         BCSR_UCC_RGMII, BCSR_UCC_RTBI);
 226                 }
 227         } else if (machine_is(p1021_mds)) {
 228 #define BCSR11_ENET_MICRST     (0x1 << 5)
 229                 /* Reset Micrel PHY */
 230                 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
 231                 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
 232         }
 233
 234         iounmap(bcsr_regs);
 235 }
 236
 237 static void __init mpc85xx_mds_qe_init(void)
 238 {
 239         struct device_node *np;
 240
 241         mpc85xx_qe_init();
 242         mpc85xx_qe_par_io_init();
 243         mpc85xx_mds_reset_ucc_phys();
 244
 245         if (machine_is(p1021_mds)) {
 246
 247                 struct ccsr_guts __iomem *guts;
 248
 249                 np = of_find_node_by_name(NULL, "global-utilities");
 250                 if (np) {
 251                         guts = of_iomap(np, 0);
 252                         if (!guts)
 253                                 pr_err("mpc85xx-rdb: could not map global utilities register\n");
 254                         else{
 255                         /* P1021 has pins muxed for QE and other functions. To
 256                          * enable QE UEC mode, we need to set bit QE0 for UCC1
 257                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
 258                          * and QE12 for QE MII management signals in PMUXCR
 259                          * register.
 260                          */
 261                                 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
 262                                                   MPC85xx_PMUXCR_QE(3) |
 263                                                   MPC85xx_PMUXCR_QE(9) |
 264                                                   MPC85xx_PMUXCR_QE(12));
 265                                 iounmap(guts);
 266                         }
 267                         of_node_put(np);
 268                 }
 269
 270         }
 271 }
 272
 273 static void __init mpc85xx_mds_qeic_init(void)
 274 {
 275         struct device_node *np;
 276
 277         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
 278         if (!of_device_is_available(np)) {
 279                 of_node_put(np);
 280                 return;
 281         }
 282
 283         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 284         if (!np) {
 285                 np = of_find_node_by_type(NULL, "qeic");
 286                 if (!np)
 287                         return;
 288         }
 289
 290         if (machine_is(p1021_mds))
 291                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
 292                                 qe_ic_cascade_high_mpic);
 293         else
 294                 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
 295         of_node_put(np);
 296 }
 297 #else
 298 static void __init mpc85xx_mds_qe_init(void) { }
 299 static void __init mpc85xx_mds_qeic_init(void) { }
 300 #endif  /* CONFIG_QUICC_ENGINE */
 301
 302 static void __init mpc85xx_mds_setup_arch(void)
 303 {
 304         if (ppc_md.progress)
 305                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
 306
 307         mpc85xx_smp_init();
 308
 309         mpc85xx_mds_qe_init();
 310
 311         fsl_pci_assign_primary();
 312
 313         swiotlb_detect_4g();
 314 }
 315
 316 #if IS_BUILTIN(CONFIG_PHYLIB)
 317
 318 static int __init board_fixups(void)
 319 {
 320         char phy_id[20];
 321         char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
 322         struct device_node *mdio;
 323         struct resource res;
 324         int i;
 325
 326         for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
 327                 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
 328
 329                 of_address_to_resource(mdio, 0, &res);
 330                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
 331                         (unsigned long long)res.start, 1);
 332
 333                 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
 334                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
 335
 336                 /* Register a workaround for errata */
 337                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
 338                         (unsigned long long)res.start, 7);
 339                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
 340
 341                 of_node_put(mdio);
 342         }
 343
 344         return 0;
 345 }
 346
 347 machine_arch_initcall(mpc8568_mds, board_fixups);
 348 machine_arch_initcall(mpc8569_mds, board_fixups);
 349
 350 #endif
 351
 352 static int __init mpc85xx_publish_devices(void)
 353 {
 354         if (machine_is(mpc8568_mds))
 355                 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
 356         if (machine_is(mpc8569_mds))
 357                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 358
 359         return mpc85xx_common_publish_devices();
 360 }
 361
 362 machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
 363 machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
 364 machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
 365
 366 static void __init mpc85xx_mds_pic_init(void)
 367 {
 368         struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
 369                         MPIC_SINGLE_DEST_CPU,
 370                         0, 256, " OpenPIC  ");
 371         BUG_ON(mpic == NULL);
 372
 373         mpic_init(mpic);
 374         mpc85xx_mds_qeic_init();
 375 }
 376
 377 static int __init mpc85xx_mds_probe(void)
 378 {
 379         return of_machine_is_compatible("MPC85xxMDS");
 380 }
 381
 382 define_machine(mpc8568_mds) {
 383         .name           = "MPC8568 MDS",
 384         .probe          = mpc85xx_mds_probe,
 385         .setup_arch     = mpc85xx_mds_setup_arch,
 386         .init_IRQ       = mpc85xx_mds_pic_init,
 387         .get_irq        = mpic_get_irq,
 388         .calibrate_decr = generic_calibrate_decr,
 389         .progress       = udbg_progress,
 390 #ifdef CONFIG_PCI
 391         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 392         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 393 #endif
 394 };
 395
 396 static int __init mpc8569_mds_probe(void)
 397 {
 398         return of_machine_is_compatible("fsl,MPC8569EMDS");
 399 }
 400
 401 define_machine(mpc8569_mds) {
 402         .name           = "MPC8569 MDS",
 403         .probe          = mpc8569_mds_probe,
 404         .setup_arch     = mpc85xx_mds_setup_arch,
 405         .init_IRQ       = mpc85xx_mds_pic_init,
 406         .get_irq        = mpic_get_irq,
 407         .calibrate_decr = generic_calibrate_decr,
 408         .progress       = udbg_progress,
 409 #ifdef CONFIG_PCI
 410         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 411         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 412 #endif
 413 };
 414
 415 static int __init p1021_mds_probe(void)
 416 {
 417         return of_machine_is_compatible("fsl,P1021MDS");
 418
 419 }
 420
 421 define_machine(p1021_mds) {
 422         .name           = "P1021 MDS",
 423         .probe          = p1021_mds_probe,
 424         .setup_arch     = mpc85xx_mds_setup_arch,
 425         .init_IRQ       = mpc85xx_mds_pic_init,
 426         .get_irq        = mpic_get_irq,
 427         .calibrate_decr = generic_calibrate_decr,
 428         .progress       = udbg_progress,
 429 #ifdef CONFIG_PCI
 430         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 431         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
 432 #endif
 433 };