2 * P1022 RDK board specific routines
4 * Copyright 2012 Freescale Semiconductor, Inc.
6 * Author: Timur Tabi <timur@freescale.com>
10 * This file is licensed under the terms of the GNU General Public License
11 * version 2. This program is licensed "as is" without any warranty of any
12 * kind, whether express or implied.
15 #include <linux/pci.h>
16 #include <linux/of_platform.h>
17 #include <asm/div64.h>
19 #include <asm/swiotlb.h>
21 #include <sysdev/fsl_soc.h>
22 #include <sysdev/fsl_pci.h>
24 #include <asm/fsl_guts.h>
29 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
31 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
32 #define CLKDVDR_PXCKEN 0x80000000
33 #define CLKDVDR_PXCKINV 0x10000000
34 #define CLKDVDR_PXCKDLY 0x06000000
35 #define CLKDVDR_PXCLK_MASK 0x00FF0000
38 * p1022rdk_set_monitor_port: switch the output to a different monitor port
40 static void p1022rdk_set_monitor_port(enum fsl_diu_monitor_port port
)
42 if (port
!= FSL_DIU_PORT_DVI
) {
43 pr_err("p1022rdk: unsupported monitor port %i\n", port
);
49 * p1022rdk_set_pixel_clock: program the DIU's clock
51 * @pixclock: the wavelength, in picoseconds, of the clock
53 void p1022rdk_set_pixel_clock(unsigned int pixclock
)
55 struct device_node
*guts_np
= NULL
;
56 struct ccsr_guts __iomem
*guts
;
61 /* Map the global utilities registers. */
62 guts_np
= of_find_compatible_node(NULL
, NULL
, "fsl,p1022-guts");
64 pr_err("p1022rdk: missing global utilties device node\n");
68 guts
= of_iomap(guts_np
, 0);
71 pr_err("p1022rdk: could not map global utilties device\n");
75 /* Convert pixclock from a wavelength to a frequency */
76 temp
= 1000000000000ULL;
77 do_div(temp
, pixclock
);
81 * 'pxclk' is the ratio of the platform clock to the pixel clock.
82 * This number is programmed into the CLKDVDR register, and the valid
83 * range of values is 2-255.
85 pxclk
= DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq
);
86 pxclk
= clamp_t(u32
, pxclk
, 2, 255);
88 /* Disable the pixel clock, and set it to non-inverted and no delay */
89 clrbits32(&guts
->clkdvdr
,
90 CLKDVDR_PXCKEN
| CLKDVDR_PXCKDLY
| CLKDVDR_PXCLK_MASK
);
92 /* Enable the clock and set the pxclk */
93 setbits32(&guts
->clkdvdr
, CLKDVDR_PXCKEN
| (pxclk
<< 16));
99 * p1022rdk_valid_monitor_port: set the monitor port for sysfs
101 enum fsl_diu_monitor_port
102 p1022rdk_valid_monitor_port(enum fsl_diu_monitor_port port
)
104 return FSL_DIU_PORT_DVI
;
109 void __init
p1022_rdk_pic_init(void)
111 struct mpic
*mpic
= mpic_alloc(NULL
, 0, MPIC_BIG_ENDIAN
|
112 MPIC_SINGLE_DEST_CPU
,
113 0, 256, " OpenPIC ");
114 BUG_ON(mpic
== NULL
);
119 * Setup the architecture
121 static void __init
p1022_rdk_setup_arch(void)
124 ppc_md
.progress("p1022_rdk_setup_arch()", 0);
126 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
127 diu_ops
.set_monitor_port
= p1022rdk_set_monitor_port
;
128 diu_ops
.set_pixel_clock
= p1022rdk_set_pixel_clock
;
129 diu_ops
.valid_monitor_port
= p1022rdk_valid_monitor_port
;
134 fsl_pci_assign_primary();
138 pr_info("Freescale / iVeia P1022 RDK reference board\n");
141 machine_arch_initcall(p1022_rdk
, mpc85xx_common_publish_devices
);
143 machine_arch_initcall(p1022_rdk
, swiotlb_setup_bus_notifier
);
146 * Called very early, device-tree isn't unflattened
148 static int __init
p1022_rdk_probe(void)
150 unsigned long root
= of_get_flat_dt_root();
152 return of_flat_dt_is_compatible(root
, "fsl,p1022rdk");
155 define_machine(p1022_rdk
) {
157 .probe
= p1022_rdk_probe
,
158 .setup_arch
= p1022_rdk_setup_arch
,
159 .init_IRQ
= p1022_rdk_pic_init
,
161 .pcibios_fixup_bus
= fsl_pcibios_fixup_bus
,
163 .get_irq
= mpic_get_irq
,
164 .restart
= fsl_rstcr_restart
,
165 .calibrate_decr
= generic_calibrate_decr
,
166 .progress
= udbg_progress
,