2 * T1042 platform DIU operation
4 * Copyright 2014 Freescale Semiconductor Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
12 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
17 #include <linux/of_address.h>
19 #include <sysdev/fsl_soc.h>
21 /*DIU Pixel ClockCR offset in scfg*/
22 #define CCSR_SCFG_PIXCLKCR 0x28
24 /* DIU Pixel Clock bits of the PIXCLKCR */
25 #define PIXCLKCR_PXCKEN 0x80000000
26 #define PIXCLKCR_PXCKINV 0x40000000
27 #define PIXCLKCR_PXCKDLY 0x0000FF00
28 #define PIXCLKCR_PXCLK_MASK 0x00FF0000
30 /* Some CPLD register definitions */
31 #define CPLD_DIUCSR 0x16
32 #define CPLD_DIUCSR_DVIEN 0x80
33 #define CPLD_DIUCSR_BACKLIGHT 0x0f
35 struct device_node
*cpld_node
;
38 * t1042rdb_set_monitor_port: switch the output to a different monitor port
40 static void t1042rdb_set_monitor_port(enum fsl_diu_monitor_port port
)
42 static void __iomem
*cpld_base
;
44 cpld_base
= of_iomap(cpld_node
, 0);
46 pr_err("%s: Could not map cpld registers\n", __func__
);
51 case FSL_DIU_PORT_DVI
:
52 /* Enable the DVI(HDMI) port, disable the DFP and
55 clrbits8(cpld_base
+ CPLD_DIUCSR
, CPLD_DIUCSR_DVIEN
);
57 case FSL_DIU_PORT_LVDS
:
59 * LVDS also needs backlight enabled, otherwise the display
62 /* Enable the DFP port, disable the DVI*/
63 setbits8(cpld_base
+ CPLD_DIUCSR
, 0x01 << 8);
64 setbits8(cpld_base
+ CPLD_DIUCSR
, 0x01 << 4);
65 setbits8(cpld_base
+ CPLD_DIUCSR
, CPLD_DIUCSR_BACKLIGHT
);
68 pr_err("%s: Unsupported monitor port %i\n", __func__
, port
);
73 of_node_put(cpld_node
);
77 * t1042rdb_set_pixel_clock: program the DIU's clock
78 * @pixclock: pixel clock in ps (pico seconds)
80 static void t1042rdb_set_pixel_clock(unsigned int pixclock
)
82 struct device_node
*scfg_np
;
88 scfg_np
= of_find_compatible_node(NULL
, NULL
, "fsl,t1040-scfg");
90 pr_err("%s: Missing scfg node. Can not display video.\n",
95 scfg
= of_iomap(scfg_np
, 0);
98 pr_err("%s: Could not map device. Can not display video.\n",
103 /* Convert pixclock into frequency */
104 temp
= 1000000000000ULL;
105 do_div(temp
, pixclock
);
109 * 'pxclk' is the ratio of the platform clock to the pixel clock.
110 * This number is programmed into the PIXCLKCR register, and the valid
111 * range of values is 2-255.
113 pxclk
= DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq
);
114 pxclk
= clamp_t(u32
, pxclk
, 2, 255);
116 /* Disable the pixel clock, and set it to non-inverted and no delay */
117 clrbits32(scfg
+ CCSR_SCFG_PIXCLKCR
,
118 PIXCLKCR_PXCKEN
| PIXCLKCR_PXCKDLY
| PIXCLKCR_PXCLK_MASK
);
120 /* Enable the clock and set the pxclk */
121 setbits32(scfg
+ CCSR_SCFG_PIXCLKCR
, PIXCLKCR_PXCKEN
| (pxclk
<< 16));
127 * t1042rdb_valid_monitor_port: set the monitor port for sysfs
129 static enum fsl_diu_monitor_port
130 t1042rdb_valid_monitor_port(enum fsl_diu_monitor_port port
)
133 case FSL_DIU_PORT_DVI
:
134 case FSL_DIU_PORT_LVDS
:
137 return FSL_DIU_PORT_DVI
; /* Dual-link LVDS is not supported */
141 static int __init
t1042rdb_diu_init(void)
143 cpld_node
= of_find_compatible_node(NULL
, NULL
, "fsl,t1042rdb-cpld");
147 diu_ops
.set_monitor_port
= t1042rdb_set_monitor_port
;
148 diu_ops
.set_pixel_clock
= t1042rdb_set_pixel_clock
;
149 diu_ops
.valid_monitor_port
= t1042rdb_valid_monitor_port
;
154 early_initcall(t1042rdb_diu_init
);
156 MODULE_LICENSE("GPL");