arch/powerpc/platforms/8xx/m8xx_setup.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 1995  Linus Torvalds
   4  *  Adapted from 'alpha' version by Gary Thomas
   5  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   6  *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
   7  *  Further modified for generic 8xx by Dan.
   8  */
   9
  10 /*
  11  * bootup setup stuff..
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/init.h>
  17 #include <linux/time.h>
  18 #include <linux/rtc.h>
  19 #include <linux/fsl_devices.h>
  20
  21 #include <asm/io.h>
  22 #include <asm/8xx_immap.h>
  23 #include <asm/prom.h>
  24 #include <asm/fs_pd.h>
  25 #include <mm/mmu_decl.h>
  26
  27 #include "pic.h"
  28
  29 #include "mpc8xx.h"
  30
  31 extern int cpm_pic_init(void);
  32 extern int cpm_get_irq(void);
  33
  34 /* A place holder for time base interrupts, if they are ever enabled. */
  35 static irqreturn_t timebase_interrupt(int irq, void *dev)
  36 {
  37         printk ("timebase_interrupt()\n");
  38
  39         return IRQ_HANDLED;
  40 }
  41
  42 static struct irqaction tbint_irqaction = {
  43         .handler = timebase_interrupt,
  44         .flags = IRQF_NO_THREAD,
  45         .name = "tbint",
  46 };
  47
  48 /* per-board overridable init_internal_rtc() function. */
  49 void __init __attribute__ ((weak))
  50 init_internal_rtc(void)
  51 {
  52         sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
  53
  54         /* Disable the RTC one second and alarm interrupts. */
  55         clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
  56
  57         /* Enable the RTC */
  58         setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
  59         immr_unmap(sys_tmr);
  60 }
  61
  62 static int __init get_freq(char *name, unsigned long *val)
  63 {
  64         struct device_node *cpu;
  65         const unsigned int *fp;
  66         int found = 0;
  67
  68         /* The cpu node should have timebase and clock frequency properties */
  69         cpu = of_find_node_by_type(NULL, "cpu");
  70
  71         if (cpu) {
  72                 fp = of_get_property(cpu, name, NULL);
  73                 if (fp) {
  74                         found = 1;
  75                         *val = *fp;
  76                 }
  77
  78                 of_node_put(cpu);
  79         }
  80
  81         return found;
  82 }
  83
  84 /* The decrementer counts at the system (internal) clock frequency divided by
  85  * sixteen, or external oscillator divided by four.  We force the processor
  86  * to use system clock divided by sixteen.
  87  */
  88 void __init mpc8xx_calibrate_decr(void)
  89 {
  90         struct device_node *cpu;
  91         cark8xx_t __iomem *clk_r1;
  92         car8xx_t __iomem *clk_r2;
  93         sitk8xx_t __iomem *sys_tmr1;
  94         sit8xx_t __iomem *sys_tmr2;
  95         int irq, virq;
  96
  97         clk_r1 = immr_map(im_clkrstk);
  98
  99         /* Unlock the SCCR. */
 100         out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
 101         out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
 102         immr_unmap(clk_r1);
 103
 104         /* Force all 8xx processors to use divide by 16 processor clock. */
 105         clk_r2 = immr_map(im_clkrst);
 106         setbits32(&clk_r2->car_sccr, 0x02000000);
 107         immr_unmap(clk_r2);
 108
 109         /* Processor frequency is MHz.
 110          */
 111         ppc_proc_freq = 50000000;
 112         if (!get_freq("clock-frequency", &ppc_proc_freq))
 113                 printk(KERN_ERR "WARNING: Estimating processor frequency "
 114                                 "(not found)\n");
 115
 116         ppc_tb_freq = ppc_proc_freq / 16;
 117         printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
 118
 119         /* Perform some more timer/timebase initialization.  This used
 120          * to be done elsewhere, but other changes caused it to get
 121          * called more than once....that is a bad thing.
 122          *
 123          * First, unlock all of the registers we are going to modify.
 124          * To protect them from corruption during power down, registers
 125          * that are maintained by keep alive power are "locked".  To
 126          * modify these registers we have to write the key value to
 127          * the key location associated with the register.
 128          * Some boards power up with these unlocked, while others
 129          * are locked.  Writing anything (including the unlock code?)
 130          * to the unlocked registers will lock them again.  So, here
 131          * we guarantee the registers are locked, then we unlock them
 132          * for our use.
 133          */
 134         sys_tmr1 = immr_map(im_sitk);
 135         out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
 136         out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
 137         out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
 138         out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
 139         out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
 140         out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
 141         immr_unmap(sys_tmr1);
 142
 143         init_internal_rtc();
 144
 145         /* Enabling the decrementer also enables the timebase interrupts
 146          * (or from the other point of view, to get decrementer interrupts
 147          * we have to enable the timebase).  The decrementer interrupt
 148          * is wired into the vector table, nothing to do here for that.
 149          */
 150         cpu = of_find_node_by_type(NULL, "cpu");
 151         virq= irq_of_parse_and_map(cpu, 0);
 152         irq = virq_to_hw(virq);
 153
 154         sys_tmr2 = immr_map(im_sit);
 155         out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
 156                                         (TBSCR_TBF | TBSCR_TBE));
 157         immr_unmap(sys_tmr2);
 158
 159         if (setup_irq(virq, &tbint_irqaction))
 160                 panic("Could not allocate timer IRQ!");
 161 }
 162
 163 /* The RTC on the MPC8xx is an internal register.
 164  * We want to protect this during power down, so we need to unlock,
 165  * modify, and re-lock.
 166  */
 167
 168 int mpc8xx_set_rtc_time(struct rtc_time *tm)
 169 {
 170         sitk8xx_t __iomem *sys_tmr1;
 171         sit8xx_t __iomem *sys_tmr2;
 172         int time;
 173
 174         sys_tmr1 = immr_map(im_sitk);
 175         sys_tmr2 = immr_map(im_sit);
 176         time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
 177                       tm->tm_hour, tm->tm_min, tm->tm_sec);
 178
 179         out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
 180         out_be32(&sys_tmr2->sit_rtc, time);
 181         out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);
 182
 183         immr_unmap(sys_tmr2);
 184         immr_unmap(sys_tmr1);
 185         return 0;
 186 }
 187
 188 void mpc8xx_get_rtc_time(struct rtc_time *tm)
 189 {
 190         unsigned long data;
 191         sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
 192
 193         /* Get time from the RTC. */
 194         data = in_be32(&sys_tmr->sit_rtc);
 195         to_tm(data, tm);
 196         tm->tm_year -= 1900;
 197         tm->tm_mon -= 1;
 198         immr_unmap(sys_tmr);
 199         return;
 200 }
 201
 202 void __noreturn mpc8xx_restart(char *cmd)
 203 {
 204         car8xx_t __iomem *clk_r = immr_map(im_clkrst);
 205
 206
 207         local_irq_disable();
 208
 209         setbits32(&clk_r->car_plprcr, 0x00000080);
 210         /* Clear the ME bit in MSR to cause checkstop on machine check
 211         */
 212         mtmsr(mfmsr() & ~0x1000);
 213
 214         in_8(&clk_r->res[0]);
 215         panic("Restart failed\n");
 216 }
 217
 218 static void cpm_cascade(struct irq_desc *desc)
 219 {
 220         struct irq_chip *chip = irq_desc_get_chip(desc);
 221         int cascade_irq = cpm_get_irq();
 222
 223         if (cascade_irq >= 0)
 224                 generic_handle_irq(cascade_irq);
 225
 226         chip->irq_eoi(&desc->irq_data);
 227 }
 228
 229 /* Initialize the internal interrupt controllers.  The number of
 230  * interrupts supported can vary with the processor type, and the
 231  * 82xx family can have up to 64.
 232  * External interrupts can be either edge or level triggered, and
 233  * need to be initialized by the appropriate driver.
 234  */
 235 void __init mpc8xx_pics_init(void)
 236 {
 237         int irq;
 238
 239         if (mpc8xx_pic_init()) {
 240                 printk(KERN_ERR "Failed interrupt 8xx controller  initialization\n");
 241                 return;
 242         }
 243
 244         irq = cpm_pic_init();
 245         if (irq)
 246                 irq_set_chained_handler(irq, cpm_cascade);
 247 }