1 # SPDX-License-Identifier: GPL-2.0
2 menu "Platform support"
4 source "arch/powerpc/platforms/powernv/Kconfig"
5 source "arch/powerpc/platforms/pseries/Kconfig"
6 source "arch/powerpc/platforms/chrp/Kconfig"
7 source "arch/powerpc/platforms/512x/Kconfig"
8 source "arch/powerpc/platforms/52xx/Kconfig"
9 source "arch/powerpc/platforms/powermac/Kconfig"
10 source "arch/powerpc/platforms/maple/Kconfig"
11 source "arch/powerpc/platforms/pasemi/Kconfig"
12 source "arch/powerpc/platforms/ps3/Kconfig"
13 source "arch/powerpc/platforms/cell/Kconfig"
14 source "arch/powerpc/platforms/8xx/Kconfig"
15 source "arch/powerpc/platforms/82xx/Kconfig"
16 source "arch/powerpc/platforms/83xx/Kconfig"
17 source "arch/powerpc/platforms/85xx/Kconfig"
18 source "arch/powerpc/platforms/86xx/Kconfig"
19 source "arch/powerpc/platforms/embedded6xx/Kconfig"
20 source "arch/powerpc/platforms/44x/Kconfig"
21 source "arch/powerpc/platforms/40x/Kconfig"
22 source "arch/powerpc/platforms/amigaone/Kconfig"
25 bool "KVM Guest support"
28 This option enables various optimizations for running under the KVM
29 hypervisor. Overhead for the kernel when not running inside KVM should
32 In case of doubt, say Y
35 bool "ePAPR para-virtualization support"
37 Enables ePAPR para-virtualization support for guests.
39 In case of doubt, say Y
43 depends on PPC_BOOK3S_32 || PPC64
45 Support for running natively on the hardware, i.e. without
46 a hypervisor. This option is not user-selectable but should
47 be selected by all platforms that need it.
49 config PPC_OF_BOOT_TRAMPOLINE
50 bool "Support booting from Open Firmware or yaboot"
51 depends on PPC_BOOK3S_32 || PPC64
54 Support from booting from Open Firmware or yaboot using an
55 Open Firmware client interface. This enables the kernel to
56 communicate with open firmware to retrieve system information
57 such as the device tree.
59 In case of doubt, say Y
61 config PPC_DT_CPU_FTRS
62 bool "Device-tree based CPU feature discovery & setup"
63 depends on PPC_BOOK3S_64
66 This enables code to use a new device tree binding for describing CPU
67 compatibility and features. Saying Y here will attempt to use the new
68 binding if the firmware provides it. Currently only the skiboot
69 firmware provides this binding.
70 If you're not sure say Y.
72 config UDBG_RTAS_CONSOLE
73 bool "RTAS based debug console"
76 config PPC_SMP_MUXED_IPI
79 Select this option if your platform supports SMP and your
80 interrupt controller provides less than 4 interrupts to each
81 cpu. This will enable the generic code to multiplex the 4
82 messages on to one ipi.
91 bool "MPIC Global Timer"
92 depends on MPIC && FSL_SOC
94 The MPIC global timer is a hardware timer inside the
95 Freescale PIC complying with OpenPIC standard. When the
96 specified interval times out, the hardware timer generates
97 an interrupt. The driver currently is only tested on fsl
98 chip, but it can potentially support other global timers
99 complying with the OpenPIC standard.
101 config FSL_MPIC_TIMER_WAKEUP
102 tristate "Freescale MPIC global timer wakeup driver"
103 depends on FSL_SOC && MPIC_TIMER && PM
105 The driver provides a way to wake up the system by MPIC
107 e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup"
109 config PPC_EPAPR_HV_PIC
111 select EPAPR_PARAVIRT
117 bool "MPIC message register support"
120 Enables support for the MPIC message registers. These
121 registers are used for inter-processor communication.
133 config RTAS_ERROR_LOGGING
137 config PPC_RTAS_DAEMON
142 bool "Proc interface to RTAS"
143 depends on PPC_RTAS && PROC_FS
147 tristate "Firmware flash interface"
148 depends on PPC64 && RTAS_PROC
153 config MPIC_U3_HT_IRQS
156 config MPIC_BROKEN_REGREAD
160 This option enables a MPIC driver workaround for some chips
161 that have a bug that causes some interrupt source information
162 to not read back properly. It is safe to use on other chips as
163 well, but enabling it uses about 8KB of memory to keep copies
164 of the register contents in software.
168 depends on (PPC_POWERNV || PPC_PSERIES) && PCI
180 config PPC_INDIRECT_PIO
184 config PPC_INDIRECT_MMIO
187 config PPC_IO_WORKAROUNDS
190 source "drivers/cpufreq/Kconfig"
192 menu "CPUIdle driver"
194 source "drivers/cpuidle/Kconfig"
198 config PPC601_SYNC_FIX
199 bool "Workarounds for PPC601 bugs"
200 depends on PPC_BOOK3S_32 && PPC_PMAC
202 Some versions of the PPC601 (the first PowerPC chip) have bugs which
203 mean that extra synchronization instructions are required near
204 certain instructions, typically those that make major changes to the
205 CPU state. These extra instructions reduce performance slightly.
206 If you say N here, these extra instructions will not be included,
207 resulting in a kernel which will run faster but may not run at all
208 on some systems with the PPC601 chip.
210 If in doubt, say Y here.
213 bool "On-chip CPU temperature sensor support"
214 depends on PPC_BOOK3S_32
216 G3 and G4 processors have an on-chip temperature sensor called the
217 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
218 temperature within 2-4 degrees Celsius. This option shows the current
219 on-die temperature in /proc/cpuinfo if the cpu supports it.
221 Unfortunately, on some chip revisions, this sensor is very inaccurate
222 and in many cases, does not work at all, so don't assume the cpu
223 temp is actually what /proc/cpuinfo says it is.
226 bool "Interrupt driven TAU driver (DANGEROUS)"
229 The TAU supports an interrupt driven mode which causes an interrupt
230 whenever the temperature goes out of range. This is the fastest way
231 to get notified the temp has exceeded a range. With this option off,
232 a timer is used to re-check the temperature periodically.
234 However, on some cpus it appears that the TAU interrupt hardware
235 is buggy and can cause a situation which would lead unexplained hard
238 Unless you are extending the TAU driver, or enjoy kernel/hardware
239 debugging, leave this option off.
242 bool "Average high and low temp"
245 The TAU hardware can compare the temperature to an upper and lower
246 bound. The default behavior is to show both the upper and lower
247 bound in /proc/cpuinfo. If the range is large, the temperature is
248 either changing a lot, or the TAU hardware is broken (likely on some
249 G4's). If the range is small (around 4 degrees), the temperature is
250 relatively stable. If you say Y here, a single temperature value,
251 halfway between the upper and lower bounds, will be reported in
254 If in doubt, say N here.
257 bool "QE GPIO support"
258 depends on QUICC_ENGINE
261 Say Y here if you're going to use hardware that connects to the
265 bool "Enable support for the CPM2 (Communications Processor Module)"
266 depends on (FSL_SOC_BOOKE && PPC32) || 8260
271 The CPM2 (Communications Processor Module) is a coprocessor on
272 embedded CPUs made by Freescale. Selecting this option means that
273 you wish to build a kernel for a machine with a CPM2 coprocessor
274 on it (826x, 827x, 8560).
278 select GENERIC_ISA_DMA
280 Supports for the ULI1575 PCIe south bridge that exists on some
281 Freescale reference boards. The boards all use the ULI in pretty
286 select GENERIC_ALLOCATOR
291 Uses information from the OF or flattened device tree to instantiate
292 platform devices for direct mapped RTC chips like the DS1742 or DS1743.
295 bool "Use the platform RTC operations from user space"
297 select RTC_DRV_GENERIC
299 This option provides backwards compatibility with the old gen_rtc.ko
300 module that was traditionally used for old PowerPC machines.
301 Platforms should migrate to enabling the RTC_DRV_GENERIC by hand
302 replacing their get_rtc_time/set_rtc_time callbacks with
303 a proper RTC device driver.
306 bool "Support for simple, memory-mapped GPIO controllers"
310 Say Y here to support simple, memory-mapped GPIO controllers.
311 These are usually BCSRs used to control board's switches, LEDs,
312 chip-selects, Ethernet/USB PHY's power and various other small
313 on-board peripherals.
315 config MCU_MPC8349EMITX
316 bool "MPC8349E-mITX MCU driver"
317 depends on I2C=y && PPC_83xx
320 Say Y here to enable soft power-off functionality on the Freescale
321 boards with the MPC8349E-mITX-compatible MCU chips. This driver will
322 also register MCU GPIOs with the generic GPIO API, so you'll able
323 to use MCU pins as GPIOs.
326 bool "Xilinx PCI host bridge support"
327 depends on PCI && XILINX_VIRTEX