arch/powerpc/platforms/cell/axon_msi.c

   1 /*
   2  * Copyright 2007, Michael Ellerman, IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10
  11 #include <linux/interrupt.h>
  12 #include <linux/irq.h>
  13 #include <linux/kernel.h>
  14 #include <linux/pci.h>
  15 #include <linux/msi.h>
  16 #include <linux/of_platform.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/slab.h>
  19
  20 #include <asm/dcr.h>
  21 #include <asm/machdep.h>
  22 #include <asm/prom.h>
  23
  24
  25 /*
  26  * MSIC registers, specified as offsets from dcr_base
  27  */
  28 #define MSIC_CTRL_REG   0x0
  29
  30 /* Base Address registers specify FIFO location in BE memory */
  31 #define MSIC_BASE_ADDR_HI_REG   0x3
  32 #define MSIC_BASE_ADDR_LO_REG   0x4
  33
  34 /* Hold the read/write offsets into the FIFO */
  35 #define MSIC_READ_OFFSET_REG    0x5
  36 #define MSIC_WRITE_OFFSET_REG   0x6
  37
  38
  39 /* MSIC control register flags */
  40 #define MSIC_CTRL_ENABLE                0x0001
  41 #define MSIC_CTRL_FIFO_FULL_ENABLE      0x0002
  42 #define MSIC_CTRL_IRQ_ENABLE            0x0008
  43 #define MSIC_CTRL_FULL_STOP_ENABLE      0x0010
  44
  45 /*
  46  * The MSIC can be configured to use a FIFO of 32KB, 64KB, 128KB or 256KB.
  47  * Currently we're using a 64KB FIFO size.
  48  */
  49 #define MSIC_FIFO_SIZE_SHIFT    16
  50 #define MSIC_FIFO_SIZE_BYTES    (1 << MSIC_FIFO_SIZE_SHIFT)
  51
  52 /*
  53  * To configure the FIFO size as (1 << n) bytes, we write (n - 15) into bits
  54  * 8-9 of the MSIC control reg.
  55  */
  56 #define MSIC_CTRL_FIFO_SIZE     (((MSIC_FIFO_SIZE_SHIFT - 15) << 8) & 0x300)
  57
  58 /*
  59  * We need to mask the read/write offsets to make sure they stay within
  60  * the bounds of the FIFO. Also they should always be 16-byte aligned.
  61  */
  62 #define MSIC_FIFO_SIZE_MASK     ((MSIC_FIFO_SIZE_BYTES - 1) & ~0xFu)
  63
  64 /* Each entry in the FIFO is 16 bytes, the first 4 bytes hold the irq # */
  65 #define MSIC_FIFO_ENTRY_SIZE    0x10
  66
  67
  68 struct axon_msic {
  69         struct irq_host *irq_host;
  70         __le32 *fifo_virt;
  71         dma_addr_t fifo_phys;
  72         dcr_host_t dcr_host;
  73         u32 read_offset;
  74 #ifdef DEBUG
  75         u32 __iomem *trigger;
  76 #endif
  77 };
  78
  79 #ifdef DEBUG
  80 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
  81 #else
  82 static inline void axon_msi_debug_setup(struct device_node *dn,
  83                                         struct axon_msic *msic) { }
  84 #endif
  85
  86
  87 static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
  88 {
  89         pr_devel("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n);
  90
  91         dcr_write(msic->dcr_host, dcr_n, val);
  92 }
  93
  94 static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
  95 {
  96         struct axon_msic *msic = get_irq_data(irq);
  97         u32 write_offset, msi;
  98         int idx;
  99         int retry = 0;
 100
 101         write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);
 102         pr_devel("axon_msi: original write_offset 0x%x\n", write_offset);
 103
 104         /* write_offset doesn't wrap properly, so we have to mask it */
 105         write_offset &= MSIC_FIFO_SIZE_MASK;
 106
 107         while (msic->read_offset != write_offset && retry < 100) {
 108                 idx  = msic->read_offset / sizeof(__le32);
 109                 msi  = le32_to_cpu(msic->fifo_virt[idx]);
 110                 msi &= 0xFFFF;
 111
 112                 pr_devel("axon_msi: woff %x roff %x msi %x\n",
 113                           write_offset, msic->read_offset, msi);
 114
 115                 if (msi < NR_IRQS && irq_map[msi].host == msic->irq_host) {
 116                         generic_handle_irq(msi);
 117                         msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
 118                 } else {
 119                         /*
 120                          * Reading the MSIC_WRITE_OFFSET_REG does not
 121                          * reliably flush the outstanding DMA to the
 122                          * FIFO buffer. Here we were reading stale
 123                          * data, so we need to retry.
 124                          */
 125                         udelay(1);
 126                         retry++;
 127                         pr_devel("axon_msi: invalid irq 0x%x!\n", msi);
 128                         continue;
 129                 }
 130
 131                 if (retry) {
 132                         pr_devel("axon_msi: late irq 0x%x, retry %d\n",
 133                                  msi, retry);
 134                         retry = 0;
 135                 }
 136
 137                 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
 138                 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
 139         }
 140
 141         if (retry) {
 142                 printk(KERN_WARNING "axon_msi: irq timed out\n");
 143
 144                 msic->read_offset += MSIC_FIFO_ENTRY_SIZE;
 145                 msic->read_offset &= MSIC_FIFO_SIZE_MASK;
 146         }
 147
 148         desc->chip->eoi(irq);
 149 }
 150
 151 static struct axon_msic *find_msi_translator(struct pci_dev *dev)
 152 {
 153         struct irq_host *irq_host;
 154         struct device_node *dn, *tmp;
 155         const phandle *ph;
 156         struct axon_msic *msic = NULL;
 157
 158         dn = of_node_get(pci_device_to_OF_node(dev));
 159         if (!dn) {
 160                 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
 161                 return NULL;
 162         }
 163
 164         for (; dn; dn = of_get_next_parent(dn)) {
 165                 ph = of_get_property(dn, "msi-translator", NULL);
 166                 if (ph)
 167                         break;
 168         }
 169
 170         if (!ph) {
 171                 dev_dbg(&dev->dev,
 172                         "axon_msi: no msi-translator property found\n");
 173                 goto out_error;
 174         }
 175
 176         tmp = dn;
 177         dn = of_find_node_by_phandle(*ph);
 178         of_node_put(tmp);
 179         if (!dn) {
 180                 dev_dbg(&dev->dev,
 181                         "axon_msi: msi-translator doesn't point to a node\n");
 182                 goto out_error;
 183         }
 184
 185         irq_host = irq_find_host(dn);
 186         if (!irq_host) {
 187                 dev_dbg(&dev->dev, "axon_msi: no irq_host found for node %s\n",
 188                         dn->full_name);
 189                 goto out_error;
 190         }
 191
 192         msic = irq_host->host_data;
 193
 194 out_error:
 195         of_node_put(dn);
 196
 197         return msic;
 198 }
 199
 200 static int axon_msi_check_device(struct pci_dev *dev, int nvec, int type)
 201 {
 202         if (!find_msi_translator(dev))
 203                 return -ENODEV;
 204
 205         return 0;
 206 }
 207
 208 static int setup_msi_msg_address(struct pci_dev *dev, struct msi_msg *msg)
 209 {
 210         struct device_node *dn;
 211         struct msi_desc *entry;
 212         int len;
 213         const u32 *prop;
 214
 215         dn = of_node_get(pci_device_to_OF_node(dev));
 216         if (!dn) {
 217                 dev_dbg(&dev->dev, "axon_msi: no pci_dn found\n");
 218                 return -ENODEV;
 219         }
 220
 221         entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
 222
 223         for (; dn; dn = of_get_next_parent(dn)) {
 224                 if (entry->msi_attrib.is_64) {
 225                         prop = of_get_property(dn, "msi-address-64", &len);
 226                         if (prop)
 227                                 break;
 228                 }
 229
 230                 prop = of_get_property(dn, "msi-address-32", &len);
 231                 if (prop)
 232                         break;
 233         }
 234
 235         if (!prop) {
 236                 dev_dbg(&dev->dev,
 237                         "axon_msi: no msi-address-(32|64) properties found\n");
 238                 return -ENOENT;
 239         }
 240
 241         switch (len) {
 242         case 8:
 243                 msg->address_hi = prop[0];
 244                 msg->address_lo = prop[1];
 245                 break;
 246         case 4:
 247                 msg->address_hi = 0;
 248                 msg->address_lo = prop[0];
 249                 break;
 250         default:
 251                 dev_dbg(&dev->dev,
 252                         "axon_msi: malformed msi-address-(32|64) property\n");
 253                 of_node_put(dn);
 254                 return -EINVAL;
 255         }
 256
 257         of_node_put(dn);
 258
 259         return 0;
 260 }
 261
 262 static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
 263 {
 264         unsigned int virq, rc;
 265         struct msi_desc *entry;
 266         struct msi_msg msg;
 267         struct axon_msic *msic;
 268
 269         msic = find_msi_translator(dev);
 270         if (!msic)
 271                 return -ENODEV;
 272
 273         rc = setup_msi_msg_address(dev, &msg);
 274         if (rc)
 275                 return rc;
 276
 277         /* We rely on being able to stash a virq in a u16 */
 278         BUILD_BUG_ON(NR_IRQS > 65536);
 279
 280         list_for_each_entry(entry, &dev->msi_list, list) {
 281                 virq = irq_create_direct_mapping(msic->irq_host);
 282                 if (virq == NO_IRQ) {
 283                         dev_warn(&dev->dev,
 284                                  "axon_msi: virq allocation failed!\n");
 285                         return -1;
 286                 }
 287                 dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
 288
 289                 set_irq_msi(virq, entry);
 290                 msg.data = virq;
 291                 write_msi_msg(virq, &msg);
 292         }
 293
 294         return 0;
 295 }
 296
 297 static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
 298 {
 299         struct msi_desc *entry;
 300
 301         dev_dbg(&dev->dev, "axon_msi: tearing down msi irqs\n");
 302
 303         list_for_each_entry(entry, &dev->msi_list, list) {
 304                 if (entry->irq == NO_IRQ)
 305                         continue;
 306
 307                 set_irq_msi(entry->irq, NULL);
 308                 irq_dispose_mapping(entry->irq);
 309         }
 310 }
 311
 312 static struct irq_chip msic_irq_chip = {
 313         .mask           = mask_msi_irq,
 314         .unmask         = unmask_msi_irq,
 315         .shutdown       = unmask_msi_irq,
 316         .name           = "AXON-MSI",
 317 };
 318
 319 static int msic_host_map(struct irq_host *h, unsigned int virq,
 320                          irq_hw_number_t hw)
 321 {
 322         set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
 323
 324         return 0;
 325 }
 326
 327 static struct irq_host_ops msic_host_ops = {
 328         .map    = msic_host_map,
 329 };
 330
 331 static int axon_msi_shutdown(struct of_device *device)
 332 {
 333         struct axon_msic *msic = dev_get_drvdata(&device->dev);
 334         u32 tmp;
 335
 336         pr_devel("axon_msi: disabling %s\n",
 337                   msic->irq_host->of_node->full_name);
 338         tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);
 339         tmp &= ~MSIC_CTRL_ENABLE & ~MSIC_CTRL_IRQ_ENABLE;
 340         msic_dcr_write(msic, MSIC_CTRL_REG, tmp);
 341
 342         return 0;
 343 }
 344
 345 static int axon_msi_probe(struct of_device *device,
 346                           const struct of_device_id *device_id)
 347 {
 348         struct device_node *dn = device->dev.of_node;
 349         struct axon_msic *msic;
 350         unsigned int virq;
 351         int dcr_base, dcr_len;
 352
 353         pr_devel("axon_msi: setting up dn %s\n", dn->full_name);
 354
 355         msic = kzalloc(sizeof(struct axon_msic), GFP_KERNEL);
 356         if (!msic) {
 357                 printk(KERN_ERR "axon_msi: couldn't allocate msic for %s\n",
 358                        dn->full_name);
 359                 goto out;
 360         }
 361
 362         dcr_base = dcr_resource_start(dn, 0);
 363         dcr_len = dcr_resource_len(dn, 0);
 364
 365         if (dcr_base == 0 || dcr_len == 0) {
 366                 printk(KERN_ERR
 367                        "axon_msi: couldn't parse dcr properties on %s\n",
 368                         dn->full_name);
 369                 goto out_free_msic;
 370         }
 371
 372         msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);
 373         if (!DCR_MAP_OK(msic->dcr_host)) {
 374                 printk(KERN_ERR "axon_msi: dcr_map failed for %s\n",
 375                        dn->full_name);
 376                 goto out_free_msic;
 377         }
 378
 379         msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,
 380                                              &msic->fifo_phys, GFP_KERNEL);
 381         if (!msic->fifo_virt) {
 382                 printk(KERN_ERR "axon_msi: couldn't allocate fifo for %s\n",
 383                        dn->full_name);
 384                 goto out_free_msic;
 385         }
 386
 387         virq = irq_of_parse_and_map(dn, 0);
 388         if (virq == NO_IRQ) {
 389                 printk(KERN_ERR "axon_msi: irq parse and map failed for %s\n",
 390                        dn->full_name);
 391                 goto out_free_fifo;
 392         }
 393         memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
 394
 395         msic->irq_host = irq_alloc_host(dn, IRQ_HOST_MAP_NOMAP,
 396                                         NR_IRQS, &msic_host_ops, 0);
 397         if (!msic->irq_host) {
 398                 printk(KERN_ERR "axon_msi: couldn't allocate irq_host for %s\n",
 399                        dn->full_name);
 400                 goto out_free_fifo;
 401         }
 402
 403         msic->irq_host->host_data = msic;
 404
 405         set_irq_data(virq, msic);
 406         set_irq_chained_handler(virq, axon_msi_cascade);
 407         pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
 408
 409         /* Enable the MSIC hardware */
 410         msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);
 411         msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,
 412                                   msic->fifo_phys & 0xFFFFFFFF);
 413         msic_dcr_write(msic, MSIC_CTRL_REG,
 414                         MSIC_CTRL_IRQ_ENABLE | MSIC_CTRL_ENABLE |
 415                         MSIC_CTRL_FIFO_SIZE);
 416
 417         msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)
 418                                 & MSIC_FIFO_SIZE_MASK;
 419
 420         dev_set_drvdata(&device->dev, msic);
 421
 422         ppc_md.setup_msi_irqs = axon_msi_setup_msi_irqs;
 423         ppc_md.teardown_msi_irqs = axon_msi_teardown_msi_irqs;
 424         ppc_md.msi_check_device = axon_msi_check_device;
 425
 426         axon_msi_debug_setup(dn, msic);
 427
 428         printk(KERN_DEBUG "axon_msi: setup MSIC on %s\n", dn->full_name);
 429
 430         return 0;
 431
 432 out_free_fifo:
 433         dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,
 434                           msic->fifo_phys);
 435 out_free_msic:
 436         kfree(msic);
 437 out:
 438
 439         return -1;
 440 }
 441
 442 static const struct of_device_id axon_msi_device_id[] = {
 443         {
 444                 .compatible     = "ibm,axon-msic"
 445         },
 446         {}
 447 };
 448
 449 static struct of_platform_driver axon_msi_driver = {
 450         .probe          = axon_msi_probe,
 451         .shutdown       = axon_msi_shutdown,
 452         .driver = {
 453                 .name = "axon-msi",
 454                 .owner = THIS_MODULE,
 455                 .of_match_table = axon_msi_device_id,
 456         },
 457 };
 458
 459 static int __init axon_msi_init(void)
 460 {
 461         return of_register_platform_driver(&axon_msi_driver);
 462 }
 463 subsys_initcall(axon_msi_init);
 464
 465
 466 #ifdef DEBUG
 467 static int msic_set(void *data, u64 val)
 468 {
 469         struct axon_msic *msic = data;
 470         out_le32(msic->trigger, val);
 471         return 0;
 472 }
 473
 474 static int msic_get(void *data, u64 *val)
 475 {
 476         *val = 0;
 477         return 0;
 478 }
 479
 480 DEFINE_SIMPLE_ATTRIBUTE(fops_msic, msic_get, msic_set, "%llu\n");
 481
 482 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
 483 {
 484         char name[8];
 485         u64 addr;
 486
 487         addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
 488         if (addr == OF_BAD_ADDR) {
 489                 pr_devel("axon_msi: couldn't translate reg property\n");
 490                 return;
 491         }
 492
 493         msic->trigger = ioremap(addr, 0x4);
 494         if (!msic->trigger) {
 495                 pr_devel("axon_msi: ioremap failed\n");
 496                 return;
 497         }
 498
 499         snprintf(name, sizeof(name), "msic_%d", of_node_to_nid(dn));
 500
 501         if (!debugfs_create_file(name, 0600, powerpc_debugfs_root,
 502                                  msic, &fops_msic)) {
 503                 pr_devel("axon_msi: debugfs_create_file failed!\n");
 504                 return;
 505         }
 506 }
 507 #endif /* DEBUG */