2 * Support for SCC external PCI
4 * (C) Copyright 2004-2007 TOSHIBA CORPORATION
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 #include <linux/kernel.h>
24 #include <linux/threads.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/pci_regs.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/ppc-pci.h>
35 #include "celleb_scc.h"
36 #include "celleb_pci.h"
38 #define MAX_PCI_DEVICES 32
39 #define MAX_PCI_FUNCTIONS 8
41 #define iob() __asm__ __volatile__("eieio; sync":::"memory")
43 static inline PCI_IO_ADDR
celleb_epci_get_epci_base(
44 struct pci_controller
*hose
)
48 * Celleb epci uses cfg_addr as a base address for
49 * epci control registers.
52 return hose
->cfg_addr
;
55 static inline PCI_IO_ADDR
celleb_epci_get_epci_cfg(
56 struct pci_controller
*hose
)
60 * Celleb epci uses cfg_data as a base address for
61 * configuration area for epci devices.
64 return hose
->cfg_data
;
67 static inline void clear_and_disable_master_abort_interrupt(
68 struct pci_controller
*hose
)
70 PCI_IO_ADDR epci_base
;
72 epci_base
= celleb_epci_get_epci_base(hose
);
73 reg
= epci_base
+ PCI_COMMAND
;
74 out_be32(reg
, in_be32(reg
) | (PCI_STATUS_REC_MASTER_ABORT
<< 16));
77 static int celleb_epci_check_abort(struct pci_controller
*hose
,
81 PCI_IO_ADDR epci_base
;
85 epci_base
= celleb_epci_get_epci_base(hose
);
87 reg
= epci_base
+ PCI_COMMAND
;
90 if (val
& (PCI_STATUS_REC_MASTER_ABORT
<< 16)) {
92 (val
& 0xffff) | (PCI_STATUS_REC_MASTER_ABORT
<< 16));
94 /* clear PCI Controller error, FRE, PMFE */
95 reg
= epci_base
+ SCC_EPCI_STATUS
;
96 out_be32(reg
, SCC_EPCI_INT_PAI
);
98 reg
= epci_base
+ SCC_EPCI_VCSR
;
99 val
= in_be32(reg
) & 0xffff;
100 val
|= SCC_EPCI_VCSR_FRE
;
103 reg
= epci_base
+ SCC_EPCI_VISTAT
;
104 out_be32(reg
, SCC_EPCI_VISTAT_PMFE
);
105 return PCIBIOS_DEVICE_NOT_FOUND
;
108 return PCIBIOS_SUCCESSFUL
;
111 static PCI_IO_ADDR
celleb_epci_make_config_addr(struct pci_bus
*bus
,
112 struct pci_controller
*hose
, unsigned int devfn
, int where
)
116 if (bus
!= hose
->bus
)
117 addr
= celleb_epci_get_epci_cfg(hose
) +
118 (((bus
->number
& 0xff) << 16)
119 | ((devfn
& 0xff) << 8)
123 addr
= celleb_epci_get_epci_cfg(hose
) +
124 (((devfn
& 0xff) << 8) | (where
& 0xff));
126 pr_debug("EPCI: config_addr = 0x%p\n", addr
);
131 static int celleb_epci_read_config(struct pci_bus
*bus
,
132 unsigned int devfn
, int where
, int size
, u32
*val
)
134 PCI_IO_ADDR epci_base
;
136 struct pci_controller
*hose
= pci_bus_to_host(bus
);
138 /* allignment check */
139 BUG_ON(where
% size
);
141 if (!celleb_epci_get_epci_cfg(hose
))
142 return PCIBIOS_DEVICE_NOT_FOUND
;
144 if (bus
->number
== hose
->first_busno
&& devfn
== 0) {
145 /* EPCI controller self */
147 epci_base
= celleb_epci_get_epci_base(hose
);
148 addr
= epci_base
+ where
;
155 *val
= in_be16(addr
);
158 *val
= in_be32(addr
);
161 return PCIBIOS_DEVICE_NOT_FOUND
;
166 clear_and_disable_master_abort_interrupt(hose
);
167 addr
= celleb_epci_make_config_addr(bus
, hose
, devfn
, where
);
174 *val
= in_le16(addr
);
177 *val
= in_le32(addr
);
180 return PCIBIOS_DEVICE_NOT_FOUND
;
185 "addr=0x%p, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
186 addr
, devfn
, where
, size
, *val
);
188 return celleb_epci_check_abort(hose
, NULL
);
191 static int celleb_epci_write_config(struct pci_bus
*bus
,
192 unsigned int devfn
, int where
, int size
, u32 val
)
194 PCI_IO_ADDR epci_base
;
196 struct pci_controller
*hose
= pci_bus_to_host(bus
);
198 /* allignment check */
199 BUG_ON(where
% size
);
201 if (!celleb_epci_get_epci_cfg(hose
))
202 return PCIBIOS_DEVICE_NOT_FOUND
;
204 if (bus
->number
== hose
->first_busno
&& devfn
== 0) {
205 /* EPCI controller self */
207 epci_base
= celleb_epci_get_epci_base(hose
);
208 addr
= epci_base
+ where
;
221 return PCIBIOS_DEVICE_NOT_FOUND
;
226 clear_and_disable_master_abort_interrupt(hose
);
227 addr
= celleb_epci_make_config_addr(bus
, hose
, devfn
, where
);
240 return PCIBIOS_DEVICE_NOT_FOUND
;
244 return celleb_epci_check_abort(hose
, addr
);
247 struct pci_ops celleb_epci_ops
= {
248 .read
= celleb_epci_read_config
,
249 .write
= celleb_epci_write_config
,
252 /* to be moved in FW */
253 static int __init
celleb_epci_init(struct pci_controller
*hose
)
257 PCI_IO_ADDR epci_base
;
260 epci_base
= celleb_epci_get_epci_base(hose
);
262 /* PCI core reset(Internal bus and PCI clock) */
263 reg
= epci_base
+ SCC_EPCI_CKCTRL
;
265 if (val
== 0x00030101)
268 val
&= ~(SCC_EPCI_CKCTRL_CRST0
| SCC_EPCI_CKCTRL_CRST1
);
271 /* set PCI core clock */
273 val
|= (SCC_EPCI_CKCTRL_OCLKEN
| SCC_EPCI_CKCTRL_LCLKEN
);
276 /* release PCI core reset (internal bus) */
278 val
|= SCC_EPCI_CKCTRL_CRST0
;
281 /* set PCI clock select */
282 reg
= epci_base
+ SCC_EPCI_CLKRST
;
284 val
&= ~SCC_EPCI_CLKRST_CKS_MASK
;
285 val
|= SCC_EPCI_CLKRST_CKS_2
;
289 reg
= epci_base
+ SCC_EPCI_ABTSET
;
290 out_be32(reg
, 0x0f1f001f); /* temporary value */
293 reg
= epci_base
+ SCC_EPCI_CLKRST
;
295 val
|= SCC_EPCI_CLKRST_BC
;
298 /* PCI clock enable */
300 val
|= SCC_EPCI_CLKRST_PCKEN
;
303 /* release PCI core reset (all) */
304 reg
= epci_base
+ SCC_EPCI_CKCTRL
;
306 val
|= (SCC_EPCI_CKCTRL_CRST0
| SCC_EPCI_CKCTRL_CRST1
);
309 /* set base translation registers. (already set by Beat) */
311 /* set base address masks. (already set by Beat) */
314 /* release interrupt masks and clear all interrupts */
315 reg
= epci_base
+ SCC_EPCI_INTSET
;
316 out_be32(reg
, 0x013f011f); /* all interrupts enable */
317 reg
= epci_base
+ SCC_EPCI_VIENAB
;
318 val
= SCC_EPCI_VIENAB_PMPEE
| SCC_EPCI_VIENAB_PMFEE
;
320 reg
= epci_base
+ SCC_EPCI_STATUS
;
321 out_be32(reg
, 0xffffffff);
322 reg
= epci_base
+ SCC_EPCI_VISTAT
;
323 out_be32(reg
, 0xffffffff);
325 /* disable PCI->IB address translation */
326 reg
= epci_base
+ SCC_EPCI_VCSR
;
328 val
&= ~(SCC_EPCI_VCSR_DR
| SCC_EPCI_VCSR_AT
);
331 /* set base addresses. (no need to set?) */
333 /* memory space, bus master enable */
334 reg
= epci_base
+ PCI_COMMAND
;
335 val
= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
;
338 /* endian mode setup */
339 reg
= epci_base
+ SCC_EPCI_ECMODE
;
343 /* set control option */
344 reg
= epci_base
+ SCC_EPCI_CNTOPT
;
346 val
|= SCC_EPCI_CNTOPT_O2PMB
;
349 /* XXX: temporay: set registers for address conversion setup */
350 reg
= epci_base
+ SCC_EPCI_CNF10_REG
;
351 out_be32(reg
, 0x80000008);
352 reg
= epci_base
+ SCC_EPCI_CNF14_REG
;
353 out_be32(reg
, 0x40000008);
355 reg
= epci_base
+ SCC_EPCI_BAM0
;
356 out_be32(reg
, 0x80000000);
357 reg
= epci_base
+ SCC_EPCI_BAM1
;
358 out_be32(reg
, 0xe0000000);
360 reg
= epci_base
+ SCC_EPCI_PVBAT
;
361 out_be32(reg
, 0x80000000);
364 /* release external PCI reset */
365 reg
= epci_base
+ SCC_EPCI_CLKRST
;
367 val
|= SCC_EPCI_CLKRST_PCIRST
;
374 static int __init
celleb_setup_epci(struct device_node
*node
,
375 struct pci_controller
*hose
)
379 pr_debug("PCI: celleb_setup_epci()\n");
383 * Celleb epci uses cfg_addr and cfg_data member of
384 * pci_controller structure in irregular way.
386 * cfg_addr is used to map for control registers of
389 * cfg_data is used for configuration area of devices
390 * on Celleb epci buses.
393 if (of_address_to_resource(node
, 0, &r
))
395 hose
->cfg_addr
= ioremap(r
.start
, resource_size(&r
));
398 pr_debug("EPCI: cfg_addr map 0x%016llx->0x%016lx + 0x%016llx\n",
399 r
.start
, (unsigned long)hose
->cfg_addr
, resource_size(&r
));
401 if (of_address_to_resource(node
, 2, &r
))
403 hose
->cfg_data
= ioremap(r
.start
, resource_size(&r
));
406 pr_debug("EPCI: cfg_data map 0x%016llx->0x%016lx + 0x%016llx\n",
407 r
.start
, (unsigned long)hose
->cfg_data
, resource_size(&r
));
409 hose
->ops
= &celleb_epci_ops
;
410 celleb_epci_init(hose
);
416 iounmap(hose
->cfg_addr
);
419 iounmap(hose
->cfg_data
);
423 struct celleb_phb_spec celleb_epci_spec __initdata
= {
424 .setup
= celleb_setup_epci
,
425 .ops
= &spiderpci_ops
,
426 .iowa_init
= &spiderpci_iowa_init
,
427 .iowa_data
= (void *)0,