arch/powerpc/platforms/cell/spu_base.c

   1 /*
   2  * Low-level SPU handling
   3  *
   4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   5  *
   6  * Author: Arnd Bergmann <arndb@de.ibm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #undef DEBUG
  24
  25 #include <linux/interrupt.h>
  26 #include <linux/list.h>
  27 #include <linux/module.h>
  28 #include <linux/poll.h>
  29 #include <linux/ptrace.h>
  30 #include <linux/slab.h>
  31 #include <linux/wait.h>
  32
  33 #include <asm/io.h>
  34 #include <asm/prom.h>
  35 #include <asm/semaphore.h>
  36 #include <asm/spu.h>
  37 #include <asm/mmu_context.h>
  38
  39 #include "interrupt.h"
  40
  41 static int __spu_trap_invalid_dma(struct spu *spu)
  42 {
  43         pr_debug("%s\n", __FUNCTION__);
  44         force_sig(SIGBUS, /* info, */ current);
  45         return 0;
  46 }
  47
  48 static int __spu_trap_dma_align(struct spu *spu)
  49 {
  50         pr_debug("%s\n", __FUNCTION__);
  51         force_sig(SIGBUS, /* info, */ current);
  52         return 0;
  53 }
  54
  55 static int __spu_trap_error(struct spu *spu)
  56 {
  57         pr_debug("%s\n", __FUNCTION__);
  58         force_sig(SIGILL, /* info, */ current);
  59         return 0;
  60 }
  61
  62 static void spu_restart_dma(struct spu *spu)
  63 {
  64         struct spu_priv2 __iomem *priv2 = spu->priv2;
  65
  66         if (!test_bit(SPU_CONTEXT_SWITCH_PENDING_nr, &spu->flags))
  67                 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
  68 }
  69
  70 static int __spu_trap_data_seg(struct spu *spu, unsigned long ea)
  71 {
  72         struct spu_priv2 __iomem *priv2 = spu->priv2;
  73         struct mm_struct *mm = spu->mm;
  74         u64 esid, vsid;
  75
  76         pr_debug("%s\n", __FUNCTION__);
  77
  78         if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE_nr, &spu->flags)) {
  79                 /* SLBs are pre-loaded for context switch, so
  80                  * we should never get here!
  81                  */
  82                 printk("%s: invalid access during switch!\n", __func__);
  83                 return 1;
  84         }
  85         if (!mm || (REGION_ID(ea) != USER_REGION_ID)) {
  86                 /* Future: support kernel segments so that drivers
  87                  * can use SPUs.
  88                  */
  89                 pr_debug("invalid region access at %016lx\n", ea);
  90                 return 1;
  91         }
  92
  93         esid = (ea & ESID_MASK) | SLB_ESID_V;
  94         vsid = (get_vsid(mm->context.id, ea) << SLB_VSID_SHIFT) | SLB_VSID_USER;
  95         if (in_hugepage_area(mm->context, ea))
  96                 vsid |= SLB_VSID_L;
  97
  98         out_be64(&priv2->slb_index_W, spu->slb_replace);
  99         out_be64(&priv2->slb_vsid_RW, vsid);
 100         out_be64(&priv2->slb_esid_RW, esid);
 101
 102         spu->slb_replace++;
 103         if (spu->slb_replace >= 8)
 104                 spu->slb_replace = 0;
 105
 106         spu_restart_dma(spu);
 107
 108         return 0;
 109 }
 110
 111 extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap); //XXX
 112 static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
 113 {
 114         pr_debug("%s\n", __FUNCTION__);
 115
 116         /* Handle kernel space hash faults immediately.
 117            User hash faults need to be deferred to process context. */
 118         if ((dsisr & MFC_DSISR_PTE_NOT_FOUND)
 119             && REGION_ID(ea) != USER_REGION_ID
 120             && hash_page(ea, _PAGE_PRESENT, 0x300) == 0) {
 121                 spu_restart_dma(spu);
 122                 return 0;
 123         }
 124
 125         if (test_bit(SPU_CONTEXT_SWITCH_ACTIVE_nr, &spu->flags)) {
 126                 printk("%s: invalid access during switch!\n", __func__);
 127                 return 1;
 128         }
 129
 130         spu->dar = ea;
 131         spu->dsisr = dsisr;
 132         mb();
 133         wake_up(&spu->stop_wq);
 134         return 0;
 135 }
 136
 137 static int __spu_trap_mailbox(struct spu *spu)
 138 {
 139         if (spu->ibox_callback)
 140                 spu->ibox_callback(spu);
 141
 142         /* atomically disable SPU mailbox interrupts */
 143         spin_lock(&spu->register_lock);
 144         out_be64(&spu->priv1->int_mask_class2_RW,
 145                 in_be64(&spu->priv1->int_mask_class2_RW) & ~0x1);
 146         spin_unlock(&spu->register_lock);
 147         return 0;
 148 }
 149
 150 static int __spu_trap_stop(struct spu *spu)
 151 {
 152         pr_debug("%s\n", __FUNCTION__);
 153         spu->stop_code = in_be32(&spu->problem->spu_status_R);
 154         wake_up(&spu->stop_wq);
 155         return 0;
 156 }
 157
 158 static int __spu_trap_halt(struct spu *spu)
 159 {
 160         pr_debug("%s\n", __FUNCTION__);
 161         spu->stop_code = in_be32(&spu->problem->spu_status_R);
 162         wake_up(&spu->stop_wq);
 163         return 0;
 164 }
 165
 166 static int __spu_trap_tag_group(struct spu *spu)
 167 {
 168         pr_debug("%s\n", __FUNCTION__);
 169         /* wake_up(&spu->dma_wq); */
 170         return 0;
 171 }
 172
 173 static int __spu_trap_spubox(struct spu *spu)
 174 {
 175         if (spu->wbox_callback)
 176                 spu->wbox_callback(spu);
 177
 178         /* atomically disable SPU mailbox interrupts */
 179         spin_lock(&spu->register_lock);
 180         out_be64(&spu->priv1->int_mask_class2_RW,
 181                 in_be64(&spu->priv1->int_mask_class2_RW) & ~0x10);
 182         spin_unlock(&spu->register_lock);
 183         return 0;
 184 }
 185
 186 static irqreturn_t
 187 spu_irq_class_0(int irq, void *data, struct pt_regs *regs)
 188 {
 189         struct spu *spu;
 190
 191         spu = data;
 192         spu->class_0_pending = 1;
 193         wake_up(&spu->stop_wq);
 194
 195         return IRQ_HANDLED;
 196 }
 197
 198 static int
 199 spu_irq_class_0_bottom(struct spu *spu)
 200 {
 201         unsigned long stat;
 202
 203         spu->class_0_pending = 0;
 204
 205         stat = in_be64(&spu->priv1->int_stat_class0_RW);
 206
 207         if (stat & 1) /* invalid MFC DMA */
 208                 __spu_trap_invalid_dma(spu);
 209
 210         if (stat & 2) /* invalid DMA alignment */
 211                 __spu_trap_dma_align(spu);
 212
 213         if (stat & 4) /* error on SPU */
 214                 __spu_trap_error(spu);
 215
 216         out_be64(&spu->priv1->int_stat_class0_RW, stat);
 217         return 0;
 218 }
 219
 220 static irqreturn_t
 221 spu_irq_class_1(int irq, void *data, struct pt_regs *regs)
 222 {
 223         struct spu *spu;
 224         unsigned long stat, mask, dar, dsisr;
 225
 226         spu = data;
 227
 228         /* atomically read & clear class1 status. */
 229         spin_lock(&spu->register_lock);
 230         mask  = in_be64(&spu->priv1->int_mask_class1_RW);
 231         stat  = in_be64(&spu->priv1->int_stat_class1_RW) & mask;
 232         dar   = in_be64(&spu->priv1->mfc_dar_RW);
 233         dsisr = in_be64(&spu->priv1->mfc_dsisr_RW);
 234         out_be64(&spu->priv1->mfc_dsisr_RW, 0UL);
 235         out_be64(&spu->priv1->int_stat_class1_RW, stat);
 236         spin_unlock(&spu->register_lock);
 237
 238         if (stat & 1) /* segment fault */
 239                 __spu_trap_data_seg(spu, dar);
 240
 241         if (stat & 2) { /* mapping fault */
 242                 __spu_trap_data_map(spu, dar, dsisr);
 243         }
 244
 245         if (stat & 4) /* ls compare & suspend on get */
 246                 ;
 247
 248         if (stat & 8) /* ls compare & suspend on put */
 249                 ;
 250
 251         return stat ? IRQ_HANDLED : IRQ_NONE;
 252 }
 253
 254 static irqreturn_t
 255 spu_irq_class_2(int irq, void *data, struct pt_regs *regs)
 256 {
 257         struct spu *spu;
 258         unsigned long stat;
 259
 260         spu = data;
 261         stat = in_be64(&spu->priv1->int_stat_class2_RW);
 262
 263         pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat,
 264                 in_be64(&spu->priv1->int_mask_class2_RW));
 265
 266
 267         if (stat & 1)  /* PPC core mailbox */
 268                 __spu_trap_mailbox(spu);
 269
 270         if (stat & 2) /* SPU stop-and-signal */
 271                 __spu_trap_stop(spu);
 272
 273         if (stat & 4) /* SPU halted */
 274                 __spu_trap_halt(spu);
 275
 276         if (stat & 8) /* DMA tag group complete */
 277                 __spu_trap_tag_group(spu);
 278
 279         if (stat & 0x10) /* SPU mailbox threshold */
 280                 __spu_trap_spubox(spu);
 281
 282         out_be64(&spu->priv1->int_stat_class2_RW, stat);
 283         return stat ? IRQ_HANDLED : IRQ_NONE;
 284 }
 285
 286 static int
 287 spu_request_irqs(struct spu *spu)
 288 {
 289         int ret;
 290         int irq_base;
 291
 292         irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
 293
 294         snprintf(spu->irq_c0, sizeof (spu->irq_c0), "spe%02d.0", spu->number);
 295         ret = request_irq(irq_base + spu->isrc,
 296                  spu_irq_class_0, 0, spu->irq_c0, spu);
 297         if (ret)
 298                 goto out;
 299         out_be64(&spu->priv1->int_mask_class0_RW, 0x7);
 300
 301         snprintf(spu->irq_c1, sizeof (spu->irq_c1), "spe%02d.1", spu->number);
 302         ret = request_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc,
 303                  spu_irq_class_1, 0, spu->irq_c1, spu);
 304         if (ret)
 305                 goto out1;
 306         out_be64(&spu->priv1->int_mask_class1_RW, 0x3);
 307
 308         snprintf(spu->irq_c2, sizeof (spu->irq_c2), "spe%02d.2", spu->number);
 309         ret = request_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc,
 310                  spu_irq_class_2, 0, spu->irq_c2, spu);
 311         if (ret)
 312                 goto out2;
 313         out_be64(&spu->priv1->int_mask_class2_RW, 0xe);
 314         goto out;
 315
 316 out2:
 317         free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
 318 out1:
 319         free_irq(irq_base + spu->isrc, spu);
 320 out:
 321         return ret;
 322 }
 323
 324 static void
 325 spu_free_irqs(struct spu *spu)
 326 {
 327         int irq_base;
 328
 329         irq_base = IIC_NODE_STRIDE * spu->node + IIC_SPE_OFFSET;
 330
 331         free_irq(irq_base + spu->isrc, spu);
 332         free_irq(irq_base + IIC_CLASS_STRIDE + spu->isrc, spu);
 333         free_irq(irq_base + 2*IIC_CLASS_STRIDE + spu->isrc, spu);
 334 }
 335
 336 static LIST_HEAD(spu_list);
 337 static DECLARE_MUTEX(spu_mutex);
 338
 339 static void spu_init_channels(struct spu *spu)
 340 {
 341         static const struct {
 342                  unsigned channel;
 343                  unsigned count;
 344         } zero_list[] = {
 345                 { 0x00, 1, }, { 0x01, 1, }, { 0x03, 1, }, { 0x04, 1, },
 346                 { 0x18, 1, }, { 0x19, 1, }, { 0x1b, 1, }, { 0x1d, 1, },
 347         }, count_list[] = {
 348                 { 0x00, 0, }, { 0x03, 0, }, { 0x04, 0, }, { 0x15, 16, },
 349                 { 0x17, 1, }, { 0x18, 0, }, { 0x19, 0, }, { 0x1b, 0, },
 350                 { 0x1c, 1, }, { 0x1d, 0, }, { 0x1e, 1, },
 351         };
 352         struct spu_priv2 *priv2;
 353         int i;
 354
 355         priv2 = spu->priv2;
 356
 357         /* initialize all channel data to zero */
 358         for (i = 0; i < ARRAY_SIZE(zero_list); i++) {
 359                 int count;
 360
 361                 out_be64(&priv2->spu_chnlcntptr_RW, zero_list[i].channel);
 362                 for (count = 0; count < zero_list[i].count; count++)
 363                         out_be64(&priv2->spu_chnldata_RW, 0);
 364         }
 365
 366         /* initialize channel counts to meaningful values */
 367         for (i = 0; i < ARRAY_SIZE(count_list); i++) {
 368                 out_be64(&priv2->spu_chnlcntptr_RW, count_list[i].channel);
 369                 out_be64(&priv2->spu_chnlcnt_RW, count_list[i].count);
 370         }
 371 }
 372
 373 static void spu_init_regs(struct spu *spu)
 374 {
 375         out_be64(&spu->priv1->int_mask_class0_RW, 0x7);
 376         out_be64(&spu->priv1->int_mask_class1_RW, 0x3);
 377         out_be64(&spu->priv1->int_mask_class2_RW, 0xe);
 378 }
 379
 380 struct spu *spu_alloc(void)
 381 {
 382         struct spu *spu;
 383
 384         down(&spu_mutex);
 385         if (!list_empty(&spu_list)) {
 386                 spu = list_entry(spu_list.next, struct spu, list);
 387                 list_del_init(&spu->list);
 388                 pr_debug("Got SPU %x %d\n", spu->isrc, spu->number);
 389         } else {
 390                 pr_debug("No SPU left\n");
 391                 spu = NULL;
 392         }
 393         up(&spu_mutex);
 394
 395         if (spu) {
 396                 spu_init_channels(spu);
 397                 spu_init_regs(spu);
 398         }
 399
 400         return spu;
 401 }
 402 EXPORT_SYMBOL_GPL(spu_alloc);
 403
 404 void spu_free(struct spu *spu)
 405 {
 406         down(&spu_mutex);
 407         list_add_tail(&spu->list, &spu_list);
 408         up(&spu_mutex);
 409 }
 410 EXPORT_SYMBOL_GPL(spu_free);
 411
 412 static int spu_handle_mm_fault(struct spu *spu)
 413 {
 414         struct mm_struct *mm = spu->mm;
 415         struct vm_area_struct *vma;
 416         u64 ea, dsisr, is_write;
 417         int ret;
 418
 419         ea = spu->dar;
 420         dsisr = spu->dsisr;
 421 #if 0
 422         if (!IS_VALID_EA(ea)) {
 423                 return -EFAULT;
 424         }
 425 #endif /* XXX */
 426         if (mm == NULL) {
 427                 return -EFAULT;
 428         }
 429         if (mm->pgd == NULL) {
 430                 return -EFAULT;
 431         }
 432
 433         down_read(&mm->mmap_sem);
 434         vma = find_vma(mm, ea);
 435         if (!vma)
 436                 goto bad_area;
 437         if (vma->vm_start <= ea)
 438                 goto good_area;
 439         if (!(vma->vm_flags & VM_GROWSDOWN))
 440                 goto bad_area;
 441 #if 0
 442         if (expand_stack(vma, ea))
 443                 goto bad_area;
 444 #endif /* XXX */
 445 good_area:
 446         is_write = dsisr & MFC_DSISR_ACCESS_PUT;
 447         if (is_write) {
 448                 if (!(vma->vm_flags & VM_WRITE))
 449                         goto bad_area;
 450         } else {
 451                 if (dsisr & MFC_DSISR_ACCESS_DENIED)
 452                         goto bad_area;
 453                 if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
 454                         goto bad_area;
 455         }
 456         ret = 0;
 457         switch (handle_mm_fault(mm, vma, ea, is_write)) {
 458         case VM_FAULT_MINOR:
 459                 current->min_flt++;
 460                 break;
 461         case VM_FAULT_MAJOR:
 462                 current->maj_flt++;
 463                 break;
 464         case VM_FAULT_SIGBUS:
 465                 ret = -EFAULT;
 466                 goto bad_area;
 467         case VM_FAULT_OOM:
 468                 ret = -ENOMEM;
 469                 goto bad_area;
 470         default:
 471                 BUG();
 472         }
 473         up_read(&mm->mmap_sem);
 474         return ret;
 475
 476 bad_area:
 477         up_read(&mm->mmap_sem);
 478         return -EFAULT;
 479 }
 480
 481 static int spu_handle_pte_fault(struct spu *spu)
 482 {
 483         u64 ea, dsisr, access, error = 0UL;
 484         int ret = 0;
 485
 486         ea = spu->dar;
 487         dsisr = spu->dsisr;
 488         if (dsisr & MFC_DSISR_PTE_NOT_FOUND) {
 489                 access = (_PAGE_PRESENT | _PAGE_USER);
 490                 access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL;
 491                 if (hash_page(ea, access, 0x300) != 0)
 492                         error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
 493         }
 494         if ((error & CLASS1_ENABLE_STORAGE_FAULT_INTR) ||
 495             (dsisr & MFC_DSISR_ACCESS_DENIED)) {
 496                 if ((ret = spu_handle_mm_fault(spu)) != 0)
 497                         error |= CLASS1_ENABLE_STORAGE_FAULT_INTR;
 498                 else
 499                         error &= ~CLASS1_ENABLE_STORAGE_FAULT_INTR;
 500         }
 501         spu->dar = 0UL;
 502         spu->dsisr = 0UL;
 503         if (!error) {
 504                 spu_restart_dma(spu);
 505         } else {
 506                 __spu_trap_invalid_dma(spu);
 507         }
 508         return ret;
 509 }
 510
 511 static inline int spu_pending(struct spu *spu, u32 * stat)
 512 {
 513         struct spu_problem __iomem *prob = spu->problem;
 514         u64 pte_fault;
 515
 516         *stat = in_be32(&prob->spu_status_R);
 517         pte_fault = spu->dsisr &
 518                     (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED);
 519         return (!(*stat & 0x1) || pte_fault || spu->class_0_pending) ? 1 : 0;
 520 }
 521
 522 int spu_run(struct spu *spu)
 523 {
 524         struct spu_problem __iomem *prob;
 525         struct spu_priv1 __iomem *priv1;
 526         struct spu_priv2 __iomem *priv2;
 527         u32 status;
 528         int ret;
 529
 530         prob = spu->problem;
 531         priv1 = spu->priv1;
 532         priv2 = spu->priv2;
 533
 534         /* Let SPU run.  */
 535         eieio();
 536         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
 537
 538         do {
 539                 ret = wait_event_interruptible(spu->stop_wq,
 540                                                spu_pending(spu, &status));
 541
 542                 if (spu->dsisr &
 543                     (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED))
 544                         ret = spu_handle_pte_fault(spu);
 545
 546                 if (spu->class_0_pending)
 547                         spu_irq_class_0_bottom(spu);
 548
 549                 if (!ret && signal_pending(current))
 550                         ret = -ERESTARTSYS;
 551
 552         } while (!ret && !(status &
 553                            (SPU_STATUS_STOPPED_BY_STOP |
 554                             SPU_STATUS_STOPPED_BY_HALT)));
 555
 556         /* Ensure SPU is stopped.  */
 557         out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
 558         eieio();
 559         while (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)
 560                 cpu_relax();
 561
 562         out_be64(&priv2->slb_invalidate_all_W, 0);
 563         out_be64(&priv1->tlb_invalidate_entry_W, 0UL);
 564         eieio();
 565
 566         /* Check for SPU breakpoint.  */
 567         if (unlikely(current->ptrace & PT_PTRACED)) {
 568                 status = in_be32(&prob->spu_status_R);
 569
 570                 if ((status & SPU_STATUS_STOPPED_BY_STOP)
 571                     && status >> SPU_STOP_STATUS_SHIFT == 0x3fff) {
 572                         force_sig(SIGTRAP, current);
 573                         ret = -ERESTARTSYS;
 574                 }
 575         }
 576
 577         return ret;
 578 }
 579 EXPORT_SYMBOL_GPL(spu_run);
 580
 581 static void __iomem * __init map_spe_prop(struct device_node *n,
 582                                                  const char *name)
 583 {
 584         struct address_prop {
 585                 unsigned long address;
 586                 unsigned int len;
 587         } __attribute__((packed)) *prop;
 588
 589         void *p;
 590         int proplen;
 591
 592         p = get_property(n, name, &proplen);
 593         if (proplen != sizeof (struct address_prop))
 594                 return NULL;
 595
 596         prop = p;
 597
 598         return ioremap(prop->address, prop->len);
 599 }
 600
 601 static void spu_unmap(struct spu *spu)
 602 {
 603         iounmap(spu->priv2);
 604         iounmap(spu->priv1);
 605         iounmap(spu->problem);
 606         iounmap((u8 __iomem *)spu->local_store);
 607 }
 608
 609 static int __init spu_map_device(struct spu *spu, struct device_node *spe)
 610 {
 611         char *prop;
 612         int ret;
 613
 614         ret = -ENODEV;
 615         prop = get_property(spe, "isrc", NULL);
 616         if (!prop)
 617                 goto out;
 618         spu->isrc = *(unsigned int *)prop;
 619
 620         spu->name = get_property(spe, "name", NULL);
 621         if (!spu->name)
 622                 goto out;
 623
 624         prop = get_property(spe, "local-store", NULL);
 625         if (!prop)
 626                 goto out;
 627         spu->local_store_phys = *(unsigned long *)prop;
 628
 629         /* we use local store as ram, not io memory */
 630         spu->local_store = (void __force *)map_spe_prop(spe, "local-store");
 631         if (!spu->local_store)
 632                 goto out;
 633
 634         spu->problem= map_spe_prop(spe, "problem");
 635         if (!spu->problem)
 636                 goto out_unmap;
 637
 638         spu->priv1= map_spe_prop(spe, "priv1");
 639         if (!spu->priv1)
 640                 goto out_unmap;
 641
 642         spu->priv2= map_spe_prop(spe, "priv2");
 643         if (!spu->priv2)
 644                 goto out_unmap;
 645         ret = 0;
 646         goto out;
 647
 648 out_unmap:
 649         spu_unmap(spu);
 650 out:
 651         return ret;
 652 }
 653
 654 static int __init find_spu_node_id(struct device_node *spe)
 655 {
 656         unsigned int *id;
 657         struct device_node *cpu;
 658
 659         cpu = spe->parent->parent;
 660         id = (unsigned int *)get_property(cpu, "node-id", NULL);
 661
 662         return id ? *id : 0;
 663 }
 664
 665 static int __init create_spu(struct device_node *spe)
 666 {
 667         struct spu *spu;
 668         int ret;
 669         static int number;
 670
 671         ret = -ENOMEM;
 672         spu = kmalloc(sizeof (*spu), GFP_KERNEL);
 673         if (!spu)
 674                 goto out;
 675
 676         ret = spu_map_device(spu, spe);
 677         if (ret)
 678                 goto out_free;
 679
 680         spu->node = find_spu_node_id(spe);
 681         spu->stop_code = 0;
 682         spu->slb_replace = 0;
 683         spu->mm = NULL;
 684         spu->ctx = NULL;
 685         spu->rq = NULL;
 686         spu->pid = 0;
 687         spu->class_0_pending = 0;
 688         spu->flags = 0UL;
 689         spu->dar = 0UL;
 690         spu->dsisr = 0UL;
 691         spin_lock_init(&spu->register_lock);
 692
 693         out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
 694         out_be64(&spu->priv1->mfc_sr1_RW, 0x33);
 695
 696         init_waitqueue_head(&spu->stop_wq);
 697         spu->ibox_callback = NULL;
 698         spu->wbox_callback = NULL;
 699
 700         down(&spu_mutex);
 701         spu->number = number++;
 702         ret = spu_request_irqs(spu);
 703         if (ret)
 704                 goto out_unmap;
 705
 706         list_add(&spu->list, &spu_list);
 707         up(&spu_mutex);
 708
 709         pr_debug(KERN_DEBUG "Using SPE %s %02x %p %p %p %p %d\n",
 710                 spu->name, spu->isrc, spu->local_store,
 711                 spu->problem, spu->priv1, spu->priv2, spu->number);
 712         goto out;
 713
 714 out_unmap:
 715         up(&spu_mutex);
 716         spu_unmap(spu);
 717 out_free:
 718         kfree(spu);
 719 out:
 720         return ret;
 721 }
 722
 723 static void destroy_spu(struct spu *spu)
 724 {
 725         list_del_init(&spu->list);
 726
 727         spu_free_irqs(spu);
 728         spu_unmap(spu);
 729         kfree(spu);
 730 }
 731
 732 static void cleanup_spu_base(void)
 733 {
 734         struct spu *spu, *tmp;
 735         down(&spu_mutex);
 736         list_for_each_entry_safe(spu, tmp, &spu_list, list)
 737                 destroy_spu(spu);
 738         up(&spu_mutex);
 739 }
 740 module_exit(cleanup_spu_base);
 741
 742 static int __init init_spu_base(void)
 743 {
 744         struct device_node *node;
 745         int ret;
 746
 747         ret = -ENODEV;
 748         for (node = of_find_node_by_type(NULL, "spe");
 749                         node; node = of_find_node_by_type(node, "spe")) {
 750                 ret = create_spu(node);
 751                 if (ret) {
 752                         printk(KERN_WARNING "%s: Error initializing %s\n",
 753                                 __FUNCTION__, node->name);
 754                         cleanup_spu_base();
 755                         break;
 756                 }
 757         }
 758         /* in some old firmware versions, the spe is called 'spc', so we
 759            look for that as well */
 760         for (node = of_find_node_by_type(NULL, "spc");
 761                         node; node = of_find_node_by_type(node, "spc")) {
 762                 ret = create_spu(node);
 763                 if (ret) {
 764                         printk(KERN_WARNING "%s: Error initializing %s\n",
 765                                 __FUNCTION__, node->name);
 766                         cleanup_spu_base();
 767                         break;
 768                 }
 769         }
 770         return ret;
 771 }
 772 module_init(init_spu_base);
 773
 774 MODULE_LICENSE("GPL");
 775 MODULE_AUTHOR("Arnd Bergmann <arndb@de.ibm.com>");