2 * Copyright (C) 2001 Allan Trautman, IBM Corporation
4 * iSeries specific routines for PCI.
6 * Based on code from pci.c and iSeries_pci.c 32bit
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/string.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/ide.h>
28 #include <linux/pci.h>
33 #include <asm/machdep.h>
34 #include <asm/pci-bridge.h>
35 #include <asm/iommu.h>
36 #include <asm/abs_addr.h>
38 #include <asm/iseries/hv_call_xm.h>
39 #include <asm/iseries/mf.h>
41 #include <asm/ppc-pci.h>
47 extern unsigned long io_page_mask
;
50 * Forward declares of prototypes.
52 static struct device_node
*find_Device_Node(int bus
, int devfn
);
53 static void scan_PHB_slots(struct pci_controller
*Phb
);
54 static void scan_EADS_bridge(HvBusNumber Bus
, HvSubBusNumber SubBus
, int IdSel
);
55 static int scan_bridge_slot(HvBusNumber Bus
, struct HvCallPci_BridgeInfo
*Info
);
57 LIST_HEAD(iSeries_Global_Device_List
);
59 static int DeviceCount
;
61 /* Counters and control flags. */
62 static long Pci_Io_Read_Count
;
63 static long Pci_Io_Write_Count
;
65 static long Pci_Cfg_Read_Count
;
66 static long Pci_Cfg_Write_Count
;
68 static long Pci_Error_Count
;
70 static int Pci_Retry_Max
= 3; /* Only retry 3 times */
71 static int Pci_Error_Flag
= 1; /* Set Retry Error on. */
73 static struct pci_ops iSeries_pci_ops
;
77 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
79 #define IOMM_TABLE_MAX_ENTRIES 1024
80 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
81 #define BASE_IO_MEMORY 0xE000000000000000UL
83 static unsigned long max_io_memory
= 0xE000000000000000UL
;
84 static long current_iomm_table_entry
;
89 static struct device_node
**iomm_table
;
90 static u8
*iobar_table
;
93 * Static and Global variables
95 static char *pci_io_text
= "iSeries PCI I/O";
96 static DEFINE_SPINLOCK(iomm_table_lock
);
99 * iomm_table_initialize
101 * Allocates and initalizes the Address Translation Table and Bar
102 * Tables to get them ready for use. Must be called before any
103 * I/O space is handed out to the device BARs.
105 static void iomm_table_initialize(void)
107 spin_lock(&iomm_table_lock
);
108 iomm_table
= kmalloc(sizeof(*iomm_table
) * IOMM_TABLE_MAX_ENTRIES
,
110 iobar_table
= kmalloc(sizeof(*iobar_table
) * IOMM_TABLE_MAX_ENTRIES
,
112 spin_unlock(&iomm_table_lock
);
113 if ((iomm_table
== NULL
) || (iobar_table
== NULL
))
114 panic("PCI: I/O tables allocation failed.\n");
118 * iomm_table_allocate_entry
120 * Adds pci_dev entry in address translation table
122 * - Allocates the number of entries required in table base on BAR
124 * - Allocates starting at BASE_IO_MEMORY and increases.
125 * - The size is round up to be a multiple of entry size.
126 * - CurrentIndex is incremented to keep track of the last entry.
127 * - Builds the resource entry for allocated BARs.
129 static void iomm_table_allocate_entry(struct pci_dev
*dev
, int bar_num
)
131 struct resource
*bar_res
= &dev
->resource
[bar_num
];
132 long bar_size
= pci_resource_len(dev
, bar_num
);
135 * No space to allocate, quick exit, skip Allocation.
140 * Set Resource values.
142 spin_lock(&iomm_table_lock
);
143 bar_res
->name
= pci_io_text
;
145 IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
;
146 bar_res
->start
+= BASE_IO_MEMORY
;
147 bar_res
->end
= bar_res
->start
+ bar_size
- 1;
149 * Allocate the number of table entries needed for BAR.
151 while (bar_size
> 0 ) {
152 iomm_table
[current_iomm_table_entry
] = dev
->sysdata
;
153 iobar_table
[current_iomm_table_entry
] = bar_num
;
154 bar_size
-= IOMM_TABLE_ENTRY_SIZE
;
155 ++current_iomm_table_entry
;
157 max_io_memory
= BASE_IO_MEMORY
+
158 (IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
);
159 spin_unlock(&iomm_table_lock
);
163 * allocate_device_bars
165 * - Allocates ALL pci_dev BAR's and updates the resources with the
166 * BAR value. BARS with zero length will have the resources
167 * The HvCallPci_getBarParms is used to get the size of the BAR
168 * space. It calls iomm_table_allocate_entry to allocate
170 * - Loops through The Bar resources(0 - 5) including the ROM
173 static void allocate_device_bars(struct pci_dev
*dev
)
175 struct resource
*bar_res
;
178 for (bar_num
= 0; bar_num
<= PCI_ROM_RESOURCE
; ++bar_num
) {
179 bar_res
= &dev
->resource
[bar_num
];
180 iomm_table_allocate_entry(dev
, bar_num
);
185 * Log error information to system console.
186 * Filter out the device not there errors.
187 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
188 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
189 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
191 static void pci_Log_Error(char *Error_Text
, int Bus
, int SubBus
,
192 int AgentId
, int HvRc
)
196 printk(KERN_ERR
"PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
197 Error_Text
, Bus
, SubBus
, AgentId
, HvRc
);
201 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
203 static struct device_node
*build_device_node(HvBusNumber Bus
,
204 HvSubBusNumber SubBus
, int AgentId
, int Function
)
206 struct device_node
*node
;
209 node
= kmalloc(sizeof(struct device_node
), GFP_KERNEL
);
212 memset(node
, 0, sizeof(struct device_node
));
213 pdn
= kzalloc(sizeof(*pdn
), GFP_KERNEL
);
220 list_add_tail(&pdn
->Device_List
, &iSeries_Global_Device_List
);
222 pdn
->bussubno
= SubBus
;
223 pdn
->devfn
= PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId
), Function
);
228 * unsigned long __init find_and_init_phbs(void)
231 * This function checks for all possible system PCI host bridges that connect
232 * PCI buses. The system hypervisor is queried as to the guest partition
233 * ownership status. A pci_controller is built for any bus which is partially
234 * owned or fully owned by this guest partition.
236 unsigned long __init
find_and_init_phbs(void)
238 struct pci_controller
*phb
;
241 /* Check all possible buses. */
242 for (bus
= 0; bus
< 256; bus
++) {
243 int ret
= HvCallXm_testBus(bus
);
245 printk("bus %d appears to exist\n", bus
);
247 phb
= pcibios_alloc_controller(NULL
);
251 phb
->pci_mem_offset
= phb
->local_number
= bus
;
252 phb
->first_busno
= bus
;
253 phb
->last_busno
= bus
;
254 phb
->ops
= &iSeries_pci_ops
;
256 /* Find and connect the devices. */
260 * Check for Unexpected Return code, a clue that something
263 else if (ret
!= 0x0301)
264 printk(KERN_ERR
"Unexpected Return on Probe(0x%04X): 0x%04X",
271 * iSeries_pcibios_init
273 * Chance to initialize and structures or variable before PCI Bus walk.
275 void iSeries_pcibios_init(void)
277 iomm_table_initialize();
278 find_and_init_phbs();
283 * iSeries_pci_final_fixup(void)
285 void __init
iSeries_pci_final_fixup(void)
287 struct pci_dev
*pdev
= NULL
;
288 struct device_node
*node
;
291 /* Fix up at the device node and pci_dev relationship */
292 mf_display_src(0xC9000100);
294 printk("pcibios_final_fixup\n");
295 for_each_pci_dev(pdev
) {
296 node
= find_Device_Node(pdev
->bus
->number
, pdev
->devfn
);
297 printk("pci dev %p (%x.%x), node %p\n", pdev
,
298 pdev
->bus
->number
, pdev
->devfn
, node
);
302 pdev
->sysdata
= (void *)node
;
303 PCI_DN(node
)->pcidev
= pdev
;
304 allocate_device_bars(pdev
);
305 iSeries_Device_Information(pdev
, DeviceCount
);
306 iommu_devnode_init_iSeries(node
);
308 printk("PCI: Device Tree not found for 0x%016lX\n",
309 (unsigned long)pdev
);
310 pdev
->irq
= PCI_DN(node
)->Irq
;
312 iSeries_activate_IRQs();
313 mf_display_src(0xC9000200);
316 void pcibios_fixup_bus(struct pci_bus
*PciBus
)
320 void pcibios_fixup_resources(struct pci_dev
*pdev
)
325 * Loop through each node function to find usable EADs bridges.
327 static void scan_PHB_slots(struct pci_controller
*Phb
)
329 struct HvCallPci_DeviceInfo
*DevInfo
;
330 HvBusNumber bus
= Phb
->local_number
; /* System Bus */
331 const HvSubBusNumber SubBus
= 0; /* EADs is always 0. */
334 const int MaxAgents
= 8;
336 DevInfo
= (struct HvCallPci_DeviceInfo
*)
337 kmalloc(sizeof(struct HvCallPci_DeviceInfo
), GFP_KERNEL
);
342 * Probe for EADs Bridges
344 for (IdSel
= 1; IdSel
< MaxAgents
; ++IdSel
) {
345 HvRc
= HvCallPci_getDeviceInfo(bus
, SubBus
, IdSel
,
346 iseries_hv_addr(DevInfo
),
347 sizeof(struct HvCallPci_DeviceInfo
));
349 if (DevInfo
->deviceType
== HvCallPci_NodeDevice
)
350 scan_EADS_bridge(bus
, SubBus
, IdSel
);
352 printk("PCI: Invalid System Configuration(0x%02X)"
353 " for bus 0x%02x id 0x%02x.\n",
354 DevInfo
->deviceType
, bus
, IdSel
);
357 pci_Log_Error("getDeviceInfo", bus
, SubBus
, IdSel
, HvRc
);
362 static void scan_EADS_bridge(HvBusNumber bus
, HvSubBusNumber SubBus
,
365 struct HvCallPci_BridgeInfo
*BridgeInfo
;
370 BridgeInfo
= (struct HvCallPci_BridgeInfo
*)
371 kmalloc(sizeof(struct HvCallPci_BridgeInfo
), GFP_KERNEL
);
372 if (BridgeInfo
== NULL
)
375 /* Note: hvSubBus and irq is always be 0 at this level! */
376 for (Function
= 0; Function
< 8; ++Function
) {
377 AgentId
= ISERIES_PCI_AGENTID(IdSel
, Function
);
378 HvRc
= HvCallXm_connectBusUnit(bus
, SubBus
, AgentId
, 0);
380 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
381 bus
, IdSel
, Function
, AgentId
);
382 /* Connect EADs: 0x18.00.12 = 0x00 */
383 HvRc
= HvCallPci_getBusUnitInfo(bus
, SubBus
, AgentId
,
384 iseries_hv_addr(BridgeInfo
),
385 sizeof(struct HvCallPci_BridgeInfo
));
387 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
388 BridgeInfo
->busUnitInfo
.deviceType
,
389 BridgeInfo
->subBusNumber
,
390 BridgeInfo
->maxAgents
,
391 BridgeInfo
->maxSubBusNumber
,
392 BridgeInfo
->logicalSlotNumber
);
393 if (BridgeInfo
->busUnitInfo
.deviceType
==
394 HvCallPci_BridgeDevice
) {
395 /* Scan_Bridge_Slot...: 0x18.00.12 */
396 scan_bridge_slot(bus
, BridgeInfo
);
398 printk("PCI: Invalid Bridge Configuration(0x%02X)",
399 BridgeInfo
->busUnitInfo
.deviceType
);
401 } else if (HvRc
!= 0x000B)
402 pci_Log_Error("EADs Connect",
403 bus
, SubBus
, AgentId
, HvRc
);
409 * This assumes that the node slot is always on the primary bus!
411 static int scan_bridge_slot(HvBusNumber Bus
,
412 struct HvCallPci_BridgeInfo
*BridgeInfo
)
414 struct device_node
*node
;
415 HvSubBusNumber SubBus
= BridgeInfo
->subBusNumber
;
419 int IdSel
= ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus
);
420 int Function
= ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus
);
421 HvAgentId EADsIdSel
= ISERIES_PCI_AGENTID(IdSel
, Function
);
423 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
424 Irq
= iSeries_allocate_IRQ(Bus
, 0, EADsIdSel
);
427 * Connect all functions of any device found.
429 for (IdSel
= 1; IdSel
<= BridgeInfo
->maxAgents
; ++IdSel
) {
430 for (Function
= 0; Function
< 8; ++Function
) {
431 HvAgentId AgentId
= ISERIES_PCI_AGENTID(IdSel
, Function
);
432 HvRc
= HvCallXm_connectBusUnit(Bus
, SubBus
,
435 pci_Log_Error("Connect Bus Unit",
436 Bus
, SubBus
, AgentId
, HvRc
);
440 HvRc
= HvCallPci_configLoad16(Bus
, SubBus
, AgentId
,
441 PCI_VENDOR_ID
, &VendorId
);
443 pci_Log_Error("Read Vendor",
444 Bus
, SubBus
, AgentId
, HvRc
);
447 printk("read vendor ID: %x\n", VendorId
);
449 /* FoundDevice: 0x18.28.10 = 0x12AE */
450 HvRc
= HvCallPci_configStore8(Bus
, SubBus
, AgentId
,
451 PCI_INTERRUPT_LINE
, Irq
);
453 pci_Log_Error("PciCfgStore Irq Failed!",
454 Bus
, SubBus
, AgentId
, HvRc
);
457 node
= build_device_node(Bus
, SubBus
, EADsIdSel
, Function
);
458 PCI_DN(node
)->Irq
= Irq
;
459 PCI_DN(node
)->LogicalSlot
= BridgeInfo
->logicalSlotNumber
;
461 } /* for (Function = 0; Function < 8; ++Function) */
462 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
467 * I/0 Memory copy MUST use mmio commands on iSeries
468 * To do; For performance, include the hv call directly
470 void iSeries_memset_io(volatile void __iomem
*dest
, char c
, size_t Count
)
473 long NumberOfBytes
= Count
;
475 while (NumberOfBytes
> 0) {
476 iSeries_Write_Byte(ByteValue
, dest
++);
480 EXPORT_SYMBOL(iSeries_memset_io
);
482 void iSeries_memcpy_toio(volatile void __iomem
*dest
, void *source
, size_t count
)
485 long NumberOfBytes
= count
;
487 while (NumberOfBytes
> 0) {
488 iSeries_Write_Byte(*src
++, dest
++);
492 EXPORT_SYMBOL(iSeries_memcpy_toio
);
494 void iSeries_memcpy_fromio(void *dest
, const volatile void __iomem
*src
, size_t count
)
497 long NumberOfBytes
= count
;
499 while (NumberOfBytes
> 0) {
500 *dst
++ = iSeries_Read_Byte(src
++);
504 EXPORT_SYMBOL(iSeries_memcpy_fromio
);
507 * Look down the chain to find the matching Device Device
509 static struct device_node
*find_Device_Node(int bus
, int devfn
)
513 list_for_each_entry(pdn
, &iSeries_Global_Device_List
, Device_List
) {
514 if ((bus
== pdn
->busno
) && (devfn
== pdn
->devfn
))
522 * Returns the device node for the passed pci_dev
523 * Sanity Check Node PciDev to passed pci_dev
524 * If none is found, returns a NULL which the client must handle.
526 static struct device_node
*get_Device_Node(struct pci_dev
*pdev
)
528 struct device_node
*node
;
530 node
= pdev
->sysdata
;
531 if (node
== NULL
|| PCI_DN(node
)->pcidev
!= pdev
)
532 node
= find_Device_Node(pdev
->bus
->number
, pdev
->devfn
);
538 * Config space read and write functions.
539 * For now at least, we look for the device node for the bus and devfn
540 * that we are asked to access. It may be possible to translate the devfn
541 * to a subbus and deviceid more directly.
543 static u64 hv_cfg_read_func
[4] = {
544 HvCallPciConfigLoad8
, HvCallPciConfigLoad16
,
545 HvCallPciConfigLoad32
, HvCallPciConfigLoad32
548 static u64 hv_cfg_write_func
[4] = {
549 HvCallPciConfigStore8
, HvCallPciConfigStore16
,
550 HvCallPciConfigStore32
, HvCallPciConfigStore32
554 * Read PCI config space
556 static int iSeries_pci_read_config(struct pci_bus
*bus
, unsigned int devfn
,
557 int offset
, int size
, u32
*val
)
559 struct device_node
*node
= find_Device_Node(bus
->number
, devfn
);
561 struct HvCallPci_LoadReturn ret
;
564 return PCIBIOS_DEVICE_NOT_FOUND
;
567 return PCIBIOS_BAD_REGISTER_NUMBER
;
570 fn
= hv_cfg_read_func
[(size
- 1) & 3];
571 HvCall3Ret16(fn
, &ret
, iseries_ds_addr(node
), offset
, 0);
575 return PCIBIOS_DEVICE_NOT_FOUND
; /* or something */
583 * Write PCI config space
586 static int iSeries_pci_write_config(struct pci_bus
*bus
, unsigned int devfn
,
587 int offset
, int size
, u32 val
)
589 struct device_node
*node
= find_Device_Node(bus
->number
, devfn
);
594 return PCIBIOS_DEVICE_NOT_FOUND
;
596 return PCIBIOS_BAD_REGISTER_NUMBER
;
598 fn
= hv_cfg_write_func
[(size
- 1) & 3];
599 ret
= HvCall4(fn
, iseries_ds_addr(node
), offset
, val
, 0);
602 return PCIBIOS_DEVICE_NOT_FOUND
;
607 static struct pci_ops iSeries_pci_ops
= {
608 .read
= iSeries_pci_read_config
,
609 .write
= iSeries_pci_write_config
614 * -> On Failure, print and log information.
615 * Increment Retry Count, if exceeds max, panic partition.
617 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
618 * PCI: Device 23.90 ReadL Retry( 1)
619 * PCI: Device 23.90 ReadL Retry Successful(1)
621 static int CheckReturnCode(char *TextHdr
, struct device_node
*DevNode
,
625 struct pci_dn
*pdn
= PCI_DN(DevNode
);
629 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
630 TextHdr
, pdn
->busno
, pdn
->devfn
,
633 * Bump the retry and check for retry count exceeded.
634 * If, Exceeded, panic the system.
636 if (((*retry
) > Pci_Retry_Max
) &&
637 (Pci_Error_Flag
> 0)) {
638 mf_display_src(0xB6000103);
640 panic("PCI: Hardware I/O Error, SRC B6000103, "
641 "Automatic Reboot Disabled.\n");
643 return -1; /* Retry Try */
649 * Translate the I/O Address into a device node, bar, and bar offset.
650 * Note: Make sure the passed variable end up on the stack to avoid
651 * the exposure of being device global.
653 static inline struct device_node
*xlate_iomm_address(
654 const volatile void __iomem
*IoAddress
,
655 u64
*dsaptr
, u64
*BarOffsetPtr
)
657 unsigned long OrigIoAddr
;
658 unsigned long BaseIoAddr
;
659 unsigned long TableIndex
;
660 struct device_node
*DevNode
;
662 OrigIoAddr
= (unsigned long __force
)IoAddress
;
663 if ((OrigIoAddr
< BASE_IO_MEMORY
) || (OrigIoAddr
>= max_io_memory
))
665 BaseIoAddr
= OrigIoAddr
- BASE_IO_MEMORY
;
666 TableIndex
= BaseIoAddr
/ IOMM_TABLE_ENTRY_SIZE
;
667 DevNode
= iomm_table
[TableIndex
];
669 if (DevNode
!= NULL
) {
670 int barnum
= iobar_table
[TableIndex
];
671 *dsaptr
= iseries_ds_addr(DevNode
) | (barnum
<< 24);
672 *BarOffsetPtr
= BaseIoAddr
% IOMM_TABLE_ENTRY_SIZE
;
674 panic("PCI: Invalid PCI IoAddress detected!\n");
679 * Read MM I/O Instructions for the iSeries
680 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
681 * else, data is returned in big Endian format.
683 * iSeries_Read_Byte = Read Byte ( 8 bit)
684 * iSeries_Read_Word = Read Word (16 bit)
685 * iSeries_Read_Long = Read Long (32 bit)
687 u8
iSeries_Read_Byte(const volatile void __iomem
*IoAddress
)
692 struct HvCallPci_LoadReturn ret
;
693 struct device_node
*DevNode
=
694 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
696 if (DevNode
== NULL
) {
697 static unsigned long last_jiffies
;
698 static int num_printed
;
700 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
701 last_jiffies
= jiffies
;
704 if (num_printed
++ < 10)
705 printk(KERN_ERR
"iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress
);
710 HvCall3Ret16(HvCallPciBarLoad8
, &ret
, dsa
, BarOffset
, 0);
711 } while (CheckReturnCode("RDB", DevNode
, &retry
, ret
.rc
) != 0);
713 return (u8
)ret
.value
;
715 EXPORT_SYMBOL(iSeries_Read_Byte
);
717 u16
iSeries_Read_Word(const volatile void __iomem
*IoAddress
)
722 struct HvCallPci_LoadReturn ret
;
723 struct device_node
*DevNode
=
724 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
726 if (DevNode
== NULL
) {
727 static unsigned long last_jiffies
;
728 static int num_printed
;
730 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
731 last_jiffies
= jiffies
;
734 if (num_printed
++ < 10)
735 printk(KERN_ERR
"iSeries_Read_Word: invalid access at IO address %p\n", IoAddress
);
740 HvCall3Ret16(HvCallPciBarLoad16
, &ret
, dsa
,
742 } while (CheckReturnCode("RDW", DevNode
, &retry
, ret
.rc
) != 0);
744 return swab16((u16
)ret
.value
);
746 EXPORT_SYMBOL(iSeries_Read_Word
);
748 u32
iSeries_Read_Long(const volatile void __iomem
*IoAddress
)
753 struct HvCallPci_LoadReturn ret
;
754 struct device_node
*DevNode
=
755 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
757 if (DevNode
== NULL
) {
758 static unsigned long last_jiffies
;
759 static int num_printed
;
761 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
762 last_jiffies
= jiffies
;
765 if (num_printed
++ < 10)
766 printk(KERN_ERR
"iSeries_Read_Long: invalid access at IO address %p\n", IoAddress
);
771 HvCall3Ret16(HvCallPciBarLoad32
, &ret
, dsa
,
773 } while (CheckReturnCode("RDL", DevNode
, &retry
, ret
.rc
) != 0);
775 return swab32((u32
)ret
.value
);
777 EXPORT_SYMBOL(iSeries_Read_Long
);
780 * Write MM I/O Instructions for the iSeries
782 * iSeries_Write_Byte = Write Byte (8 bit)
783 * iSeries_Write_Word = Write Word(16 bit)
784 * iSeries_Write_Long = Write Long(32 bit)
786 void iSeries_Write_Byte(u8 data
, volatile void __iomem
*IoAddress
)
792 struct device_node
*DevNode
=
793 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
795 if (DevNode
== NULL
) {
796 static unsigned long last_jiffies
;
797 static int num_printed
;
799 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
800 last_jiffies
= jiffies
;
803 if (num_printed
++ < 10)
804 printk(KERN_ERR
"iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress
);
808 ++Pci_Io_Write_Count
;
809 rc
= HvCall4(HvCallPciBarStore8
, dsa
, BarOffset
, data
, 0);
810 } while (CheckReturnCode("WWB", DevNode
, &retry
, rc
) != 0);
812 EXPORT_SYMBOL(iSeries_Write_Byte
);
814 void iSeries_Write_Word(u16 data
, volatile void __iomem
*IoAddress
)
820 struct device_node
*DevNode
=
821 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
823 if (DevNode
== NULL
) {
824 static unsigned long last_jiffies
;
825 static int num_printed
;
827 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
828 last_jiffies
= jiffies
;
831 if (num_printed
++ < 10)
832 printk(KERN_ERR
"iSeries_Write_Word: invalid access at IO address %p\n", IoAddress
);
836 ++Pci_Io_Write_Count
;
837 rc
= HvCall4(HvCallPciBarStore16
, dsa
, BarOffset
, swab16(data
), 0);
838 } while (CheckReturnCode("WWW", DevNode
, &retry
, rc
) != 0);
840 EXPORT_SYMBOL(iSeries_Write_Word
);
842 void iSeries_Write_Long(u32 data
, volatile void __iomem
*IoAddress
)
848 struct device_node
*DevNode
=
849 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
851 if (DevNode
== NULL
) {
852 static unsigned long last_jiffies
;
853 static int num_printed
;
855 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
856 last_jiffies
= jiffies
;
859 if (num_printed
++ < 10)
860 printk(KERN_ERR
"iSeries_Write_Long: invalid access at IO address %p\n", IoAddress
);
864 ++Pci_Io_Write_Count
;
865 rc
= HvCall4(HvCallPciBarStore32
, dsa
, BarOffset
, swab32(data
), 0);
866 } while (CheckReturnCode("WWL", DevNode
, &retry
, rc
) != 0);
868 EXPORT_SYMBOL(iSeries_Write_Long
);