arch/powerpc/platforms/maple/pci.c

   1 /*
   2  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
   3  *                    IBM Corp.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10
  11 #define DEBUG
  12
  13 #include <linux/kernel.h>
  14 #include <linux/pci.h>
  15 #include <linux/delay.h>
  16 #include <linux/string.h>
  17 #include <linux/init.h>
  18 #include <linux/bootmem.h>
  19
  20 #include <asm/sections.h>
  21 #include <asm/io.h>
  22 #include <asm/prom.h>
  23 #include <asm/pci-bridge.h>
  24 #include <asm/machdep.h>
  25 #include <asm/iommu.h>
  26 #include <asm/ppc-pci.h>
  27
  28 #include "maple.h"
  29
  30 #ifdef DEBUG
  31 #define DBG(x...) printk(x)
  32 #else
  33 #define DBG(x...)
  34 #endif
  35
  36 static struct pci_controller *u3_agp, *u3_ht;
  37
  38 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
  39 {
  40         for (; node != 0;node = node->sibling) {
  41                 const int *bus_range;
  42                 const unsigned int *class_code;
  43                 int len;
  44
  45                 /* For PCI<->PCI bridges or CardBus bridges, we go down */
  46                 class_code = get_property(node, "class-code", NULL);
  47                 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
  48                         (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
  49                         continue;
  50                 bus_range = get_property(node, "bus-range", &len);
  51                 if (bus_range != NULL && len > 2 * sizeof(int)) {
  52                         if (bus_range[1] > higher)
  53                                 higher = bus_range[1];
  54                 }
  55                 higher = fixup_one_level_bus_range(node->child, higher);
  56         }
  57         return higher;
  58 }
  59
  60 /* This routine fixes the "bus-range" property of all bridges in the
  61  * system since they tend to have their "last" member wrong on macs
  62  *
  63  * Note that the bus numbers manipulated here are OF bus numbers, they
  64  * are not Linux bus numbers.
  65  */
  66 static void __init fixup_bus_range(struct device_node *bridge)
  67 {
  68         int *bus_range;
  69         struct property *prop;
  70         int len;
  71
  72         /* Lookup the "bus-range" property for the hose */
  73         prop = of_find_property(bridge, "bus-range", &len);
  74         if (prop == NULL  || prop->value == NULL || len < 2 * sizeof(int)) {
  75                 printk(KERN_WARNING "Can't get bus-range for %s\n",
  76                                bridge->full_name);
  77                 return;
  78         }
  79         bus_range = (int *)prop->value;
  80         bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
  81 }
  82
  83
  84 static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
  85 {
  86         return (1 << (unsigned long)PCI_SLOT(devfn)) |
  87                 ((unsigned long)PCI_FUNC(devfn) << 8) |
  88                 ((unsigned long)off & 0xFCUL);
  89 }
  90
  91 static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
  92 {
  93         return ((unsigned long)bus << 16) |
  94                 ((unsigned long)devfn << 8) |
  95                 ((unsigned long)off & 0xFCUL) |
  96                 1UL;
  97 }
  98
  99 static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
 100                                        u8 bus, u8 dev_fn, u8 offset)
 101 {
 102         unsigned int caddr;
 103
 104         if (bus == hose->first_busno) {
 105                 if (dev_fn < (11 << 3))
 106                         return 0;
 107                 caddr = u3_agp_cfa0(dev_fn, offset);
 108         } else
 109                 caddr = u3_agp_cfa1(bus, dev_fn, offset);
 110
 111         /* Uninorth will return garbage if we don't read back the value ! */
 112         do {
 113                 out_le32(hose->cfg_addr, caddr);
 114         } while (in_le32(hose->cfg_addr) != caddr);
 115
 116         offset &= 0x07;
 117         return ((unsigned long)hose->cfg_data) + offset;
 118 }
 119
 120 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
 121                               int offset, int len, u32 *val)
 122 {
 123         struct pci_controller *hose;
 124         unsigned long addr;
 125
 126         hose = pci_bus_to_host(bus);
 127         if (hose == NULL)
 128                 return PCIBIOS_DEVICE_NOT_FOUND;
 129
 130         addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
 131         if (!addr)
 132                 return PCIBIOS_DEVICE_NOT_FOUND;
 133         /*
 134          * Note: the caller has already checked that offset is
 135          * suitably aligned and that len is 1, 2 or 4.
 136          */
 137         switch (len) {
 138         case 1:
 139                 *val = in_8((u8 *)addr);
 140                 break;
 141         case 2:
 142                 *val = in_le16((u16 *)addr);
 143                 break;
 144         default:
 145                 *val = in_le32((u32 *)addr);
 146                 break;
 147         }
 148         return PCIBIOS_SUCCESSFUL;
 149 }
 150
 151 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
 152                                int offset, int len, u32 val)
 153 {
 154         struct pci_controller *hose;
 155         unsigned long addr;
 156
 157         hose = pci_bus_to_host(bus);
 158         if (hose == NULL)
 159                 return PCIBIOS_DEVICE_NOT_FOUND;
 160
 161         addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
 162         if (!addr)
 163                 return PCIBIOS_DEVICE_NOT_FOUND;
 164         /*
 165          * Note: the caller has already checked that offset is
 166          * suitably aligned and that len is 1, 2 or 4.
 167          */
 168         switch (len) {
 169         case 1:
 170                 out_8((u8 *)addr, val);
 171                 (void) in_8((u8 *)addr);
 172                 break;
 173         case 2:
 174                 out_le16((u16 *)addr, val);
 175                 (void) in_le16((u16 *)addr);
 176                 break;
 177         default:
 178                 out_le32((u32 *)addr, val);
 179                 (void) in_le32((u32 *)addr);
 180                 break;
 181         }
 182         return PCIBIOS_SUCCESSFUL;
 183 }
 184
 185 static struct pci_ops u3_agp_pci_ops =
 186 {
 187         u3_agp_read_config,
 188         u3_agp_write_config
 189 };
 190
 191 static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
 192 {
 193         return (devfn << 8) | off;
 194 }
 195
 196 static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
 197 {
 198         return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
 199 }
 200
 201 static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
 202                                       u8 bus, u8 devfn, u8 offset)
 203 {
 204         if (bus == hose->first_busno) {
 205                 if (PCI_SLOT(devfn) == 0)
 206                         return 0;
 207                 return ((unsigned long)hose->cfg_data) + u3_ht_cfa0(devfn, offset);
 208         } else
 209                 return ((unsigned long)hose->cfg_data) + u3_ht_cfa1(bus, devfn, offset);
 210 }
 211
 212 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
 213                              int offset, int len, u32 *val)
 214 {
 215         struct pci_controller *hose;
 216         unsigned long addr;
 217
 218         hose = pci_bus_to_host(bus);
 219         if (hose == NULL)
 220                 return PCIBIOS_DEVICE_NOT_FOUND;
 221
 222         if (offset > 0xff)
 223                 return PCIBIOS_BAD_REGISTER_NUMBER;
 224
 225         addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
 226         if (!addr)
 227                 return PCIBIOS_DEVICE_NOT_FOUND;
 228
 229         /*
 230          * Note: the caller has already checked that offset is
 231          * suitably aligned and that len is 1, 2 or 4.
 232          */
 233         switch (len) {
 234         case 1:
 235                 *val = in_8((u8 *)addr);
 236                 break;
 237         case 2:
 238                 *val = in_le16((u16 *)addr);
 239                 break;
 240         default:
 241                 *val = in_le32((u32 *)addr);
 242                 break;
 243         }
 244         return PCIBIOS_SUCCESSFUL;
 245 }
 246
 247 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
 248                               int offset, int len, u32 val)
 249 {
 250         struct pci_controller *hose;
 251         unsigned long addr;
 252
 253         hose = pci_bus_to_host(bus);
 254         if (hose == NULL)
 255                 return PCIBIOS_DEVICE_NOT_FOUND;
 256
 257         if (offset > 0xff)
 258                 return PCIBIOS_BAD_REGISTER_NUMBER;
 259
 260         addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
 261         if (!addr)
 262                 return PCIBIOS_DEVICE_NOT_FOUND;
 263         /*
 264          * Note: the caller has already checked that offset is
 265          * suitably aligned and that len is 1, 2 or 4.
 266          */
 267         switch (len) {
 268         case 1:
 269                 out_8((u8 *)addr, val);
 270                 (void) in_8((u8 *)addr);
 271                 break;
 272         case 2:
 273                 out_le16((u16 *)addr, val);
 274                 (void) in_le16((u16 *)addr);
 275                 break;
 276         default:
 277                 out_le32((u32 *)addr, val);
 278                 (void) in_le32((u32 *)addr);
 279                 break;
 280         }
 281         return PCIBIOS_SUCCESSFUL;
 282 }
 283
 284 static struct pci_ops u3_ht_pci_ops =
 285 {
 286         u3_ht_read_config,
 287         u3_ht_write_config
 288 };
 289
 290 static void __init setup_u3_agp(struct pci_controller* hose)
 291 {
 292         /* On G5, we move AGP up to high bus number so we don't need
 293          * to reassign bus numbers for HT. If we ever have P2P bridges
 294          * on AGP, we'll have to move pci_assign_all_buses to the
 295          * pci_controller structure so we enable it for AGP and not for
 296          * HT childs.
 297          * We hard code the address because of the different size of
 298          * the reg address cell, we shall fix that by killing struct
 299          * reg_property and using some accessor functions instead
 300          */
 301         hose->first_busno = 0xf0;
 302         hose->last_busno = 0xff;
 303         hose->ops = &u3_agp_pci_ops;
 304         hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
 305         hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
 306
 307         u3_agp = hose;
 308 }
 309
 310 static void __init setup_u3_ht(struct pci_controller* hose)
 311 {
 312         hose->ops = &u3_ht_pci_ops;
 313
 314         /* We hard code the address because of the different size of
 315          * the reg address cell, we shall fix that by killing struct
 316          * reg_property and using some accessor functions instead
 317          */
 318         hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
 319
 320         hose->first_busno = 0;
 321         hose->last_busno = 0xef;
 322
 323         u3_ht = hose;
 324 }
 325
 326 static int __init add_bridge(struct device_node *dev)
 327 {
 328         int len;
 329         struct pci_controller *hose;
 330         char* disp_name;
 331         const int *bus_range;
 332         int primary = 1;
 333
 334         DBG("Adding PCI host bridge %s\n", dev->full_name);
 335
 336         bus_range = get_property(dev, "bus-range", &len);
 337         if (bus_range == NULL || len < 2 * sizeof(int)) {
 338                 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
 339                 dev->full_name);
 340         }
 341
 342         hose = pcibios_alloc_controller(dev);
 343         if (hose == NULL)
 344                 return -ENOMEM;
 345         hose->first_busno = bus_range ? bus_range[0] : 0;
 346         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 347
 348         disp_name = NULL;
 349         if (device_is_compatible(dev, "u3-agp")) {
 350                 setup_u3_agp(hose);
 351                 disp_name = "U3-AGP";
 352                 primary = 0;
 353         } else if (device_is_compatible(dev, "u3-ht")) {
 354                 setup_u3_ht(hose);
 355                 disp_name = "U3-HT";
 356                 primary = 1;
 357         }
 358         printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
 359                 disp_name, hose->first_busno, hose->last_busno);
 360
 361         /* Interpret the "ranges" property */
 362         /* This also maps the I/O region and sets isa_io/mem_base */
 363         pci_process_bridge_OF_ranges(hose, dev, primary);
 364         pci_setup_phb_io(hose, primary);
 365
 366         /* Fixup "bus-range" OF property */
 367         fixup_bus_range(dev);
 368
 369         return 0;
 370 }
 371
 372
 373 void __init maple_pcibios_fixup(void)
 374 {
 375         struct pci_dev *dev = NULL;
 376
 377         DBG(" -> maple_pcibios_fixup\n");
 378
 379         for_each_pci_dev(dev)
 380                 pci_read_irq_line(dev);
 381
 382         DBG(" <- maple_pcibios_fixup\n");
 383 }
 384
 385 static void __init maple_fixup_phb_resources(void)
 386 {
 387         struct pci_controller *hose, *tmp;
 388
 389         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 390                 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
 391                 hose->io_resource.start += offset;
 392                 hose->io_resource.end += offset;
 393                 printk(KERN_INFO "PCI Host %d, io start: %llx; io end: %llx\n",
 394                        hose->global_number,
 395                        (unsigned long long)hose->io_resource.start,
 396                        (unsigned long long)hose->io_resource.end);
 397         }
 398 }
 399
 400 void __init maple_pci_init(void)
 401 {
 402         struct device_node *np, *root;
 403         struct device_node *ht = NULL;
 404
 405         /* Probe root PCI hosts, that is on U3 the AGP host and the
 406          * HyperTransport host. That one is actually "kept" around
 407          * and actually added last as it's resource management relies
 408          * on the AGP resources to have been setup first
 409          */
 410         root = of_find_node_by_path("/");
 411         if (root == NULL) {
 412                 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
 413                 return;
 414         }
 415         for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
 416                 if (np->name == NULL)
 417                         continue;
 418                 if (strcmp(np->name, "pci") == 0) {
 419                         if (add_bridge(np) == 0)
 420                                 of_node_get(np);
 421                 }
 422                 if (strcmp(np->name, "ht") == 0) {
 423                         of_node_get(np);
 424                         ht = np;
 425                 }
 426         }
 427         of_node_put(root);
 428
 429         /* Now setup the HyperTransport host if we found any
 430          */
 431         if (ht && add_bridge(ht) != 0)
 432                 of_node_put(ht);
 433
 434         /* Fixup the IO resources on our host bridges as the common code
 435          * does it only for childs of the host bridges
 436          */
 437         maple_fixup_phb_resources();
 438
 439         /* Setup the linkage between OF nodes and PHBs */
 440         pci_devs_phb_init();
 441
 442         /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
 443          * assume there is no P2P bridge on the AGP bus, which should be a
 444          * safe assumptions hopefully.
 445          */
 446         if (u3_agp) {
 447                 struct device_node *np = u3_agp->arch_data;
 448                 PCI_DN(np)->busno = 0xf0;
 449                 for (np = np->child; np; np = np->sibling)
 450                         PCI_DN(np)->busno = 0xf0;
 451         }
 452
 453         /* Tell pci.c to not change any resource allocations.  */
 454         pci_probe_only = 1;
 455 }
 456
 457 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
 458 {
 459         struct device_node *np;
 460         unsigned int defirq = channel ? 15 : 14;
 461         unsigned int irq;
 462
 463         if (pdev->vendor != PCI_VENDOR_ID_AMD ||
 464             pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
 465                 return defirq;
 466
 467         np = pci_device_to_OF_node(pdev);
 468         if (np == NULL)
 469                 return defirq;
 470         irq = irq_of_parse_and_map(np, channel & 0x1);
 471         if (irq == NO_IRQ) {
 472                 printk("Failed to map onboard IDE interrupt for channel %d\n",
 473                        channel);
 474                 return defirq;
 475         }
 476         return irq;
 477 }
 478
 479 /* XXX: To remove once all firmwares are ok */
 480 static void fixup_maple_ide(struct pci_dev* dev)
 481 {
 482 #if 0 /* Enable this to enable IDE port 0 */
 483         {
 484                 u8 v;
 485
 486                 pci_read_config_byte(dev, 0x40, &v);
 487                 v |= 2;
 488                 pci_write_config_byte(dev, 0x40, v);
 489         }
 490 #endif
 491 #if 0 /* fix bus master base */
 492         pci_write_config_dword(dev, 0x20, 0xcc01);
 493         printk("old ide resource: %lx -> %lx \n",
 494                dev->resource[4].start, dev->resource[4].end);
 495         dev->resource[4].start = 0xcc00;
 496         dev->resource[4].end = 0xcc10;
 497 #endif
 498 #if 1 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
 499         {
 500                 struct pci_dev *apicdev;
 501                 u32 v;
 502
 503                 apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0));
 504                 if (apicdev == NULL)
 505                         printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
 506                 else {
 507                         pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14);
 508                         pci_read_config_dword(apicdev, 0xf4, &v);
 509                         v &= ~0x00000022;
 510                         pci_write_config_dword(apicdev, 0xf4, v);
 511                         pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15);
 512                         pci_read_config_dword(apicdev, 0xf4, &v);
 513                         v &= ~0x00000022;
 514                         pci_write_config_dword(apicdev, 0xf4, v);
 515                         pci_dev_put(apicdev);
 516                 }
 517         }
 518 #endif
 519 }
 520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE,
 521                          fixup_maple_ide);