arch/powerpc/platforms/maple/pci.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
   4  *                    IBM Corp.
   5  */
   6
   7 #undef DEBUG
   8
   9 #include <linux/kernel.h>
  10 #include <linux/pci.h>
  11 #include <linux/delay.h>
  12 #include <linux/string.h>
  13 #include <linux/init.h>
  14 #include <linux/irq.h>
  15
  16 #include <asm/sections.h>
  17 #include <asm/io.h>
  18 #include <asm/prom.h>
  19 #include <asm/pci-bridge.h>
  20 #include <asm/machdep.h>
  21 #include <asm/iommu.h>
  22 #include <asm/ppc-pci.h>
  23 #include <asm/isa-bridge.h>
  24
  25 #include "maple.h"
  26
  27 #ifdef DEBUG
  28 #define DBG(x...) printk(x)
  29 #else
  30 #define DBG(x...)
  31 #endif
  32
  33 static struct pci_controller *u3_agp, *u3_ht, *u4_pcie;
  34
  35 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
  36 {
  37         for (; node != 0;node = node->sibling) {
  38                 const int *bus_range;
  39                 const unsigned int *class_code;
  40                 int len;
  41
  42                 /* For PCI<->PCI bridges or CardBus bridges, we go down */
  43                 class_code = of_get_property(node, "class-code", NULL);
  44                 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
  45                         (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
  46                         continue;
  47                 bus_range = of_get_property(node, "bus-range", &len);
  48                 if (bus_range != NULL && len > 2 * sizeof(int)) {
  49                         if (bus_range[1] > higher)
  50                                 higher = bus_range[1];
  51                 }
  52                 higher = fixup_one_level_bus_range(node->child, higher);
  53         }
  54         return higher;
  55 }
  56
  57 /* This routine fixes the "bus-range" property of all bridges in the
  58  * system since they tend to have their "last" member wrong on macs
  59  *
  60  * Note that the bus numbers manipulated here are OF bus numbers, they
  61  * are not Linux bus numbers.
  62  */
  63 static void __init fixup_bus_range(struct device_node *bridge)
  64 {
  65         int *bus_range;
  66         struct property *prop;
  67         int len;
  68
  69         /* Lookup the "bus-range" property for the hose */
  70         prop = of_find_property(bridge, "bus-range", &len);
  71         if (prop == NULL  || prop->value == NULL || len < 2 * sizeof(int)) {
  72                 printk(KERN_WARNING "Can't get bus-range for %pOF\n",
  73                                bridge);
  74                 return;
  75         }
  76         bus_range = prop->value;
  77         bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
  78 }
  79
  80
  81 static unsigned long u3_agp_cfa0(u8 devfn, u8 off)
  82 {
  83         return (1 << (unsigned long)PCI_SLOT(devfn)) |
  84                 ((unsigned long)PCI_FUNC(devfn) << 8) |
  85                 ((unsigned long)off & 0xFCUL);
  86 }
  87
  88 static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off)
  89 {
  90         return ((unsigned long)bus << 16) |
  91                 ((unsigned long)devfn << 8) |
  92                 ((unsigned long)off & 0xFCUL) |
  93                 1UL;
  94 }
  95
  96 static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose,
  97                                        u8 bus, u8 dev_fn, u8 offset)
  98 {
  99         unsigned int caddr;
 100
 101         if (bus == hose->first_busno) {
 102                 if (dev_fn < (11 << 3))
 103                         return NULL;
 104                 caddr = u3_agp_cfa0(dev_fn, offset);
 105         } else
 106                 caddr = u3_agp_cfa1(bus, dev_fn, offset);
 107
 108         /* Uninorth will return garbage if we don't read back the value ! */
 109         do {
 110                 out_le32(hose->cfg_addr, caddr);
 111         } while (in_le32(hose->cfg_addr) != caddr);
 112
 113         offset &= 0x07;
 114         return hose->cfg_data + offset;
 115 }
 116
 117 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
 118                               int offset, int len, u32 *val)
 119 {
 120         struct pci_controller *hose;
 121         volatile void __iomem *addr;
 122
 123         hose = pci_bus_to_host(bus);
 124         if (hose == NULL)
 125                 return PCIBIOS_DEVICE_NOT_FOUND;
 126
 127         addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
 128         if (!addr)
 129                 return PCIBIOS_DEVICE_NOT_FOUND;
 130         /*
 131          * Note: the caller has already checked that offset is
 132          * suitably aligned and that len is 1, 2 or 4.
 133          */
 134         switch (len) {
 135         case 1:
 136                 *val = in_8(addr);
 137                 break;
 138         case 2:
 139                 *val = in_le16(addr);
 140                 break;
 141         default:
 142                 *val = in_le32(addr);
 143                 break;
 144         }
 145         return PCIBIOS_SUCCESSFUL;
 146 }
 147
 148 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
 149                                int offset, int len, u32 val)
 150 {
 151         struct pci_controller *hose;
 152         volatile void __iomem *addr;
 153
 154         hose = pci_bus_to_host(bus);
 155         if (hose == NULL)
 156                 return PCIBIOS_DEVICE_NOT_FOUND;
 157
 158         addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
 159         if (!addr)
 160                 return PCIBIOS_DEVICE_NOT_FOUND;
 161         /*
 162          * Note: the caller has already checked that offset is
 163          * suitably aligned and that len is 1, 2 or 4.
 164          */
 165         switch (len) {
 166         case 1:
 167                 out_8(addr, val);
 168                 break;
 169         case 2:
 170                 out_le16(addr, val);
 171                 break;
 172         default:
 173                 out_le32(addr, val);
 174                 break;
 175         }
 176         return PCIBIOS_SUCCESSFUL;
 177 }
 178
 179 static struct pci_ops u3_agp_pci_ops =
 180 {
 181         .read = u3_agp_read_config,
 182         .write = u3_agp_write_config,
 183 };
 184
 185 static unsigned long u3_ht_cfa0(u8 devfn, u8 off)
 186 {
 187         return (devfn << 8) | off;
 188 }
 189
 190 static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off)
 191 {
 192         return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL;
 193 }
 194
 195 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
 196                                       u8 bus, u8 devfn, u8 offset)
 197 {
 198         if (bus == hose->first_busno) {
 199                 if (PCI_SLOT(devfn) == 0)
 200                         return NULL;
 201                 return hose->cfg_data + u3_ht_cfa0(devfn, offset);
 202         } else
 203                 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset);
 204 }
 205
 206 static int u3_ht_root_read_config(struct pci_controller *hose, u8 offset,
 207                                   int len, u32 *val)
 208 {
 209         volatile void __iomem *addr;
 210
 211         addr = hose->cfg_addr;
 212         addr += ((offset & ~3) << 2) + (4 - len - (offset & 3));
 213
 214         switch (len) {
 215         case 1:
 216                 *val = in_8(addr);
 217                 break;
 218         case 2:
 219                 *val = in_be16(addr);
 220                 break;
 221         default:
 222                 *val = in_be32(addr);
 223                 break;
 224         }
 225
 226         return PCIBIOS_SUCCESSFUL;
 227 }
 228
 229 static int u3_ht_root_write_config(struct pci_controller *hose, u8 offset,
 230                                   int len, u32 val)
 231 {
 232         volatile void __iomem *addr;
 233
 234         addr = hose->cfg_addr + ((offset & ~3) << 2) + (4 - len - (offset & 3));
 235
 236         if (offset >= PCI_BASE_ADDRESS_0 && offset < PCI_CAPABILITY_LIST)
 237                 return PCIBIOS_SUCCESSFUL;
 238
 239         switch (len) {
 240         case 1:
 241                 out_8(addr, val);
 242                 break;
 243         case 2:
 244                 out_be16(addr, val);
 245                 break;
 246         default:
 247                 out_be32(addr, val);
 248                 break;
 249         }
 250
 251         return PCIBIOS_SUCCESSFUL;
 252 }
 253
 254 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
 255                              int offset, int len, u32 *val)
 256 {
 257         struct pci_controller *hose;
 258         volatile void __iomem *addr;
 259
 260         hose = pci_bus_to_host(bus);
 261         if (hose == NULL)
 262                 return PCIBIOS_DEVICE_NOT_FOUND;
 263
 264         if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
 265                 return u3_ht_root_read_config(hose, offset, len, val);
 266
 267         if (offset > 0xff)
 268                 return PCIBIOS_BAD_REGISTER_NUMBER;
 269
 270         addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
 271         if (!addr)
 272                 return PCIBIOS_DEVICE_NOT_FOUND;
 273
 274         /*
 275          * Note: the caller has already checked that offset is
 276          * suitably aligned and that len is 1, 2 or 4.
 277          */
 278         switch (len) {
 279         case 1:
 280                 *val = in_8(addr);
 281                 break;
 282         case 2:
 283                 *val = in_le16(addr);
 284                 break;
 285         default:
 286                 *val = in_le32(addr);
 287                 break;
 288         }
 289         return PCIBIOS_SUCCESSFUL;
 290 }
 291
 292 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
 293                               int offset, int len, u32 val)
 294 {
 295         struct pci_controller *hose;
 296         volatile void __iomem *addr;
 297
 298         hose = pci_bus_to_host(bus);
 299         if (hose == NULL)
 300                 return PCIBIOS_DEVICE_NOT_FOUND;
 301
 302         if (bus->number == hose->first_busno && devfn == PCI_DEVFN(0, 0))
 303                 return u3_ht_root_write_config(hose, offset, len, val);
 304
 305         if (offset > 0xff)
 306                 return PCIBIOS_BAD_REGISTER_NUMBER;
 307
 308         addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
 309         if (!addr)
 310                 return PCIBIOS_DEVICE_NOT_FOUND;
 311         /*
 312          * Note: the caller has already checked that offset is
 313          * suitably aligned and that len is 1, 2 or 4.
 314          */
 315         switch (len) {
 316         case 1:
 317                 out_8(addr, val);
 318                 break;
 319         case 2:
 320                 out_le16(addr, val);
 321                 break;
 322         default:
 323                 out_le32(addr, val);
 324                 break;
 325         }
 326         return PCIBIOS_SUCCESSFUL;
 327 }
 328
 329 static struct pci_ops u3_ht_pci_ops =
 330 {
 331         .read = u3_ht_read_config,
 332         .write = u3_ht_write_config,
 333 };
 334
 335 static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off)
 336 {
 337         return (1 << PCI_SLOT(devfn))   |
 338                (PCI_FUNC(devfn) << 8)   |
 339                ((off >> 8) << 28)       |
 340                (off & 0xfcu);
 341 }
 342
 343 static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn,
 344                                  unsigned int off)
 345 {
 346         return (bus << 16)              |
 347                (devfn << 8)             |
 348                ((off >> 8) << 28)       |
 349                (off & 0xfcu)            | 1u;
 350 }
 351
 352 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
 353                                         u8 bus, u8 dev_fn, int offset)
 354 {
 355         unsigned int caddr;
 356
 357         if (bus == hose->first_busno)
 358                 caddr = u4_pcie_cfa0(dev_fn, offset);
 359         else
 360                 caddr = u4_pcie_cfa1(bus, dev_fn, offset);
 361
 362         /* Uninorth will return garbage if we don't read back the value ! */
 363         do {
 364                 out_le32(hose->cfg_addr, caddr);
 365         } while (in_le32(hose->cfg_addr) != caddr);
 366
 367         offset &= 0x03;
 368         return hose->cfg_data + offset;
 369 }
 370
 371 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
 372                                int offset, int len, u32 *val)
 373 {
 374         struct pci_controller *hose;
 375         volatile void __iomem *addr;
 376
 377         hose = pci_bus_to_host(bus);
 378         if (hose == NULL)
 379                 return PCIBIOS_DEVICE_NOT_FOUND;
 380         if (offset >= 0x1000)
 381                 return  PCIBIOS_BAD_REGISTER_NUMBER;
 382         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
 383         if (!addr)
 384                 return PCIBIOS_DEVICE_NOT_FOUND;
 385         /*
 386          * Note: the caller has already checked that offset is
 387          * suitably aligned and that len is 1, 2 or 4.
 388          */
 389         switch (len) {
 390         case 1:
 391                 *val = in_8(addr);
 392                 break;
 393         case 2:
 394                 *val = in_le16(addr);
 395                 break;
 396         default:
 397                 *val = in_le32(addr);
 398                 break;
 399         }
 400         return PCIBIOS_SUCCESSFUL;
 401 }
 402 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
 403                                 int offset, int len, u32 val)
 404 {
 405         struct pci_controller *hose;
 406         volatile void __iomem *addr;
 407
 408         hose = pci_bus_to_host(bus);
 409         if (hose == NULL)
 410                 return PCIBIOS_DEVICE_NOT_FOUND;
 411         if (offset >= 0x1000)
 412                 return  PCIBIOS_BAD_REGISTER_NUMBER;
 413         addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset);
 414         if (!addr)
 415                 return PCIBIOS_DEVICE_NOT_FOUND;
 416         /*
 417          * Note: the caller has already checked that offset is
 418          * suitably aligned and that len is 1, 2 or 4.
 419          */
 420         switch (len) {
 421         case 1:
 422                 out_8(addr, val);
 423                 break;
 424         case 2:
 425                 out_le16(addr, val);
 426                 break;
 427         default:
 428                 out_le32(addr, val);
 429                 break;
 430         }
 431         return PCIBIOS_SUCCESSFUL;
 432 }
 433
 434 static struct pci_ops u4_pcie_pci_ops =
 435 {
 436         .read = u4_pcie_read_config,
 437         .write = u4_pcie_write_config,
 438 };
 439
 440 static void __init setup_u3_agp(struct pci_controller* hose)
 441 {
 442         /* On G5, we move AGP up to high bus number so we don't need
 443          * to reassign bus numbers for HT. If we ever have P2P bridges
 444          * on AGP, we'll have to move pci_assign_all_buses to the
 445          * pci_controller structure so we enable it for AGP and not for
 446          * HT childs.
 447          * We hard code the address because of the different size of
 448          * the reg address cell, we shall fix that by killing struct
 449          * reg_property and using some accessor functions instead
 450          */
 451         hose->first_busno = 0xf0;
 452         hose->last_busno = 0xff;
 453         hose->ops = &u3_agp_pci_ops;
 454         hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
 455         hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
 456
 457         u3_agp = hose;
 458 }
 459
 460 static void __init setup_u4_pcie(struct pci_controller* hose)
 461 {
 462         /* We currently only implement the "non-atomic" config space, to
 463          * be optimised later.
 464          */
 465         hose->ops = &u4_pcie_pci_ops;
 466         hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
 467         hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
 468
 469         u4_pcie = hose;
 470 }
 471
 472 static void __init setup_u3_ht(struct pci_controller* hose)
 473 {
 474         hose->ops = &u3_ht_pci_ops;
 475
 476         /* We hard code the address because of the different size of
 477          * the reg address cell, we shall fix that by killing struct
 478          * reg_property and using some accessor functions instead
 479          */
 480         hose->cfg_data = ioremap(0xf2000000, 0x02000000);
 481         hose->cfg_addr = ioremap(0xf8070000, 0x1000);
 482
 483         hose->first_busno = 0;
 484         hose->last_busno = 0xef;
 485
 486         u3_ht = hose;
 487 }
 488
 489 static int __init maple_add_bridge(struct device_node *dev)
 490 {
 491         int len;
 492         struct pci_controller *hose;
 493         char* disp_name;
 494         const int *bus_range;
 495         int primary = 1;
 496
 497         DBG("Adding PCI host bridge %pOF\n", dev);
 498
 499         bus_range = of_get_property(dev, "bus-range", &len);
 500         if (bus_range == NULL || len < 2 * sizeof(int)) {
 501                 printk(KERN_WARNING "Can't get bus-range for %pOF, assume bus 0\n",
 502                 dev);
 503         }
 504
 505         hose = pcibios_alloc_controller(dev);
 506         if (hose == NULL)
 507                 return -ENOMEM;
 508         hose->first_busno = bus_range ? bus_range[0] : 0;
 509         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 510         hose->controller_ops = maple_pci_controller_ops;
 511
 512         disp_name = NULL;
 513         if (of_device_is_compatible(dev, "u3-agp")) {
 514                 setup_u3_agp(hose);
 515                 disp_name = "U3-AGP";
 516                 primary = 0;
 517         } else if (of_device_is_compatible(dev, "u3-ht")) {
 518                 setup_u3_ht(hose);
 519                 disp_name = "U3-HT";
 520                 primary = 1;
 521         } else if (of_device_is_compatible(dev, "u4-pcie")) {
 522                 setup_u4_pcie(hose);
 523                 disp_name = "U4-PCIE";
 524                 primary = 0;
 525         }
 526         printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
 527                 disp_name, hose->first_busno, hose->last_busno);
 528
 529         /* Interpret the "ranges" property */
 530         /* This also maps the I/O region and sets isa_io/mem_base */
 531         pci_process_bridge_OF_ranges(hose, dev, primary);
 532
 533         /* Fixup "bus-range" OF property */
 534         fixup_bus_range(dev);
 535
 536         /* Check for legacy IOs */
 537         isa_bridge_find_early(hose);
 538
 539         return 0;
 540 }
 541
 542
 543 void maple_pci_irq_fixup(struct pci_dev *dev)
 544 {
 545         DBG(" -> maple_pci_irq_fixup\n");
 546
 547         /* Fixup IRQ for PCIe host */
 548         if (u4_pcie != NULL && dev->bus->number == 0 &&
 549             pci_bus_to_host(dev->bus) == u4_pcie) {
 550                 printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
 551                 dev->irq = irq_create_mapping(NULL, 1);
 552                 if (dev->irq)
 553                         irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
 554         }
 555
 556         /* Hide AMD8111 IDE interrupt when in legacy mode so
 557          * the driver calls pci_get_legacy_ide_irq()
 558          */
 559         if (dev->vendor == PCI_VENDOR_ID_AMD &&
 560             dev->device == PCI_DEVICE_ID_AMD_8111_IDE &&
 561             (dev->class & 5) != 5) {
 562                 dev->irq = 0;
 563         }
 564
 565         DBG(" <- maple_pci_irq_fixup\n");
 566 }
 567
 568 static int maple_pci_root_bridge_prepare(struct pci_host_bridge *bridge)
 569 {
 570         struct pci_controller *hose = pci_bus_to_host(bridge->bus);
 571         struct device_node *np, *child;
 572
 573         if (hose != u3_agp)
 574                 return 0;
 575
 576         /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
 577          * assume there is no P2P bridge on the AGP bus, which should be a
 578          * safe assumptions hopefully.
 579          */
 580         np = hose->dn;
 581         PCI_DN(np)->busno = 0xf0;
 582         for_each_child_of_node(np, child)
 583                 PCI_DN(child)->busno = 0xf0;
 584
 585         return 0;
 586 }
 587
 588 void __init maple_pci_init(void)
 589 {
 590         struct device_node *np, *root;
 591         struct device_node *ht = NULL;
 592
 593         /* Probe root PCI hosts, that is on U3 the AGP host and the
 594          * HyperTransport host. That one is actually "kept" around
 595          * and actually added last as it's resource management relies
 596          * on the AGP resources to have been setup first
 597          */
 598         root = of_find_node_by_path("/");
 599         if (root == NULL) {
 600                 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
 601                 return;
 602         }
 603         for_each_child_of_node(root, np) {
 604                 if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "ht"))
 605                         continue;
 606                 if ((of_device_is_compatible(np, "u4-pcie") ||
 607                      of_device_is_compatible(np, "u3-agp")) &&
 608                     maple_add_bridge(np) == 0)
 609                         of_node_get(np);
 610
 611                 if (of_device_is_compatible(np, "u3-ht")) {
 612                         of_node_get(np);
 613                         ht = np;
 614                 }
 615         }
 616         of_node_put(root);
 617
 618         /* Now setup the HyperTransport host if we found any
 619          */
 620         if (ht && maple_add_bridge(ht) != 0)
 621                 of_node_put(ht);
 622
 623         ppc_md.pcibios_root_bridge_prepare = maple_pci_root_bridge_prepare;
 624
 625         /* Tell pci.c to not change any resource allocations.  */
 626         pci_add_flags(PCI_PROBE_ONLY);
 627 }
 628
 629 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
 630 {
 631         struct device_node *np;
 632         unsigned int defirq = channel ? 15 : 14;
 633         unsigned int irq;
 634
 635         if (pdev->vendor != PCI_VENDOR_ID_AMD ||
 636             pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
 637                 return defirq;
 638
 639         np = pci_device_to_OF_node(pdev);
 640         if (np == NULL) {
 641                 printk("Failed to locate OF node for IDE %s\n",
 642                        pci_name(pdev));
 643                 return defirq;
 644         }
 645         irq = irq_of_parse_and_map(np, channel & 0x1);
 646         if (!irq) {
 647                 printk("Failed to map onboard IDE interrupt for channel %d\n",
 648                        channel);
 649                 return defirq;
 650         }
 651         return irq;
 652 }
 653
 654 static void quirk_ipr_msi(struct pci_dev *dev)
 655 {
 656         /* Something prevents MSIs from the IPR from working on Bimini,
 657          * and the driver has no smarts to recover. So disable MSI
 658          * on it for now. */
 659
 660         if (machine_is(maple)) {
 661                 dev->no_msi = 1;
 662                 dev_info(&dev->dev, "Quirk disabled MSI\n");
 663         }
 664 }
 665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
 666                         quirk_ipr_msi);
 667
 668 struct pci_controller_ops maple_pci_controller_ops = {
 669 };