arch/powerpc/platforms/maple/pci.c

   1 /*
   2  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
   3  *                    IBM Corp.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version
   8  * 2 of the License, or (at your option) any later version.
   9  */
  10
  11 #define DEBUG
  12
  13 #include <linux/kernel.h>
  14 #include <linux/pci.h>
  15 #include <linux/delay.h>
  16 #include <linux/string.h>
  17 #include <linux/init.h>
  18 #include <linux/bootmem.h>
  19
  20 #include <asm/sections.h>
  21 #include <asm/io.h>
  22 #include <asm/prom.h>
  23 #include <asm/pci-bridge.h>
  24 #include <asm/machdep.h>
  25 #include <asm/iommu.h>
  26 #include <asm/ppc-pci.h>
  27
  28 #include "maple.h"
  29
  30 #ifdef DEBUG
  31 #define DBG(x...) printk(x)
  32 #else
  33 #define DBG(x...)
  34 #endif
  35
  36 static struct pci_controller *u3_agp, *u3_ht;
  37
  38 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
  39 {
  40         for (; node != 0;node = node->sibling) {
  41                 int * bus_range;
  42                 unsigned int *class_code;
  43                 int len;
  44
  45                 /* For PCI<->PCI bridges or CardBus bridges, we go down */
  46                 class_code = (unsigned int *) get_property(node, "class-code", NULL);
  47                 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
  48                         (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
  49                         continue;
  50                 bus_range = (int *) get_property(node, "bus-range", &len);
  51                 if (bus_range != NULL && len > 2 * sizeof(int)) {
  52                         if (bus_range[1] > higher)
  53                                 higher = bus_range[1];
  54                 }
  55                 higher = fixup_one_level_bus_range(node->child, higher);
  56         }
  57         return higher;
  58 }
  59
  60 /* This routine fixes the "bus-range" property of all bridges in the
  61  * system since they tend to have their "last" member wrong on macs
  62  *
  63  * Note that the bus numbers manipulated here are OF bus numbers, they
  64  * are not Linux bus numbers.
  65  */
  66 static void __init fixup_bus_range(struct device_node *bridge)
  67 {
  68         int * bus_range;
  69         int len;
  70
  71         /* Lookup the "bus-range" property for the hose */
  72         bus_range = (int *) get_property(bridge, "bus-range", &len);
  73         if (bus_range == NULL || len < 2 * sizeof(int)) {
  74                 printk(KERN_WARNING "Can't get bus-range for %s\n",
  75                                bridge->full_name);
  76                 return;
  77         }
  78         bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
  79 }
  80
  81
  82 #define U3_AGP_CFA0(devfn, off) \
  83         ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
  84         | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
  85         | (((unsigned long)(off)) & 0xFCUL))
  86
  87 #define U3_AGP_CFA1(bus, devfn, off)    \
  88         ((((unsigned long)(bus)) << 16) \
  89         |(((unsigned long)(devfn)) << 8) \
  90         |(((unsigned long)(off)) & 0xFCUL) \
  91         |1UL)
  92
  93 static unsigned long u3_agp_cfg_access(struct pci_controller* hose,
  94                                        u8 bus, u8 dev_fn, u8 offset)
  95 {
  96         unsigned int caddr;
  97
  98         if (bus == hose->first_busno) {
  99                 if (dev_fn < (11 << 3))
 100                         return 0;
 101                 caddr = U3_AGP_CFA0(dev_fn, offset);
 102         } else
 103                 caddr = U3_AGP_CFA1(bus, dev_fn, offset);
 104
 105         /* Uninorth will return garbage if we don't read back the value ! */
 106         do {
 107                 out_le32(hose->cfg_addr, caddr);
 108         } while (in_le32(hose->cfg_addr) != caddr);
 109
 110         offset &= 0x07;
 111         return ((unsigned long)hose->cfg_data) + offset;
 112 }
 113
 114 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn,
 115                               int offset, int len, u32 *val)
 116 {
 117         struct pci_controller *hose;
 118         unsigned long addr;
 119
 120         hose = pci_bus_to_host(bus);
 121         if (hose == NULL)
 122                 return PCIBIOS_DEVICE_NOT_FOUND;
 123
 124         addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
 125         if (!addr)
 126                 return PCIBIOS_DEVICE_NOT_FOUND;
 127         /*
 128          * Note: the caller has already checked that offset is
 129          * suitably aligned and that len is 1, 2 or 4.
 130          */
 131         switch (len) {
 132         case 1:
 133                 *val = in_8((u8 *)addr);
 134                 break;
 135         case 2:
 136                 *val = in_le16((u16 *)addr);
 137                 break;
 138         default:
 139                 *val = in_le32((u32 *)addr);
 140                 break;
 141         }
 142         return PCIBIOS_SUCCESSFUL;
 143 }
 144
 145 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn,
 146                                int offset, int len, u32 val)
 147 {
 148         struct pci_controller *hose;
 149         unsigned long addr;
 150
 151         hose = pci_bus_to_host(bus);
 152         if (hose == NULL)
 153                 return PCIBIOS_DEVICE_NOT_FOUND;
 154
 155         addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
 156         if (!addr)
 157                 return PCIBIOS_DEVICE_NOT_FOUND;
 158         /*
 159          * Note: the caller has already checked that offset is
 160          * suitably aligned and that len is 1, 2 or 4.
 161          */
 162         switch (len) {
 163         case 1:
 164                 out_8((u8 *)addr, val);
 165                 (void) in_8((u8 *)addr);
 166                 break;
 167         case 2:
 168                 out_le16((u16 *)addr, val);
 169                 (void) in_le16((u16 *)addr);
 170                 break;
 171         default:
 172                 out_le32((u32 *)addr, val);
 173                 (void) in_le32((u32 *)addr);
 174                 break;
 175         }
 176         return PCIBIOS_SUCCESSFUL;
 177 }
 178
 179 static struct pci_ops u3_agp_pci_ops =
 180 {
 181         u3_agp_read_config,
 182         u3_agp_write_config
 183 };
 184
 185
 186 #define U3_HT_CFA0(devfn, off)          \
 187                 ((((unsigned long)devfn) << 8) | offset)
 188 #define U3_HT_CFA1(bus, devfn, off)     \
 189                 (U3_HT_CFA0(devfn, off) \
 190                 + (((unsigned long)bus) << 16) \
 191                 + 0x01000000UL)
 192
 193 static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
 194                                       u8 bus, u8 devfn, u8 offset)
 195 {
 196         if (bus == hose->first_busno) {
 197                 if (PCI_SLOT(devfn) == 0)
 198                         return 0;
 199                 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
 200         } else
 201                 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
 202 }
 203
 204 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
 205                              int offset, int len, u32 *val)
 206 {
 207         struct pci_controller *hose;
 208         unsigned long addr;
 209
 210         hose = pci_bus_to_host(bus);
 211         if (hose == NULL)
 212                 return PCIBIOS_DEVICE_NOT_FOUND;
 213
 214         addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
 215         if (!addr)
 216                 return PCIBIOS_DEVICE_NOT_FOUND;
 217
 218         /*
 219          * Note: the caller has already checked that offset is
 220          * suitably aligned and that len is 1, 2 or 4.
 221          */
 222         switch (len) {
 223         case 1:
 224                 *val = in_8((u8 *)addr);
 225                 break;
 226         case 2:
 227                 *val = in_le16((u16 *)addr);
 228                 break;
 229         default:
 230                 *val = in_le32((u32 *)addr);
 231                 break;
 232         }
 233         return PCIBIOS_SUCCESSFUL;
 234 }
 235
 236 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
 237                               int offset, int len, u32 val)
 238 {
 239         struct pci_controller *hose;
 240         unsigned long addr;
 241
 242         hose = pci_bus_to_host(bus);
 243         if (hose == NULL)
 244                 return PCIBIOS_DEVICE_NOT_FOUND;
 245
 246         addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
 247         if (!addr)
 248                 return PCIBIOS_DEVICE_NOT_FOUND;
 249         /*
 250          * Note: the caller has already checked that offset is
 251          * suitably aligned and that len is 1, 2 or 4.
 252          */
 253         switch (len) {
 254         case 1:
 255                 out_8((u8 *)addr, val);
 256                 (void) in_8((u8 *)addr);
 257                 break;
 258         case 2:
 259                 out_le16((u16 *)addr, val);
 260                 (void) in_le16((u16 *)addr);
 261                 break;
 262         default:
 263                 out_le32((u32 *)addr, val);
 264                 (void) in_le32((u32 *)addr);
 265                 break;
 266         }
 267         return PCIBIOS_SUCCESSFUL;
 268 }
 269
 270 static struct pci_ops u3_ht_pci_ops =
 271 {
 272         u3_ht_read_config,
 273         u3_ht_write_config
 274 };
 275
 276 static void __init setup_u3_agp(struct pci_controller* hose)
 277 {
 278         /* On G5, we move AGP up to high bus number so we don't need
 279          * to reassign bus numbers for HT. If we ever have P2P bridges
 280          * on AGP, we'll have to move pci_assign_all_buses to the
 281          * pci_controller structure so we enable it for AGP and not for
 282          * HT childs.
 283          * We hard code the address because of the different size of
 284          * the reg address cell, we shall fix that by killing struct
 285          * reg_property and using some accessor functions instead
 286          */
 287         hose->first_busno = 0xf0;
 288         hose->last_busno = 0xff;
 289         hose->ops = &u3_agp_pci_ops;
 290         hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
 291         hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
 292
 293         u3_agp = hose;
 294 }
 295
 296 static void __init setup_u3_ht(struct pci_controller* hose)
 297 {
 298         hose->ops = &u3_ht_pci_ops;
 299
 300         /* We hard code the address because of the different size of
 301          * the reg address cell, we shall fix that by killing struct
 302          * reg_property and using some accessor functions instead
 303          */
 304         hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
 305
 306         hose->first_busno = 0;
 307         hose->last_busno = 0xef;
 308
 309         u3_ht = hose;
 310 }
 311
 312 static int __init add_bridge(struct device_node *dev)
 313 {
 314         int len;
 315         struct pci_controller *hose;
 316         char* disp_name;
 317         int *bus_range;
 318         int primary = 1;
 319         struct property *of_prop;
 320
 321         DBG("Adding PCI host bridge %s\n", dev->full_name);
 322
 323         bus_range = (int *) get_property(dev, "bus-range", &len);
 324         if (bus_range == NULL || len < 2 * sizeof(int)) {
 325                 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
 326                 dev->full_name);
 327         }
 328
 329         hose = pcibios_alloc_controller(dev);
 330         if (hose == NULL)
 331                 return -ENOMEM;
 332         hose->first_busno = bus_range ? bus_range[0] : 0;
 333         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 334
 335         disp_name = NULL;
 336         if (device_is_compatible(dev, "u3-agp")) {
 337                 setup_u3_agp(hose);
 338                 disp_name = "U3-AGP";
 339                 primary = 0;
 340         } else if (device_is_compatible(dev, "u3-ht")) {
 341                 setup_u3_ht(hose);
 342                 disp_name = "U3-HT";
 343                 primary = 1;
 344         }
 345         printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
 346                 disp_name, hose->first_busno, hose->last_busno);
 347
 348         /* Interpret the "ranges" property */
 349         /* This also maps the I/O region and sets isa_io/mem_base */
 350         pci_process_bridge_OF_ranges(hose, dev, primary);
 351         pci_setup_phb_io(hose, primary);
 352
 353         /* Fixup "bus-range" OF property */
 354         fixup_bus_range(dev);
 355
 356         return 0;
 357 }
 358
 359
 360 void __init maple_pcibios_fixup(void)
 361 {
 362         struct pci_dev *dev = NULL;
 363
 364         DBG(" -> maple_pcibios_fixup\n");
 365
 366         for_each_pci_dev(dev)
 367                 pci_read_irq_line(dev);
 368
 369         DBG(" <- maple_pcibios_fixup\n");
 370 }
 371
 372 static void __init maple_fixup_phb_resources(void)
 373 {
 374         struct pci_controller *hose, *tmp;
 375
 376         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 377                 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
 378                 hose->io_resource.start += offset;
 379                 hose->io_resource.end += offset;
 380                 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
 381                        hose->global_number,
 382                        hose->io_resource.start, hose->io_resource.end);
 383         }
 384 }
 385
 386 void __init maple_pci_init(void)
 387 {
 388         struct device_node *np, *root;
 389         struct device_node *ht = NULL;
 390
 391         /* Probe root PCI hosts, that is on U3 the AGP host and the
 392          * HyperTransport host. That one is actually "kept" around
 393          * and actually added last as it's resource management relies
 394          * on the AGP resources to have been setup first
 395          */
 396         root = of_find_node_by_path("/");
 397         if (root == NULL) {
 398                 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n");
 399                 return;
 400         }
 401         for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
 402                 if (np->name == NULL)
 403                         continue;
 404                 if (strcmp(np->name, "pci") == 0) {
 405                         if (add_bridge(np) == 0)
 406                                 of_node_get(np);
 407                 }
 408                 if (strcmp(np->name, "ht") == 0) {
 409                         of_node_get(np);
 410                         ht = np;
 411                 }
 412         }
 413         of_node_put(root);
 414
 415         /* Now setup the HyperTransport host if we found any
 416          */
 417         if (ht && add_bridge(ht) != 0)
 418                 of_node_put(ht);
 419
 420         /* Fixup the IO resources on our host bridges as the common code
 421          * does it only for childs of the host bridges
 422          */
 423         maple_fixup_phb_resources();
 424
 425         /* Setup the linkage between OF nodes and PHBs */
 426         pci_devs_phb_init();
 427
 428         /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
 429          * assume there is no P2P bridge on the AGP bus, which should be a
 430          * safe assumptions hopefully.
 431          */
 432         if (u3_agp) {
 433                 struct device_node *np = u3_agp->arch_data;
 434                 PCI_DN(np)->busno = 0xf0;
 435                 for (np = np->child; np; np = np->sibling)
 436                         PCI_DN(np)->busno = 0xf0;
 437         }
 438
 439         /* Tell pci.c to use the common resource allocation mecanism */
 440         pci_probe_only = 0;
 441
 442         /* Allow all IO */
 443         io_page_mask = -1;
 444 }
 445
 446 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel)
 447 {
 448         struct device_node *np;
 449         int irq = channel ? 15 : 14;
 450
 451         if (pdev->vendor != PCI_VENDOR_ID_AMD ||
 452             pdev->device != PCI_DEVICE_ID_AMD_8111_IDE)
 453                 return irq;
 454
 455         np = pci_device_to_OF_node(pdev);
 456         if (np == NULL)
 457                 return irq;
 458         if (np->n_intrs < 2)
 459                 return irq;
 460         return np->intrs[channel & 0x1].line;
 461 }
 462
 463 /* XXX: To remove once all firmwares are ok */
 464 static void fixup_maple_ide(struct pci_dev* dev)
 465 {
 466 #if 0 /* Enable this to enable IDE port 0 */
 467         {
 468                 u8 v;
 469
 470                 pci_read_config_byte(dev, 0x40, &v);
 471                 v |= 2;
 472                 pci_write_config_byte(dev, 0x40, v);
 473         }
 474 #endif
 475 #if 0 /* fix bus master base */
 476         pci_write_config_dword(dev, 0x20, 0xcc01);
 477         printk("old ide resource: %lx -> %lx \n",
 478                dev->resource[4].start, dev->resource[4].end);
 479         dev->resource[4].start = 0xcc00;
 480         dev->resource[4].end = 0xcc10;
 481 #endif
 482 #if 1 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */
 483         {
 484                 struct pci_dev *apicdev;
 485                 u32 v;
 486
 487                 apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0));
 488                 if (apicdev == NULL)
 489                         printk("IDE Fixup IRQ: Can't find IO-APIC !\n");
 490                 else {
 491                         pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14);
 492                         pci_read_config_dword(apicdev, 0xf4, &v);
 493                         v &= ~0x00000022;
 494                         pci_write_config_dword(apicdev, 0xf4, v);
 495                         pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15);
 496                         pci_read_config_dword(apicdev, 0xf4, &v);
 497                         v &= ~0x00000022;
 498                         pci_write_config_dword(apicdev, 0xf4, v);
 499                         pci_dev_put(apicdev);
 500                 }
 501         }
 502 #endif
 503 }
 504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE,
 505                          fixup_maple_ide);