2 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
3 * Ben. Herrenschmidt (benh@kernel.crashing.org)
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
12 * - Replace mdelay with some schedule loop if possible
13 * - Shorten some obfuscated delays on some routines (like modem
15 * - Refcount some clocks (see darwin)
16 * - Split split split...
19 #include <linux/types.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/kernel.h>
23 #include <linux/sched.h>
25 #include <linux/of_address.h>
26 #include <linux/spinlock.h>
27 #include <linux/adb.h>
28 #include <linux/pmu.h>
29 #include <linux/ioport.h>
30 #include <linux/export.h>
31 #include <linux/pci.h>
32 #include <asm/sections.h>
33 #include <asm/errno.h>
34 #include <asm/ohare.h>
35 #include <asm/heathrow.h>
36 #include <asm/keylargo.h>
37 #include <asm/uninorth.h>
40 #include <asm/machdep.h>
41 #include <asm/pmac_feature.h>
42 #include <asm/dbdma.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/pmac_low_i2c.h>
49 #define DBG(fmt...) printk(KERN_DEBUG fmt)
54 #ifdef CONFIG_PPC_BOOK3S_32
55 extern int powersave_lowspeed
;
58 extern int powersave_nap
;
59 extern struct device_node
*k2_skiplist
[2];
62 * We use a single global lock to protect accesses. Each driver has
63 * to take care of its own locking
65 DEFINE_RAW_SPINLOCK(feature_lock
);
67 #define LOCK(flags) raw_spin_lock_irqsave(&feature_lock, flags);
68 #define UNLOCK(flags) raw_spin_unlock_irqrestore(&feature_lock, flags);
72 * Instance of some macio stuffs
74 struct macio_chip macio_chips
[MAX_MACIO_CHIPS
];
76 struct macio_chip
*macio_find(struct device_node
*child
, int type
)
81 for (i
=0; i
< MAX_MACIO_CHIPS
&& macio_chips
[i
].of_node
; i
++)
82 if (child
== macio_chips
[i
].of_node
&&
83 (!type
|| macio_chips
[i
].type
== type
))
84 return &macio_chips
[i
];
85 child
= child
->parent
;
89 EXPORT_SYMBOL_GPL(macio_find
);
91 static const char *macio_names
[] =
108 struct device_node
*uninorth_node
;
109 u32 __iomem
*uninorth_base
;
111 static u32 uninorth_rev
;
112 static int uninorth_maj
;
113 static void __iomem
*u3_ht_base
;
116 * For each motherboard family, we have a table of functions pointers
117 * that handle the various features.
120 typedef long (*feature_call
)(struct device_node
*node
, long param
, long value
);
122 struct feature_table_entry
{
123 unsigned int selector
;
124 feature_call function
;
129 const char* model_string
;
130 const char* model_name
;
132 struct feature_table_entry
* features
;
133 unsigned long board_flags
;
135 static struct pmac_mb_def pmac_mb
;
138 * Here are the chip specific feature functions
141 static inline int simple_feature_tweak(struct device_node
*node
, int type
,
142 int reg
, u32 mask
, int value
)
144 struct macio_chip
* macio
;
147 macio
= macio_find(node
, type
);
152 MACIO_BIS(reg
, mask
);
154 MACIO_BIC(reg
, mask
);
155 (void)MACIO_IN32(reg
);
163 static long ohare_htw_scc_enable(struct device_node
*node
, long param
,
166 struct macio_chip
* macio
;
167 unsigned long chan_mask
;
173 macio
= macio_find(node
, 0);
176 if (of_node_name_eq(node
, "ch-a"))
177 chan_mask
= MACIO_FLAG_SCCA_ON
;
178 else if (of_node_name_eq(node
, "ch-b"))
179 chan_mask
= MACIO_FLAG_SCCB_ON
;
183 htw
= (macio
->type
== macio_heathrow
|| macio
->type
== macio_paddington
184 || macio
->type
== macio_gatwick
);
185 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
186 trans
= (pmac_mb
.model_id
!= PMAC_TYPE_YOSEMITE
&&
187 pmac_mb
.model_id
!= PMAC_TYPE_YIKES
);
189 #ifdef CONFIG_ADB_PMU
190 if ((param
& 0xfff) == PMAC_SCC_IRDA
)
192 #endif /* CONFIG_ADB_PMU */
194 fcr
= MACIO_IN32(OHARE_FCR
);
195 /* Check if scc cell need enabling */
196 if (!(fcr
& OH_SCC_ENABLE
)) {
197 fcr
|= OH_SCC_ENABLE
;
199 /* Side effect: this will also power up the
200 * modem, but it's too messy to figure out on which
201 * ports this controls the transceiver and on which
202 * it controls the modem
205 fcr
&= ~HRW_SCC_TRANS_EN_N
;
206 MACIO_OUT32(OHARE_FCR
, fcr
);
207 fcr
|= (rmask
= HRW_RESET_SCC
);
208 MACIO_OUT32(OHARE_FCR
, fcr
);
210 fcr
|= (rmask
= OH_SCC_RESET
);
211 MACIO_OUT32(OHARE_FCR
, fcr
);
214 (void)MACIO_IN32(OHARE_FCR
);
218 MACIO_OUT32(OHARE_FCR
, fcr
);
220 if (chan_mask
& MACIO_FLAG_SCCA_ON
)
222 if (chan_mask
& MACIO_FLAG_SCCB_ON
)
224 MACIO_OUT32(OHARE_FCR
, fcr
);
225 macio
->flags
|= chan_mask
;
227 if (param
& PMAC_SCC_FLAG_XMON
)
228 macio
->flags
|= MACIO_FLAG_SCC_LOCKED
;
230 if (macio
->flags
& MACIO_FLAG_SCC_LOCKED
)
233 fcr
= MACIO_IN32(OHARE_FCR
);
234 if (chan_mask
& MACIO_FLAG_SCCA_ON
)
236 if (chan_mask
& MACIO_FLAG_SCCB_ON
)
238 MACIO_OUT32(OHARE_FCR
, fcr
);
239 if ((fcr
& (OH_SCCA_IO
| OH_SCCB_IO
)) == 0) {
240 fcr
&= ~OH_SCC_ENABLE
;
242 fcr
|= HRW_SCC_TRANS_EN_N
;
243 MACIO_OUT32(OHARE_FCR
, fcr
);
245 macio
->flags
&= ~(chan_mask
);
248 #ifdef CONFIG_ADB_PMU
249 if ((param
& 0xfff) == PMAC_SCC_IRDA
)
251 #endif /* CONFIG_ADB_PMU */
256 static long ohare_floppy_enable(struct device_node
*node
, long param
,
259 return simple_feature_tweak(node
, macio_ohare
,
260 OHARE_FCR
, OH_FLOPPY_ENABLE
, value
);
263 static long ohare_mesh_enable(struct device_node
*node
, long param
, long value
)
265 return simple_feature_tweak(node
, macio_ohare
,
266 OHARE_FCR
, OH_MESH_ENABLE
, value
);
269 static long ohare_ide_enable(struct device_node
*node
, long param
, long value
)
273 /* For some reason, setting the bit in set_initial_features()
274 * doesn't stick. I'm still investigating... --BenH.
277 simple_feature_tweak(node
, macio_ohare
,
278 OHARE_FCR
, OH_IOBUS_ENABLE
, 1);
279 return simple_feature_tweak(node
, macio_ohare
,
280 OHARE_FCR
, OH_IDE0_ENABLE
, value
);
282 return simple_feature_tweak(node
, macio_ohare
,
283 OHARE_FCR
, OH_BAY_IDE_ENABLE
, value
);
289 static long ohare_ide_reset(struct device_node
*node
, long param
, long value
)
293 return simple_feature_tweak(node
, macio_ohare
,
294 OHARE_FCR
, OH_IDE0_RESET_N
, !value
);
296 return simple_feature_tweak(node
, macio_ohare
,
297 OHARE_FCR
, OH_IDE1_RESET_N
, !value
);
303 static long ohare_sleep_state(struct device_node
*node
, long param
, long value
)
305 struct macio_chip
* macio
= &macio_chips
[0];
307 if ((pmac_mb
.board_flags
& PMAC_MB_CAN_SLEEP
) == 0)
310 MACIO_BIC(OHARE_FCR
, OH_IOBUS_ENABLE
);
311 } else if (value
== 0) {
312 MACIO_BIS(OHARE_FCR
, OH_IOBUS_ENABLE
);
318 static long heathrow_modem_enable(struct device_node
*node
, long param
,
321 struct macio_chip
* macio
;
325 macio
= macio_find(node
, macio_unknown
);
328 gpio
= MACIO_IN8(HRW_GPIO_MODEM_RESET
) & ~1;
331 MACIO_OUT8(HRW_GPIO_MODEM_RESET
, gpio
);
333 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET
);
336 if (pmac_mb
.model_id
!= PMAC_TYPE_YOSEMITE
&&
337 pmac_mb
.model_id
!= PMAC_TYPE_YIKES
) {
340 MACIO_BIC(HEATHROW_FCR
, HRW_SCC_TRANS_EN_N
);
342 MACIO_BIS(HEATHROW_FCR
, HRW_SCC_TRANS_EN_N
);
344 (void)MACIO_IN32(HEATHROW_FCR
);
349 MACIO_OUT8(HRW_GPIO_MODEM_RESET
, gpio
| 1);
350 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET
);
351 UNLOCK(flags
); mdelay(250); LOCK(flags
);
352 MACIO_OUT8(HRW_GPIO_MODEM_RESET
, gpio
);
353 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET
);
354 UNLOCK(flags
); mdelay(250); LOCK(flags
);
355 MACIO_OUT8(HRW_GPIO_MODEM_RESET
, gpio
| 1);
356 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET
);
357 UNLOCK(flags
); mdelay(250);
362 static long heathrow_floppy_enable(struct device_node
*node
, long param
,
365 return simple_feature_tweak(node
, macio_unknown
,
367 HRW_SWIM_ENABLE
|HRW_BAY_FLOPPY_ENABLE
,
371 static long heathrow_mesh_enable(struct device_node
*node
, long param
,
374 struct macio_chip
* macio
;
377 macio
= macio_find(node
, macio_unknown
);
381 /* Set clear mesh cell enable */
383 MACIO_BIS(HEATHROW_FCR
, HRW_MESH_ENABLE
);
385 MACIO_BIC(HEATHROW_FCR
, HRW_MESH_ENABLE
);
386 (void)MACIO_IN32(HEATHROW_FCR
);
388 /* Set/Clear termination power */
390 MACIO_BIC(HEATHROW_MBCR
, 0x04000000);
392 MACIO_BIS(HEATHROW_MBCR
, 0x04000000);
393 (void)MACIO_IN32(HEATHROW_MBCR
);
400 static long heathrow_ide_enable(struct device_node
*node
, long param
,
405 return simple_feature_tweak(node
, macio_unknown
,
406 HEATHROW_FCR
, HRW_IDE0_ENABLE
, value
);
408 return simple_feature_tweak(node
, macio_unknown
,
409 HEATHROW_FCR
, HRW_BAY_IDE_ENABLE
, value
);
415 static long heathrow_ide_reset(struct device_node
*node
, long param
,
420 return simple_feature_tweak(node
, macio_unknown
,
421 HEATHROW_FCR
, HRW_IDE0_RESET_N
, !value
);
423 return simple_feature_tweak(node
, macio_unknown
,
424 HEATHROW_FCR
, HRW_IDE1_RESET_N
, !value
);
430 static long heathrow_bmac_enable(struct device_node
*node
, long param
,
433 struct macio_chip
* macio
;
436 macio
= macio_find(node
, 0);
441 MACIO_BIS(HEATHROW_FCR
, HRW_BMAC_IO_ENABLE
);
442 MACIO_BIS(HEATHROW_FCR
, HRW_BMAC_RESET
);
444 (void)MACIO_IN32(HEATHROW_FCR
);
447 MACIO_BIC(HEATHROW_FCR
, HRW_BMAC_RESET
);
449 (void)MACIO_IN32(HEATHROW_FCR
);
453 MACIO_BIC(HEATHROW_FCR
, HRW_BMAC_IO_ENABLE
);
459 static long heathrow_sound_enable(struct device_node
*node
, long param
,
462 struct macio_chip
* macio
;
465 /* B&W G3 and Yikes don't support that properly (the
466 * sound appear to never come back after being shut down).
468 if (pmac_mb
.model_id
== PMAC_TYPE_YOSEMITE
||
469 pmac_mb
.model_id
== PMAC_TYPE_YIKES
)
472 macio
= macio_find(node
, 0);
477 MACIO_BIS(HEATHROW_FCR
, HRW_SOUND_CLK_ENABLE
);
478 MACIO_BIC(HEATHROW_FCR
, HRW_SOUND_POWER_N
);
480 (void)MACIO_IN32(HEATHROW_FCR
);
483 MACIO_BIS(HEATHROW_FCR
, HRW_SOUND_POWER_N
);
484 MACIO_BIC(HEATHROW_FCR
, HRW_SOUND_CLK_ENABLE
);
490 static u32 save_fcr
[6];
491 static u32 save_mbcr
;
492 static struct dbdma_regs save_dbdma
[13];
493 static struct dbdma_regs save_alt_dbdma
[13];
495 static void dbdma_save(struct macio_chip
*macio
, struct dbdma_regs
*save
)
499 /* Save state & config of DBDMA channels */
500 for (i
= 0; i
< 13; i
++) {
501 volatile struct dbdma_regs __iomem
* chan
= (void __iomem
*)
502 (macio
->base
+ ((0x8000+i
*0x100)>>2));
503 save
[i
].cmdptr_hi
= in_le32(&chan
->cmdptr_hi
);
504 save
[i
].cmdptr
= in_le32(&chan
->cmdptr
);
505 save
[i
].intr_sel
= in_le32(&chan
->intr_sel
);
506 save
[i
].br_sel
= in_le32(&chan
->br_sel
);
507 save
[i
].wait_sel
= in_le32(&chan
->wait_sel
);
511 static void dbdma_restore(struct macio_chip
*macio
, struct dbdma_regs
*save
)
515 /* Save state & config of DBDMA channels */
516 for (i
= 0; i
< 13; i
++) {
517 volatile struct dbdma_regs __iomem
* chan
= (void __iomem
*)
518 (macio
->base
+ ((0x8000+i
*0x100)>>2));
519 out_le32(&chan
->control
, (ACTIVE
|DEAD
|WAKE
|FLUSH
|PAUSE
|RUN
)<<16);
520 while (in_le32(&chan
->status
) & ACTIVE
)
522 out_le32(&chan
->cmdptr_hi
, save
[i
].cmdptr_hi
);
523 out_le32(&chan
->cmdptr
, save
[i
].cmdptr
);
524 out_le32(&chan
->intr_sel
, save
[i
].intr_sel
);
525 out_le32(&chan
->br_sel
, save
[i
].br_sel
);
526 out_le32(&chan
->wait_sel
, save
[i
].wait_sel
);
530 static void heathrow_sleep(struct macio_chip
*macio
, int secondary
)
533 dbdma_save(macio
, save_alt_dbdma
);
534 save_fcr
[2] = MACIO_IN32(0x38);
535 save_fcr
[3] = MACIO_IN32(0x3c);
537 dbdma_save(macio
, save_dbdma
);
538 save_fcr
[0] = MACIO_IN32(0x38);
539 save_fcr
[1] = MACIO_IN32(0x3c);
540 save_mbcr
= MACIO_IN32(0x34);
541 /* Make sure sound is shut down */
542 MACIO_BIS(HEATHROW_FCR
, HRW_SOUND_POWER_N
);
543 MACIO_BIC(HEATHROW_FCR
, HRW_SOUND_CLK_ENABLE
);
544 /* This seems to be necessary as well or the fan
545 * keeps coming up and battery drains fast */
546 MACIO_BIC(HEATHROW_FCR
, HRW_IOBUS_ENABLE
);
547 MACIO_BIC(HEATHROW_FCR
, HRW_IDE0_RESET_N
);
548 /* Make sure eth is down even if module or sleep
549 * won't work properly */
550 MACIO_BIC(HEATHROW_FCR
, HRW_BMAC_IO_ENABLE
| HRW_BMAC_RESET
);
552 /* Make sure modem is shut down */
553 MACIO_OUT8(HRW_GPIO_MODEM_RESET
,
554 MACIO_IN8(HRW_GPIO_MODEM_RESET
) & ~1);
555 MACIO_BIS(HEATHROW_FCR
, HRW_SCC_TRANS_EN_N
);
556 MACIO_BIC(HEATHROW_FCR
, OH_SCCA_IO
|OH_SCCB_IO
|HRW_SCC_ENABLE
);
558 /* Let things settle */
559 (void)MACIO_IN32(HEATHROW_FCR
);
562 static void heathrow_wakeup(struct macio_chip
*macio
, int secondary
)
565 MACIO_OUT32(0x38, save_fcr
[2]);
566 (void)MACIO_IN32(0x38);
568 MACIO_OUT32(0x3c, save_fcr
[3]);
569 (void)MACIO_IN32(0x38);
571 dbdma_restore(macio
, save_alt_dbdma
);
573 MACIO_OUT32(0x38, save_fcr
[0] | HRW_IOBUS_ENABLE
);
574 (void)MACIO_IN32(0x38);
576 MACIO_OUT32(0x3c, save_fcr
[1]);
577 (void)MACIO_IN32(0x38);
579 MACIO_OUT32(0x34, save_mbcr
);
580 (void)MACIO_IN32(0x38);
582 dbdma_restore(macio
, save_dbdma
);
586 static long heathrow_sleep_state(struct device_node
*node
, long param
,
589 if ((pmac_mb
.board_flags
& PMAC_MB_CAN_SLEEP
) == 0)
592 if (macio_chips
[1].type
== macio_gatwick
)
593 heathrow_sleep(&macio_chips
[0], 1);
594 heathrow_sleep(&macio_chips
[0], 0);
595 } else if (value
== 0) {
596 heathrow_wakeup(&macio_chips
[0], 0);
597 if (macio_chips
[1].type
== macio_gatwick
)
598 heathrow_wakeup(&macio_chips
[0], 1);
603 static long core99_scc_enable(struct device_node
*node
, long param
, long value
)
605 struct macio_chip
* macio
;
607 unsigned long chan_mask
;
610 macio
= macio_find(node
, 0);
613 if (of_node_name_eq(node
, "ch-a"))
614 chan_mask
= MACIO_FLAG_SCCA_ON
;
615 else if (of_node_name_eq(node
, "ch-b"))
616 chan_mask
= MACIO_FLAG_SCCB_ON
;
621 int need_reset_scc
= 0;
622 int need_reset_irda
= 0;
625 fcr
= MACIO_IN32(KEYLARGO_FCR0
);
626 /* Check if scc cell need enabling */
627 if (!(fcr
& KL0_SCC_CELL_ENABLE
)) {
628 fcr
|= KL0_SCC_CELL_ENABLE
;
631 if (chan_mask
& MACIO_FLAG_SCCA_ON
) {
632 fcr
|= KL0_SCCA_ENABLE
;
633 /* Don't enable line drivers for I2S modem */
634 if ((param
& 0xfff) == PMAC_SCC_I2S1
)
635 fcr
&= ~KL0_SCC_A_INTF_ENABLE
;
637 fcr
|= KL0_SCC_A_INTF_ENABLE
;
639 if (chan_mask
& MACIO_FLAG_SCCB_ON
) {
640 fcr
|= KL0_SCCB_ENABLE
;
641 /* Perform irda specific inits */
642 if ((param
& 0xfff) == PMAC_SCC_IRDA
) {
643 fcr
&= ~KL0_SCC_B_INTF_ENABLE
;
644 fcr
|= KL0_IRDA_ENABLE
;
645 fcr
|= KL0_IRDA_CLK32_ENABLE
| KL0_IRDA_CLK19_ENABLE
;
646 fcr
|= KL0_IRDA_SOURCE1_SEL
;
647 fcr
&= ~(KL0_IRDA_FAST_CONNECT
|KL0_IRDA_DEFAULT1
|KL0_IRDA_DEFAULT0
);
648 fcr
&= ~(KL0_IRDA_SOURCE2_SEL
|KL0_IRDA_HIGH_BAND
);
651 fcr
|= KL0_SCC_B_INTF_ENABLE
;
653 MACIO_OUT32(KEYLARGO_FCR0
, fcr
);
654 macio
->flags
|= chan_mask
;
655 if (need_reset_scc
) {
656 MACIO_BIS(KEYLARGO_FCR0
, KL0_SCC_RESET
);
657 (void)MACIO_IN32(KEYLARGO_FCR0
);
661 MACIO_BIC(KEYLARGO_FCR0
, KL0_SCC_RESET
);
663 if (need_reset_irda
) {
664 MACIO_BIS(KEYLARGO_FCR0
, KL0_IRDA_RESET
);
665 (void)MACIO_IN32(KEYLARGO_FCR0
);
669 MACIO_BIC(KEYLARGO_FCR0
, KL0_IRDA_RESET
);
672 if (param
& PMAC_SCC_FLAG_XMON
)
673 macio
->flags
|= MACIO_FLAG_SCC_LOCKED
;
675 if (macio
->flags
& MACIO_FLAG_SCC_LOCKED
)
678 fcr
= MACIO_IN32(KEYLARGO_FCR0
);
679 if (chan_mask
& MACIO_FLAG_SCCA_ON
)
680 fcr
&= ~KL0_SCCA_ENABLE
;
681 if (chan_mask
& MACIO_FLAG_SCCB_ON
) {
682 fcr
&= ~KL0_SCCB_ENABLE
;
683 /* Perform irda specific clears */
684 if ((param
& 0xfff) == PMAC_SCC_IRDA
) {
685 fcr
&= ~KL0_IRDA_ENABLE
;
686 fcr
&= ~(KL0_IRDA_CLK32_ENABLE
| KL0_IRDA_CLK19_ENABLE
);
687 fcr
&= ~(KL0_IRDA_FAST_CONNECT
|KL0_IRDA_DEFAULT1
|KL0_IRDA_DEFAULT0
);
688 fcr
&= ~(KL0_IRDA_SOURCE1_SEL
|KL0_IRDA_SOURCE2_SEL
|KL0_IRDA_HIGH_BAND
);
691 MACIO_OUT32(KEYLARGO_FCR0
, fcr
);
692 if ((fcr
& (KL0_SCCA_ENABLE
| KL0_SCCB_ENABLE
)) == 0) {
693 fcr
&= ~KL0_SCC_CELL_ENABLE
;
694 MACIO_OUT32(KEYLARGO_FCR0
, fcr
);
696 macio
->flags
&= ~(chan_mask
);
704 core99_modem_enable(struct device_node
*node
, long param
, long value
)
706 struct macio_chip
* macio
;
710 /* Hack for internal USB modem */
712 if (macio_chips
[0].type
!= macio_keylargo
)
714 node
= macio_chips
[0].of_node
;
716 macio
= macio_find(node
, 0);
719 gpio
= MACIO_IN8(KL_GPIO_MODEM_RESET
);
720 gpio
|= KEYLARGO_GPIO_OUTPUT_ENABLE
;
721 gpio
&= ~KEYLARGO_GPIO_OUTOUT_DATA
;
725 MACIO_OUT8(KL_GPIO_MODEM_RESET
, gpio
);
727 (void)MACIO_IN8(KL_GPIO_MODEM_RESET
);
732 MACIO_BIC(KEYLARGO_FCR2
, KL2_ALT_DATA_OUT
);
734 (void)MACIO_IN32(KEYLARGO_FCR2
);
737 MACIO_BIS(KEYLARGO_FCR2
, KL2_ALT_DATA_OUT
);
742 MACIO_OUT8(KL_GPIO_MODEM_RESET
, gpio
| KEYLARGO_GPIO_OUTOUT_DATA
);
743 (void)MACIO_IN8(KL_GPIO_MODEM_RESET
);
744 UNLOCK(flags
); mdelay(250); LOCK(flags
);
745 MACIO_OUT8(KL_GPIO_MODEM_RESET
, gpio
);
746 (void)MACIO_IN8(KL_GPIO_MODEM_RESET
);
747 UNLOCK(flags
); mdelay(250); LOCK(flags
);
748 MACIO_OUT8(KL_GPIO_MODEM_RESET
, gpio
| KEYLARGO_GPIO_OUTOUT_DATA
);
749 (void)MACIO_IN8(KL_GPIO_MODEM_RESET
);
750 UNLOCK(flags
); mdelay(250);
756 pangea_modem_enable(struct device_node
*node
, long param
, long value
)
758 struct macio_chip
* macio
;
762 /* Hack for internal USB modem */
764 if (macio_chips
[0].type
!= macio_pangea
&&
765 macio_chips
[0].type
!= macio_intrepid
)
767 node
= macio_chips
[0].of_node
;
769 macio
= macio_find(node
, 0);
772 gpio
= MACIO_IN8(KL_GPIO_MODEM_RESET
);
773 gpio
|= KEYLARGO_GPIO_OUTPUT_ENABLE
;
774 gpio
&= ~KEYLARGO_GPIO_OUTOUT_DATA
;
778 MACIO_OUT8(KL_GPIO_MODEM_RESET
, gpio
);
780 (void)MACIO_IN8(KL_GPIO_MODEM_RESET
);
785 MACIO_OUT8(KL_GPIO_MODEM_POWER
,
786 KEYLARGO_GPIO_OUTPUT_ENABLE
);
788 (void)MACIO_IN32(KEYLARGO_FCR2
);
791 MACIO_OUT8(KL_GPIO_MODEM_POWER
,
792 KEYLARGO_GPIO_OUTPUT_ENABLE
| KEYLARGO_GPIO_OUTOUT_DATA
);
797 MACIO_OUT8(KL_GPIO_MODEM_RESET
, gpio
| KEYLARGO_GPIO_OUTOUT_DATA
);
798 (void)MACIO_IN8(KL_GPIO_MODEM_RESET
);
799 UNLOCK(flags
); mdelay(250); LOCK(flags
);
800 MACIO_OUT8(KL_GPIO_MODEM_RESET
, gpio
);
801 (void)MACIO_IN8(KL_GPIO_MODEM_RESET
);
802 UNLOCK(flags
); mdelay(250); LOCK(flags
);
803 MACIO_OUT8(KL_GPIO_MODEM_RESET
, gpio
| KEYLARGO_GPIO_OUTOUT_DATA
);
804 (void)MACIO_IN8(KL_GPIO_MODEM_RESET
);
805 UNLOCK(flags
); mdelay(250);
811 core99_ata100_enable(struct device_node
*node
, long value
)
814 struct pci_dev
*pdev
= NULL
;
818 if (uninorth_rev
< 0x24)
823 UN_BIS(UNI_N_CLOCK_CNTL
, UNI_N_CLOCK_CNTL_ATA100
);
825 UN_BIC(UNI_N_CLOCK_CNTL
, UNI_N_CLOCK_CNTL_ATA100
);
826 (void)UN_IN(UNI_N_CLOCK_CNTL
);
831 if (pci_device_from_OF_node(node
, &pbus
, &pid
) == 0)
832 pdev
= pci_get_domain_bus_and_slot(0, pbus
, pid
);
835 rc
= pci_enable_device(pdev
);
837 pci_set_master(pdev
);
846 core99_ide_enable(struct device_node
*node
, long param
, long value
)
848 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
853 return simple_feature_tweak(node
, macio_unknown
,
854 KEYLARGO_FCR1
, KL1_EIDE0_ENABLE
, value
);
856 return simple_feature_tweak(node
, macio_unknown
,
857 KEYLARGO_FCR1
, KL1_EIDE1_ENABLE
, value
);
859 return simple_feature_tweak(node
, macio_unknown
,
860 KEYLARGO_FCR1
, KL1_UIDE_ENABLE
, value
);
862 return core99_ata100_enable(node
, value
);
869 core99_ide_reset(struct device_node
*node
, long param
, long value
)
873 return simple_feature_tweak(node
, macio_unknown
,
874 KEYLARGO_FCR1
, KL1_EIDE0_RESET_N
, !value
);
876 return simple_feature_tweak(node
, macio_unknown
,
877 KEYLARGO_FCR1
, KL1_EIDE1_RESET_N
, !value
);
879 return simple_feature_tweak(node
, macio_unknown
,
880 KEYLARGO_FCR1
, KL1_UIDE_RESET_N
, !value
);
887 core99_gmac_enable(struct device_node
*node
, long param
, long value
)
893 UN_BIS(UNI_N_CLOCK_CNTL
, UNI_N_CLOCK_CNTL_GMAC
);
895 UN_BIC(UNI_N_CLOCK_CNTL
, UNI_N_CLOCK_CNTL_GMAC
);
896 (void)UN_IN(UNI_N_CLOCK_CNTL
);
904 core99_gmac_phy_reset(struct device_node
*node
, long param
, long value
)
907 struct macio_chip
*macio
;
909 macio
= &macio_chips
[0];
910 if (macio
->type
!= macio_keylargo
&& macio
->type
!= macio_pangea
&&
911 macio
->type
!= macio_intrepid
)
915 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET
, KEYLARGO_GPIO_OUTPUT_ENABLE
);
916 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET
);
920 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET
, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
921 KEYLARGO_GPIO_OUTOUT_DATA
);
929 core99_sound_chip_enable(struct device_node
*node
, long param
, long value
)
931 struct macio_chip
* macio
;
934 macio
= macio_find(node
, 0);
938 /* Do a better probe code, screamer G4 desktops &
939 * iMacs can do that too, add a recalibrate in
942 if (pmac_mb
.model_id
== PMAC_TYPE_PISMO
||
943 pmac_mb
.model_id
== PMAC_TYPE_TITANIUM
) {
946 MACIO_OUT8(KL_GPIO_SOUND_POWER
,
947 KEYLARGO_GPIO_OUTPUT_ENABLE
|
948 KEYLARGO_GPIO_OUTOUT_DATA
);
950 MACIO_OUT8(KL_GPIO_SOUND_POWER
,
951 KEYLARGO_GPIO_OUTPUT_ENABLE
);
952 (void)MACIO_IN8(KL_GPIO_SOUND_POWER
);
959 core99_airport_enable(struct device_node
*node
, long param
, long value
)
961 struct macio_chip
* macio
;
965 macio
= macio_find(node
, 0);
969 /* Hint: we allow passing of macio itself for the sake of the
972 if (node
!= macio
->of_node
&&
973 (!node
->parent
|| node
->parent
!= macio
->of_node
))
975 state
= (macio
->flags
& MACIO_FLAG_AIRPORT_ON
) != 0;
979 /* This code is a reproduction of OF enable-cardslot
980 * and init-wireless methods, slightly hacked until
984 MACIO_OUT8(KEYLARGO_GPIO_0
+0xf, 5);
985 (void)MACIO_IN8(KEYLARGO_GPIO_0
+0xf);
989 MACIO_OUT8(KEYLARGO_GPIO_0
+0xf, 4);
990 (void)MACIO_IN8(KEYLARGO_GPIO_0
+0xf);
996 MACIO_BIC(KEYLARGO_FCR2
, KL2_CARDSEL_16
);
997 (void)MACIO_IN32(KEYLARGO_FCR2
);
999 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0
+0xb, 0);
1000 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0
+0xb);
1002 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0
+0xa, 0x28);
1003 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0
+0xa);
1005 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0
+0xd, 0x28);
1006 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0
+0xd);
1008 MACIO_OUT8(KEYLARGO_GPIO_0
+0xd, 0x28);
1009 (void)MACIO_IN8(KEYLARGO_GPIO_0
+0xd);
1011 MACIO_OUT8(KEYLARGO_GPIO_0
+0xe, 0x28);
1012 (void)MACIO_IN8(KEYLARGO_GPIO_0
+0xe);
1015 MACIO_OUT32(0x1c000, 0);
1017 MACIO_OUT8(0x1a3e0, 0x41);
1018 (void)MACIO_IN8(0x1a3e0);
1021 MACIO_BIS(KEYLARGO_FCR2
, KL2_CARDSEL_16
);
1022 (void)MACIO_IN32(KEYLARGO_FCR2
);
1026 macio
->flags
|= MACIO_FLAG_AIRPORT_ON
;
1029 MACIO_BIC(KEYLARGO_FCR2
, KL2_CARDSEL_16
);
1030 (void)MACIO_IN32(KEYLARGO_FCR2
);
1031 MACIO_OUT8(KL_GPIO_AIRPORT_0
, 0);
1032 MACIO_OUT8(KL_GPIO_AIRPORT_1
, 0);
1033 MACIO_OUT8(KL_GPIO_AIRPORT_2
, 0);
1034 MACIO_OUT8(KL_GPIO_AIRPORT_3
, 0);
1035 MACIO_OUT8(KL_GPIO_AIRPORT_4
, 0);
1036 (void)MACIO_IN8(KL_GPIO_AIRPORT_4
);
1039 macio
->flags
&= ~MACIO_FLAG_AIRPORT_ON
;
1046 core99_reset_cpu(struct device_node
*node
, long param
, long value
)
1048 unsigned int reset_io
= 0;
1049 unsigned long flags
;
1050 struct macio_chip
*macio
;
1051 struct device_node
*np
;
1052 const int dflt_reset_lines
[] = { KL_GPIO_RESET_CPU0
,
1055 KL_GPIO_RESET_CPU3
};
1057 macio
= &macio_chips
[0];
1058 if (macio
->type
!= macio_keylargo
)
1061 for_each_of_cpu_node(np
) {
1062 const u32
*num
= of_get_property(np
, "reg", NULL
);
1063 const u32
*rst
= of_get_property(np
, "soft-reset", NULL
);
1064 if (num
== NULL
|| rst
== NULL
)
1066 if (param
== *num
) {
1071 if (np
== NULL
|| reset_io
== 0)
1072 reset_io
= dflt_reset_lines
[param
];
1075 MACIO_OUT8(reset_io
, KEYLARGO_GPIO_OUTPUT_ENABLE
);
1076 (void)MACIO_IN8(reset_io
);
1078 MACIO_OUT8(reset_io
, 0);
1079 (void)MACIO_IN8(reset_io
);
1084 #endif /* CONFIG_SMP */
1087 core99_usb_enable(struct device_node
*node
, long param
, long value
)
1089 struct macio_chip
*macio
;
1090 unsigned long flags
;
1095 macio
= &macio_chips
[0];
1096 if (macio
->type
!= macio_keylargo
&& macio
->type
!= macio_pangea
&&
1097 macio
->type
!= macio_intrepid
)
1100 prop
= of_get_property(node
, "AAPL,clock-id", NULL
);
1103 if (strncmp(prop
, "usb0u048", 8) == 0)
1105 else if (strncmp(prop
, "usb1u148", 8) == 0)
1107 else if (strncmp(prop
, "usb2u248", 8) == 0)
1112 /* Sorry for the brute-force locking, but this is only used during
1113 * sleep and the timing seem to be critical
1119 MACIO_BIC(KEYLARGO_FCR0
, (KL0_USB0_PAD_SUSPEND0
| KL0_USB0_PAD_SUSPEND1
));
1120 (void)MACIO_IN32(KEYLARGO_FCR0
);
1124 MACIO_BIS(KEYLARGO_FCR0
, KL0_USB0_CELL_ENABLE
);
1125 } else if (number
== 2) {
1126 MACIO_BIC(KEYLARGO_FCR0
, (KL0_USB1_PAD_SUSPEND0
| KL0_USB1_PAD_SUSPEND1
));
1128 (void)MACIO_IN32(KEYLARGO_FCR0
);
1131 MACIO_BIS(KEYLARGO_FCR0
, KL0_USB1_CELL_ENABLE
);
1132 } else if (number
== 4) {
1133 MACIO_BIC(KEYLARGO_FCR1
, (KL1_USB2_PAD_SUSPEND0
| KL1_USB2_PAD_SUSPEND1
));
1135 (void)MACIO_IN32(KEYLARGO_FCR1
);
1138 MACIO_BIS(KEYLARGO_FCR1
, KL1_USB2_CELL_ENABLE
);
1141 reg
= MACIO_IN32(KEYLARGO_FCR4
);
1142 reg
&= ~(KL4_PORT_WAKEUP_ENABLE(number
) | KL4_PORT_RESUME_WAKE_EN(number
) |
1143 KL4_PORT_CONNECT_WAKE_EN(number
) | KL4_PORT_DISCONNECT_WAKE_EN(number
));
1144 reg
&= ~(KL4_PORT_WAKEUP_ENABLE(number
+1) | KL4_PORT_RESUME_WAKE_EN(number
+1) |
1145 KL4_PORT_CONNECT_WAKE_EN(number
+1) | KL4_PORT_DISCONNECT_WAKE_EN(number
+1));
1146 MACIO_OUT32(KEYLARGO_FCR4
, reg
);
1147 (void)MACIO_IN32(KEYLARGO_FCR4
);
1150 reg
= MACIO_IN32(KEYLARGO_FCR3
);
1151 reg
&= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1152 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1153 reg
&= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1154 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1155 MACIO_OUT32(KEYLARGO_FCR3
, reg
);
1156 (void)MACIO_IN32(KEYLARGO_FCR3
);
1159 if (macio
->type
== macio_intrepid
) {
1160 /* wait for clock stopped bits to clear */
1161 u32 test0
= 0, test1
= 0;
1162 u32 status0
, status1
;
1168 test0
= UNI_N_CLOCK_STOPPED_USB0
;
1169 test1
= UNI_N_CLOCK_STOPPED_USB0PCI
;
1172 test0
= UNI_N_CLOCK_STOPPED_USB1
;
1173 test1
= UNI_N_CLOCK_STOPPED_USB1PCI
;
1176 test0
= UNI_N_CLOCK_STOPPED_USB2
;
1177 test1
= UNI_N_CLOCK_STOPPED_USB2PCI
;
1181 if (--timeout
<= 0) {
1182 printk(KERN_ERR
"core99_usb_enable: "
1183 "Timeout waiting for clocks\n");
1187 status0
= UN_IN(UNI_N_CLOCK_STOP_STATUS0
);
1188 status1
= UN_IN(UNI_N_CLOCK_STOP_STATUS1
);
1189 } while ((status0
& test0
) | (status1
& test1
));
1195 reg
= MACIO_IN32(KEYLARGO_FCR4
);
1196 reg
|= KL4_PORT_WAKEUP_ENABLE(number
) | KL4_PORT_RESUME_WAKE_EN(number
) |
1197 KL4_PORT_CONNECT_WAKE_EN(number
) | KL4_PORT_DISCONNECT_WAKE_EN(number
);
1198 reg
|= KL4_PORT_WAKEUP_ENABLE(number
+1) | KL4_PORT_RESUME_WAKE_EN(number
+1) |
1199 KL4_PORT_CONNECT_WAKE_EN(number
+1) | KL4_PORT_DISCONNECT_WAKE_EN(number
+1);
1200 MACIO_OUT32(KEYLARGO_FCR4
, reg
);
1201 (void)MACIO_IN32(KEYLARGO_FCR4
);
1204 reg
= MACIO_IN32(KEYLARGO_FCR3
);
1205 reg
|= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1206 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1207 reg
|= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1208 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1209 MACIO_OUT32(KEYLARGO_FCR3
, reg
);
1210 (void)MACIO_IN32(KEYLARGO_FCR3
);
1214 if (macio
->type
!= macio_intrepid
)
1215 MACIO_BIC(KEYLARGO_FCR0
, KL0_USB0_CELL_ENABLE
);
1216 (void)MACIO_IN32(KEYLARGO_FCR0
);
1218 MACIO_BIS(KEYLARGO_FCR0
, (KL0_USB0_PAD_SUSPEND0
| KL0_USB0_PAD_SUSPEND1
));
1219 (void)MACIO_IN32(KEYLARGO_FCR0
);
1220 } else if (number
== 2) {
1221 if (macio
->type
!= macio_intrepid
)
1222 MACIO_BIC(KEYLARGO_FCR0
, KL0_USB1_CELL_ENABLE
);
1223 (void)MACIO_IN32(KEYLARGO_FCR0
);
1225 MACIO_BIS(KEYLARGO_FCR0
, (KL0_USB1_PAD_SUSPEND0
| KL0_USB1_PAD_SUSPEND1
));
1226 (void)MACIO_IN32(KEYLARGO_FCR0
);
1227 } else if (number
== 4) {
1229 MACIO_BIS(KEYLARGO_FCR1
, (KL1_USB2_PAD_SUSPEND0
| KL1_USB2_PAD_SUSPEND1
));
1230 (void)MACIO_IN32(KEYLARGO_FCR1
);
1240 core99_firewire_enable(struct device_node
*node
, long param
, long value
)
1242 unsigned long flags
;
1243 struct macio_chip
*macio
;
1245 macio
= &macio_chips
[0];
1246 if (macio
->type
!= macio_keylargo
&& macio
->type
!= macio_pangea
&&
1247 macio
->type
!= macio_intrepid
)
1249 if (!(macio
->flags
& MACIO_FLAG_FW_SUPPORTED
))
1254 UN_BIS(UNI_N_CLOCK_CNTL
, UNI_N_CLOCK_CNTL_FW
);
1255 (void)UN_IN(UNI_N_CLOCK_CNTL
);
1257 UN_BIC(UNI_N_CLOCK_CNTL
, UNI_N_CLOCK_CNTL_FW
);
1258 (void)UN_IN(UNI_N_CLOCK_CNTL
);
1267 core99_firewire_cable_power(struct device_node
*node
, long param
, long value
)
1269 unsigned long flags
;
1270 struct macio_chip
*macio
;
1272 /* Trick: we allow NULL node */
1273 if ((pmac_mb
.board_flags
& PMAC_MB_HAS_FW_POWER
) == 0)
1275 macio
= &macio_chips
[0];
1276 if (macio
->type
!= macio_keylargo
&& macio
->type
!= macio_pangea
&&
1277 macio
->type
!= macio_intrepid
)
1279 if (!(macio
->flags
& MACIO_FLAG_FW_SUPPORTED
))
1284 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER
, 0);
1285 MACIO_IN8(KL_GPIO_FW_CABLE_POWER
);
1288 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER
, 4);
1289 MACIO_IN8(KL_GPIO_FW_CABLE_POWER
); udelay(10);
1298 intrepid_aack_delay_enable(struct device_node
*node
, long param
, long value
)
1300 unsigned long flags
;
1302 if (uninorth_rev
< 0xd2)
1307 UN_BIS(UNI_N_AACK_DELAY
, UNI_N_AACK_DELAY_ENABLE
);
1309 UN_BIC(UNI_N_AACK_DELAY
, UNI_N_AACK_DELAY_ENABLE
);
1316 #endif /* CONFIG_PPC64 */
1319 core99_read_gpio(struct device_node
*node
, long param
, long value
)
1321 struct macio_chip
*macio
= &macio_chips
[0];
1323 return MACIO_IN8(param
);
1328 core99_write_gpio(struct device_node
*node
, long param
, long value
)
1330 struct macio_chip
*macio
= &macio_chips
[0];
1332 MACIO_OUT8(param
, (u8
)(value
& 0xff));
1337 static long g5_gmac_enable(struct device_node
*node
, long param
, long value
)
1339 struct macio_chip
*macio
= &macio_chips
[0];
1340 unsigned long flags
;
1347 MACIO_BIS(KEYLARGO_FCR1
, K2_FCR1_GMAC_CLK_ENABLE
);
1349 k2_skiplist
[0] = NULL
;
1351 k2_skiplist
[0] = node
;
1353 MACIO_BIC(KEYLARGO_FCR1
, K2_FCR1_GMAC_CLK_ENABLE
);
1362 static long g5_fw_enable(struct device_node
*node
, long param
, long value
)
1364 struct macio_chip
*macio
= &macio_chips
[0];
1365 unsigned long flags
;
1372 MACIO_BIS(KEYLARGO_FCR1
, K2_FCR1_FW_CLK_ENABLE
);
1374 k2_skiplist
[1] = NULL
;
1376 k2_skiplist
[1] = node
;
1378 MACIO_BIC(KEYLARGO_FCR1
, K2_FCR1_FW_CLK_ENABLE
);
1387 static long g5_mpic_enable(struct device_node
*node
, long param
, long value
)
1389 unsigned long flags
;
1390 struct device_node
*parent
= of_get_parent(node
);
1395 is_u3
= of_node_name_eq(parent
, "u3") || of_node_name_eq(parent
, "u4");
1396 of_node_put(parent
);
1401 UN_BIS(U3_TOGGLE_REG
, U3_MPIC_RESET
| U3_MPIC_OUTPUT_ENABLE
);
1407 static long g5_eth_phy_reset(struct device_node
*node
, long param
, long value
)
1409 struct macio_chip
*macio
= &macio_chips
[0];
1410 struct device_node
*phy
;
1414 * We must not reset the combo PHYs, only the BCM5221 found in
1417 phy
= of_get_next_child(node
, NULL
);
1420 need_reset
= of_device_is_compatible(phy
, "B5221");
1425 /* PHY reset is GPIO 29, not in device-tree unfortunately */
1426 MACIO_OUT8(K2_GPIO_EXTINT_0
+ 29,
1427 KEYLARGO_GPIO_OUTPUT_ENABLE
| KEYLARGO_GPIO_OUTOUT_DATA
);
1428 /* Thankfully, this is now always called at a time when we can
1429 * schedule by sungem.
1432 MACIO_OUT8(K2_GPIO_EXTINT_0
+ 29, 0);
1437 static long g5_i2s_enable(struct device_node
*node
, long param
, long value
)
1439 /* Very crude implementation for now */
1440 struct macio_chip
*macio
= &macio_chips
[0];
1441 unsigned long flags
;
1445 K2_FCR1_I2S0_CELL_ENABLE
|
1446 K2_FCR1_I2S0_CLK_ENABLE_BIT
| K2_FCR1_I2S0_ENABLE
,
1447 KL3_I2S0_CLK18_ENABLE
1449 { KL0_SCC_A_INTF_ENABLE
,
1450 K2_FCR1_I2S1_CELL_ENABLE
|
1451 K2_FCR1_I2S1_CLK_ENABLE_BIT
| K2_FCR1_I2S1_ENABLE
,
1452 KL3_I2S1_CLK18_ENABLE
1454 { KL0_SCC_B_INTF_ENABLE
,
1455 SH_FCR1_I2S2_CELL_ENABLE
|
1456 SH_FCR1_I2S2_CLK_ENABLE_BIT
| SH_FCR1_I2S2_ENABLE
,
1457 SH_FCR3_I2S2_CLK18_ENABLE
1461 if (macio
->type
!= macio_keylargo2
&& macio
->type
!= macio_shasta
)
1463 if (strncmp(node
->name
, "i2s-", 4))
1465 cell
= node
->name
[4] - 'a';
1471 if (macio
->type
== macio_shasta
)
1480 MACIO_BIC(KEYLARGO_FCR0
, fcrs
[cell
][0]);
1481 MACIO_BIS(KEYLARGO_FCR1
, fcrs
[cell
][1]);
1482 MACIO_BIS(KEYLARGO_FCR3
, fcrs
[cell
][2]);
1484 MACIO_BIC(KEYLARGO_FCR3
, fcrs
[cell
][2]);
1485 MACIO_BIC(KEYLARGO_FCR1
, fcrs
[cell
][1]);
1486 MACIO_BIS(KEYLARGO_FCR0
, fcrs
[cell
][0]);
1496 static long g5_reset_cpu(struct device_node
*node
, long param
, long value
)
1498 unsigned int reset_io
= 0;
1499 unsigned long flags
;
1500 struct macio_chip
*macio
;
1501 struct device_node
*np
;
1503 macio
= &macio_chips
[0];
1504 if (macio
->type
!= macio_keylargo2
&& macio
->type
!= macio_shasta
)
1507 for_each_of_cpu_node(np
) {
1508 const u32
*num
= of_get_property(np
, "reg", NULL
);
1509 const u32
*rst
= of_get_property(np
, "soft-reset", NULL
);
1510 if (num
== NULL
|| rst
== NULL
)
1512 if (param
== *num
) {
1517 if (np
== NULL
|| reset_io
== 0)
1521 MACIO_OUT8(reset_io
, KEYLARGO_GPIO_OUTPUT_ENABLE
);
1522 (void)MACIO_IN8(reset_io
);
1524 MACIO_OUT8(reset_io
, 0);
1525 (void)MACIO_IN8(reset_io
);
1530 #endif /* CONFIG_SMP */
1533 * This can be called from pmac_smp so isn't static
1535 * This takes the second CPU off the bus on dual CPU machines
1538 void g5_phy_disable_cpu1(void)
1540 if (uninorth_maj
== 3)
1541 UN_OUT(U3_API_PHY_CONFIG_1
, 0);
1543 #endif /* CONFIG_PPC64 */
1545 #ifndef CONFIG_PPC64
1549 static u32 save_gpio_levels
[2];
1550 static u8 save_gpio_extint
[KEYLARGO_GPIO_EXTINT_CNT
];
1551 static u8 save_gpio_normal
[KEYLARGO_GPIO_CNT
];
1552 static u32 save_unin_clock_ctl
;
1554 static void keylargo_shutdown(struct macio_chip
*macio
, int sleep_mode
)
1560 MACIO_BIS(KEYLARGO_FCR0
, KL0_USB_REF_SUSPEND
);
1561 (void)MACIO_IN32(KEYLARGO_FCR0
);
1565 MACIO_BIC(KEYLARGO_FCR0
,KL0_SCCA_ENABLE
| KL0_SCCB_ENABLE
|
1566 KL0_SCC_CELL_ENABLE
|
1567 KL0_IRDA_ENABLE
| KL0_IRDA_CLK32_ENABLE
|
1568 KL0_IRDA_CLK19_ENABLE
);
1570 MACIO_BIC(KEYLARGO_MBCR
, KL_MBCR_MB0_DEV_MASK
);
1571 MACIO_BIS(KEYLARGO_MBCR
, KL_MBCR_MB0_IDE_ENABLE
);
1573 MACIO_BIC(KEYLARGO_FCR1
,
1574 KL1_AUDIO_SEL_22MCLK
| KL1_AUDIO_CLK_ENABLE_BIT
|
1575 KL1_AUDIO_CLK_OUT_ENABLE
| KL1_AUDIO_CELL_ENABLE
|
1576 KL1_I2S0_CELL_ENABLE
| KL1_I2S0_CLK_ENABLE_BIT
|
1577 KL1_I2S0_ENABLE
| KL1_I2S1_CELL_ENABLE
|
1578 KL1_I2S1_CLK_ENABLE_BIT
| KL1_I2S1_ENABLE
|
1579 KL1_EIDE0_ENABLE
| KL1_EIDE0_RESET_N
|
1580 KL1_EIDE1_ENABLE
| KL1_EIDE1_RESET_N
|
1583 MACIO_BIS(KEYLARGO_FCR2
, KL2_ALT_DATA_OUT
);
1584 MACIO_BIC(KEYLARGO_FCR2
, KL2_IOBUS_ENABLE
);
1586 temp
= MACIO_IN32(KEYLARGO_FCR3
);
1587 if (macio
->rev
>= 2) {
1588 temp
|= KL3_SHUTDOWN_PLL2X
;
1590 temp
|= KL3_SHUTDOWN_PLL_TOTAL
;
1593 temp
|= KL3_SHUTDOWN_PLLKW6
| KL3_SHUTDOWN_PLLKW4
|
1594 KL3_SHUTDOWN_PLLKW35
;
1596 temp
|= KL3_SHUTDOWN_PLLKW12
;
1597 temp
&= ~(KL3_CLK66_ENABLE
| KL3_CLK49_ENABLE
| KL3_CLK45_ENABLE
1598 | KL3_CLK31_ENABLE
| KL3_I2S1_CLK18_ENABLE
| KL3_I2S0_CLK18_ENABLE
);
1600 temp
&= ~(KL3_TIMER_CLK18_ENABLE
| KL3_VIA_CLK16_ENABLE
);
1601 MACIO_OUT32(KEYLARGO_FCR3
, temp
);
1603 /* Flush posted writes & wait a bit */
1604 (void)MACIO_IN32(KEYLARGO_FCR0
); mdelay(1);
1607 static void pangea_shutdown(struct macio_chip
*macio
, int sleep_mode
)
1611 MACIO_BIC(KEYLARGO_FCR0
,KL0_SCCA_ENABLE
| KL0_SCCB_ENABLE
|
1612 KL0_SCC_CELL_ENABLE
|
1613 KL0_USB0_CELL_ENABLE
| KL0_USB1_CELL_ENABLE
);
1615 MACIO_BIC(KEYLARGO_FCR1
,
1616 KL1_AUDIO_SEL_22MCLK
| KL1_AUDIO_CLK_ENABLE_BIT
|
1617 KL1_AUDIO_CLK_OUT_ENABLE
| KL1_AUDIO_CELL_ENABLE
|
1618 KL1_I2S0_CELL_ENABLE
| KL1_I2S0_CLK_ENABLE_BIT
|
1619 KL1_I2S0_ENABLE
| KL1_I2S1_CELL_ENABLE
|
1620 KL1_I2S1_CLK_ENABLE_BIT
| KL1_I2S1_ENABLE
|
1622 if (pmac_mb
.board_flags
& PMAC_MB_MOBILE
)
1623 MACIO_BIC(KEYLARGO_FCR1
, KL1_UIDE_RESET_N
);
1625 MACIO_BIS(KEYLARGO_FCR2
, KL2_ALT_DATA_OUT
);
1627 temp
= MACIO_IN32(KEYLARGO_FCR3
);
1628 temp
|= KL3_SHUTDOWN_PLLKW6
| KL3_SHUTDOWN_PLLKW4
|
1629 KL3_SHUTDOWN_PLLKW35
;
1630 temp
&= ~(KL3_CLK49_ENABLE
| KL3_CLK45_ENABLE
| KL3_CLK31_ENABLE
1631 | KL3_I2S0_CLK18_ENABLE
| KL3_I2S1_CLK18_ENABLE
);
1633 temp
&= ~(KL3_VIA_CLK16_ENABLE
| KL3_TIMER_CLK18_ENABLE
);
1634 MACIO_OUT32(KEYLARGO_FCR3
, temp
);
1636 /* Flush posted writes & wait a bit */
1637 (void)MACIO_IN32(KEYLARGO_FCR0
); mdelay(1);
1640 static void intrepid_shutdown(struct macio_chip
*macio
, int sleep_mode
)
1644 MACIO_BIC(KEYLARGO_FCR0
,KL0_SCCA_ENABLE
| KL0_SCCB_ENABLE
|
1645 KL0_SCC_CELL_ENABLE
);
1647 MACIO_BIC(KEYLARGO_FCR1
,
1648 KL1_I2S0_CELL_ENABLE
| KL1_I2S0_CLK_ENABLE_BIT
|
1649 KL1_I2S0_ENABLE
| KL1_I2S1_CELL_ENABLE
|
1650 KL1_I2S1_CLK_ENABLE_BIT
| KL1_I2S1_ENABLE
|
1652 if (pmac_mb
.board_flags
& PMAC_MB_MOBILE
)
1653 MACIO_BIC(KEYLARGO_FCR1
, KL1_UIDE_RESET_N
);
1655 temp
= MACIO_IN32(KEYLARGO_FCR3
);
1656 temp
&= ~(KL3_CLK49_ENABLE
| KL3_CLK45_ENABLE
|
1657 KL3_I2S1_CLK18_ENABLE
| KL3_I2S0_CLK18_ENABLE
);
1659 temp
&= ~(KL3_TIMER_CLK18_ENABLE
| KL3_IT_VIA_CLK32_ENABLE
);
1660 MACIO_OUT32(KEYLARGO_FCR3
, temp
);
1662 /* Flush posted writes & wait a bit */
1663 (void)MACIO_IN32(KEYLARGO_FCR0
);
1671 struct macio_chip
*macio
;
1674 macio
= &macio_chips
[0];
1675 if (macio
->type
!= macio_keylargo
&& macio
->type
!= macio_pangea
&&
1676 macio
->type
!= macio_intrepid
)
1679 /* We power off the wireless slot in case it was not done
1680 * by the driver. We don't power it on automatically however
1682 if (macio
->flags
& MACIO_FLAG_AIRPORT_ON
)
1683 core99_airport_enable(macio
->of_node
, 0, 0);
1685 /* We power off the FW cable. Should be done by the driver... */
1686 if (macio
->flags
& MACIO_FLAG_FW_SUPPORTED
) {
1687 core99_firewire_enable(NULL
, 0, 0);
1688 core99_firewire_cable_power(NULL
, 0, 0);
1691 /* We make sure int. modem is off (in case driver lost it) */
1692 if (macio
->type
== macio_keylargo
)
1693 core99_modem_enable(macio
->of_node
, 0, 0);
1695 pangea_modem_enable(macio
->of_node
, 0, 0);
1697 /* We make sure the sound is off as well */
1698 core99_sound_chip_enable(macio
->of_node
, 0, 0);
1701 * Save various bits of KeyLargo
1704 /* Save the state of the various GPIOs */
1705 save_gpio_levels
[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0
);
1706 save_gpio_levels
[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1
);
1707 for (i
=0; i
<KEYLARGO_GPIO_EXTINT_CNT
; i
++)
1708 save_gpio_extint
[i
] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0
+i
);
1709 for (i
=0; i
<KEYLARGO_GPIO_CNT
; i
++)
1710 save_gpio_normal
[i
] = MACIO_IN8(KEYLARGO_GPIO_0
+i
);
1713 if (macio
->type
== macio_keylargo
)
1714 save_mbcr
= MACIO_IN32(KEYLARGO_MBCR
);
1715 save_fcr
[0] = MACIO_IN32(KEYLARGO_FCR0
);
1716 save_fcr
[1] = MACIO_IN32(KEYLARGO_FCR1
);
1717 save_fcr
[2] = MACIO_IN32(KEYLARGO_FCR2
);
1718 save_fcr
[3] = MACIO_IN32(KEYLARGO_FCR3
);
1719 save_fcr
[4] = MACIO_IN32(KEYLARGO_FCR4
);
1720 if (macio
->type
== macio_pangea
|| macio
->type
== macio_intrepid
)
1721 save_fcr
[5] = MACIO_IN32(KEYLARGO_FCR5
);
1723 /* Save state & config of DBDMA channels */
1724 dbdma_save(macio
, save_dbdma
);
1727 * Turn off as much as we can
1729 if (macio
->type
== macio_pangea
)
1730 pangea_shutdown(macio
, 1);
1731 else if (macio
->type
== macio_intrepid
)
1732 intrepid_shutdown(macio
, 1);
1733 else if (macio
->type
== macio_keylargo
)
1734 keylargo_shutdown(macio
, 1);
1737 * Put the host bridge to sleep
1740 save_unin_clock_ctl
= UN_IN(UNI_N_CLOCK_CNTL
);
1741 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
1744 UN_OUT(UNI_N_CLOCK_CNTL
, save_unin_clock_ctl
&
1745 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW
/*|UNI_N_CLOCK_CNTL_PCI*/));
1747 UN_OUT(UNI_N_HWINIT_STATE
, UNI_N_HWINIT_STATE_SLEEPING
);
1748 UN_OUT(UNI_N_POWER_MGT
, UNI_N_POWER_MGT_SLEEP
);
1752 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
1754 if (pmac_mb
.model_id
== PMAC_TYPE_SAWTOOTH
) {
1755 MACIO_BIS(0x506e0, 0x00400000);
1756 MACIO_BIS(0x506e0, 0x80000000);
1762 core99_wake_up(void)
1764 struct macio_chip
*macio
;
1767 macio
= &macio_chips
[0];
1768 if (macio
->type
!= macio_keylargo
&& macio
->type
!= macio_pangea
&&
1769 macio
->type
!= macio_intrepid
)
1773 * Wakeup the host bridge
1775 UN_OUT(UNI_N_POWER_MGT
, UNI_N_POWER_MGT_NORMAL
);
1777 UN_OUT(UNI_N_HWINIT_STATE
, UNI_N_HWINIT_STATE_RUNNING
);
1784 if (macio
->type
== macio_keylargo
) {
1785 MACIO_OUT32(KEYLARGO_MBCR
, save_mbcr
);
1786 (void)MACIO_IN32(KEYLARGO_MBCR
); udelay(10);
1788 MACIO_OUT32(KEYLARGO_FCR0
, save_fcr
[0]);
1789 (void)MACIO_IN32(KEYLARGO_FCR0
); udelay(10);
1790 MACIO_OUT32(KEYLARGO_FCR1
, save_fcr
[1]);
1791 (void)MACIO_IN32(KEYLARGO_FCR1
); udelay(10);
1792 MACIO_OUT32(KEYLARGO_FCR2
, save_fcr
[2]);
1793 (void)MACIO_IN32(KEYLARGO_FCR2
); udelay(10);
1794 MACIO_OUT32(KEYLARGO_FCR3
, save_fcr
[3]);
1795 (void)MACIO_IN32(KEYLARGO_FCR3
); udelay(10);
1796 MACIO_OUT32(KEYLARGO_FCR4
, save_fcr
[4]);
1797 (void)MACIO_IN32(KEYLARGO_FCR4
); udelay(10);
1798 if (macio
->type
== macio_pangea
|| macio
->type
== macio_intrepid
) {
1799 MACIO_OUT32(KEYLARGO_FCR5
, save_fcr
[5]);
1800 (void)MACIO_IN32(KEYLARGO_FCR5
); udelay(10);
1803 dbdma_restore(macio
, save_dbdma
);
1805 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0
, save_gpio_levels
[0]);
1806 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1
, save_gpio_levels
[1]);
1807 for (i
=0; i
<KEYLARGO_GPIO_EXTINT_CNT
; i
++)
1808 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0
+i
, save_gpio_extint
[i
]);
1809 for (i
=0; i
<KEYLARGO_GPIO_CNT
; i
++)
1810 MACIO_OUT8(KEYLARGO_GPIO_0
+i
, save_gpio_normal
[i
]);
1812 /* FIXME more black magic with OpenPIC ... */
1813 if (pmac_mb
.model_id
== PMAC_TYPE_SAWTOOTH
) {
1814 MACIO_BIC(0x506e0, 0x00400000);
1815 MACIO_BIC(0x506e0, 0x80000000);
1818 UN_OUT(UNI_N_CLOCK_CNTL
, save_unin_clock_ctl
);
1824 #endif /* CONFIG_PM */
1827 core99_sleep_state(struct device_node
*node
, long param
, long value
)
1829 /* Param == 1 means to enter the "fake sleep" mode that is
1830 * used for CPU speed switch
1834 UN_OUT(UNI_N_HWINIT_STATE
, UNI_N_HWINIT_STATE_SLEEPING
);
1835 UN_OUT(UNI_N_POWER_MGT
, UNI_N_POWER_MGT_IDLE2
);
1837 UN_OUT(UNI_N_POWER_MGT
, UNI_N_POWER_MGT_NORMAL
);
1839 UN_OUT(UNI_N_HWINIT_STATE
, UNI_N_HWINIT_STATE_RUNNING
);
1844 if ((pmac_mb
.board_flags
& PMAC_MB_CAN_SLEEP
) == 0)
1849 return core99_sleep();
1850 else if (value
== 0)
1851 return core99_wake_up();
1853 #endif /* CONFIG_PM */
1857 #endif /* CONFIG_PPC64 */
1860 generic_dev_can_wake(struct device_node
*node
, long param
, long value
)
1862 /* Todo: eventually check we are really dealing with on-board
1866 if (pmac_mb
.board_flags
& PMAC_MB_MAY_SLEEP
)
1867 pmac_mb
.board_flags
|= PMAC_MB_CAN_SLEEP
;
1871 static long generic_get_mb_info(struct device_node
*node
, long param
, long value
)
1874 case PMAC_MB_INFO_MODEL
:
1875 return pmac_mb
.model_id
;
1876 case PMAC_MB_INFO_FLAGS
:
1877 return pmac_mb
.board_flags
;
1878 case PMAC_MB_INFO_NAME
:
1879 /* hack hack hack... but should work */
1880 *((const char **)value
) = pmac_mb
.model_name
;
1891 /* Used on any machine
1893 static struct feature_table_entry any_features
[] = {
1894 { PMAC_FTR_GET_MB_INFO
, generic_get_mb_info
},
1895 { PMAC_FTR_DEVICE_CAN_WAKE
, generic_dev_can_wake
},
1899 #ifndef CONFIG_PPC64
1901 /* OHare based motherboards. Currently, we only use these on the
1902 * 2400,3400 and 3500 series powerbooks. Some older desktops seem
1903 * to have issues with turning on/off those asic cells
1905 static struct feature_table_entry ohare_features
[] = {
1906 { PMAC_FTR_SCC_ENABLE
, ohare_htw_scc_enable
},
1907 { PMAC_FTR_SWIM3_ENABLE
, ohare_floppy_enable
},
1908 { PMAC_FTR_MESH_ENABLE
, ohare_mesh_enable
},
1909 { PMAC_FTR_IDE_ENABLE
, ohare_ide_enable
},
1910 { PMAC_FTR_IDE_RESET
, ohare_ide_reset
},
1911 { PMAC_FTR_SLEEP_STATE
, ohare_sleep_state
},
1915 /* Heathrow desktop machines (Beige G3).
1916 * Separated as some features couldn't be properly tested
1917 * and the serial port control bits appear to confuse it.
1919 static struct feature_table_entry heathrow_desktop_features
[] = {
1920 { PMAC_FTR_SWIM3_ENABLE
, heathrow_floppy_enable
},
1921 { PMAC_FTR_MESH_ENABLE
, heathrow_mesh_enable
},
1922 { PMAC_FTR_IDE_ENABLE
, heathrow_ide_enable
},
1923 { PMAC_FTR_IDE_RESET
, heathrow_ide_reset
},
1924 { PMAC_FTR_BMAC_ENABLE
, heathrow_bmac_enable
},
1928 /* Heathrow based laptop, that is the Wallstreet and mainstreet
1931 static struct feature_table_entry heathrow_laptop_features
[] = {
1932 { PMAC_FTR_SCC_ENABLE
, ohare_htw_scc_enable
},
1933 { PMAC_FTR_MODEM_ENABLE
, heathrow_modem_enable
},
1934 { PMAC_FTR_SWIM3_ENABLE
, heathrow_floppy_enable
},
1935 { PMAC_FTR_MESH_ENABLE
, heathrow_mesh_enable
},
1936 { PMAC_FTR_IDE_ENABLE
, heathrow_ide_enable
},
1937 { PMAC_FTR_IDE_RESET
, heathrow_ide_reset
},
1938 { PMAC_FTR_BMAC_ENABLE
, heathrow_bmac_enable
},
1939 { PMAC_FTR_SOUND_CHIP_ENABLE
, heathrow_sound_enable
},
1940 { PMAC_FTR_SLEEP_STATE
, heathrow_sleep_state
},
1944 /* Paddington based machines
1945 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
1947 static struct feature_table_entry paddington_features
[] = {
1948 { PMAC_FTR_SCC_ENABLE
, ohare_htw_scc_enable
},
1949 { PMAC_FTR_MODEM_ENABLE
, heathrow_modem_enable
},
1950 { PMAC_FTR_SWIM3_ENABLE
, heathrow_floppy_enable
},
1951 { PMAC_FTR_MESH_ENABLE
, heathrow_mesh_enable
},
1952 { PMAC_FTR_IDE_ENABLE
, heathrow_ide_enable
},
1953 { PMAC_FTR_IDE_RESET
, heathrow_ide_reset
},
1954 { PMAC_FTR_BMAC_ENABLE
, heathrow_bmac_enable
},
1955 { PMAC_FTR_SOUND_CHIP_ENABLE
, heathrow_sound_enable
},
1956 { PMAC_FTR_SLEEP_STATE
, heathrow_sleep_state
},
1960 /* Core99 & MacRISC 2 machines (all machines released since the
1961 * iBook (included), that is all AGP machines, except pangea
1962 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
1963 * used on iBook2 & iMac "flow power".
1965 static struct feature_table_entry core99_features
[] = {
1966 { PMAC_FTR_SCC_ENABLE
, core99_scc_enable
},
1967 { PMAC_FTR_MODEM_ENABLE
, core99_modem_enable
},
1968 { PMAC_FTR_IDE_ENABLE
, core99_ide_enable
},
1969 { PMAC_FTR_IDE_RESET
, core99_ide_reset
},
1970 { PMAC_FTR_GMAC_ENABLE
, core99_gmac_enable
},
1971 { PMAC_FTR_GMAC_PHY_RESET
, core99_gmac_phy_reset
},
1972 { PMAC_FTR_SOUND_CHIP_ENABLE
, core99_sound_chip_enable
},
1973 { PMAC_FTR_AIRPORT_ENABLE
, core99_airport_enable
},
1974 { PMAC_FTR_USB_ENABLE
, core99_usb_enable
},
1975 { PMAC_FTR_1394_ENABLE
, core99_firewire_enable
},
1976 { PMAC_FTR_1394_CABLE_POWER
, core99_firewire_cable_power
},
1978 { PMAC_FTR_SLEEP_STATE
, core99_sleep_state
},
1981 { PMAC_FTR_RESET_CPU
, core99_reset_cpu
},
1982 #endif /* CONFIG_SMP */
1983 { PMAC_FTR_READ_GPIO
, core99_read_gpio
},
1984 { PMAC_FTR_WRITE_GPIO
, core99_write_gpio
},
1990 static struct feature_table_entry rackmac_features
[] = {
1991 { PMAC_FTR_SCC_ENABLE
, core99_scc_enable
},
1992 { PMAC_FTR_IDE_ENABLE
, core99_ide_enable
},
1993 { PMAC_FTR_IDE_RESET
, core99_ide_reset
},
1994 { PMAC_FTR_GMAC_ENABLE
, core99_gmac_enable
},
1995 { PMAC_FTR_GMAC_PHY_RESET
, core99_gmac_phy_reset
},
1996 { PMAC_FTR_USB_ENABLE
, core99_usb_enable
},
1997 { PMAC_FTR_1394_ENABLE
, core99_firewire_enable
},
1998 { PMAC_FTR_1394_CABLE_POWER
, core99_firewire_cable_power
},
1999 { PMAC_FTR_SLEEP_STATE
, core99_sleep_state
},
2001 { PMAC_FTR_RESET_CPU
, core99_reset_cpu
},
2002 #endif /* CONFIG_SMP */
2003 { PMAC_FTR_READ_GPIO
, core99_read_gpio
},
2004 { PMAC_FTR_WRITE_GPIO
, core99_write_gpio
},
2010 static struct feature_table_entry pangea_features
[] = {
2011 { PMAC_FTR_SCC_ENABLE
, core99_scc_enable
},
2012 { PMAC_FTR_MODEM_ENABLE
, pangea_modem_enable
},
2013 { PMAC_FTR_IDE_ENABLE
, core99_ide_enable
},
2014 { PMAC_FTR_IDE_RESET
, core99_ide_reset
},
2015 { PMAC_FTR_GMAC_ENABLE
, core99_gmac_enable
},
2016 { PMAC_FTR_GMAC_PHY_RESET
, core99_gmac_phy_reset
},
2017 { PMAC_FTR_SOUND_CHIP_ENABLE
, core99_sound_chip_enable
},
2018 { PMAC_FTR_AIRPORT_ENABLE
, core99_airport_enable
},
2019 { PMAC_FTR_USB_ENABLE
, core99_usb_enable
},
2020 { PMAC_FTR_1394_ENABLE
, core99_firewire_enable
},
2021 { PMAC_FTR_1394_CABLE_POWER
, core99_firewire_cable_power
},
2022 { PMAC_FTR_SLEEP_STATE
, core99_sleep_state
},
2023 { PMAC_FTR_READ_GPIO
, core99_read_gpio
},
2024 { PMAC_FTR_WRITE_GPIO
, core99_write_gpio
},
2028 /* Intrepid features
2030 static struct feature_table_entry intrepid_features
[] = {
2031 { PMAC_FTR_SCC_ENABLE
, core99_scc_enable
},
2032 { PMAC_FTR_MODEM_ENABLE
, pangea_modem_enable
},
2033 { PMAC_FTR_IDE_ENABLE
, core99_ide_enable
},
2034 { PMAC_FTR_IDE_RESET
, core99_ide_reset
},
2035 { PMAC_FTR_GMAC_ENABLE
, core99_gmac_enable
},
2036 { PMAC_FTR_GMAC_PHY_RESET
, core99_gmac_phy_reset
},
2037 { PMAC_FTR_SOUND_CHIP_ENABLE
, core99_sound_chip_enable
},
2038 { PMAC_FTR_AIRPORT_ENABLE
, core99_airport_enable
},
2039 { PMAC_FTR_USB_ENABLE
, core99_usb_enable
},
2040 { PMAC_FTR_1394_ENABLE
, core99_firewire_enable
},
2041 { PMAC_FTR_1394_CABLE_POWER
, core99_firewire_cable_power
},
2042 { PMAC_FTR_SLEEP_STATE
, core99_sleep_state
},
2043 { PMAC_FTR_READ_GPIO
, core99_read_gpio
},
2044 { PMAC_FTR_WRITE_GPIO
, core99_write_gpio
},
2045 { PMAC_FTR_AACK_DELAY_ENABLE
, intrepid_aack_delay_enable
},
2049 #else /* CONFIG_PPC64 */
2053 static struct feature_table_entry g5_features
[] = {
2054 { PMAC_FTR_GMAC_ENABLE
, g5_gmac_enable
},
2055 { PMAC_FTR_1394_ENABLE
, g5_fw_enable
},
2056 { PMAC_FTR_ENABLE_MPIC
, g5_mpic_enable
},
2057 { PMAC_FTR_GMAC_PHY_RESET
, g5_eth_phy_reset
},
2058 { PMAC_FTR_SOUND_CHIP_ENABLE
, g5_i2s_enable
},
2060 { PMAC_FTR_RESET_CPU
, g5_reset_cpu
},
2061 #endif /* CONFIG_SMP */
2062 { PMAC_FTR_READ_GPIO
, core99_read_gpio
},
2063 { PMAC_FTR_WRITE_GPIO
, core99_write_gpio
},
2067 #endif /* CONFIG_PPC64 */
2069 static struct pmac_mb_def pmac_mb_defs
[] = {
2070 #ifndef CONFIG_PPC64
2075 { "AAPL,8500", "PowerMac 8500/8600",
2076 PMAC_TYPE_PSURGE
, NULL
,
2079 { "AAPL,9500", "PowerMac 9500/9600",
2080 PMAC_TYPE_PSURGE
, NULL
,
2083 { "AAPL,7200", "PowerMac 7200",
2084 PMAC_TYPE_PSURGE
, NULL
,
2087 { "AAPL,7300", "PowerMac 7200/7300",
2088 PMAC_TYPE_PSURGE
, NULL
,
2091 { "AAPL,7500", "PowerMac 7500",
2092 PMAC_TYPE_PSURGE
, NULL
,
2095 { "AAPL,ShinerESB", "Apple Network Server",
2096 PMAC_TYPE_ANS
, NULL
,
2099 { "AAPL,e407", "Alchemy",
2100 PMAC_TYPE_ALCHEMY
, NULL
,
2103 { "AAPL,e411", "Gazelle",
2104 PMAC_TYPE_GAZELLE
, NULL
,
2107 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)",
2108 PMAC_TYPE_GOSSAMER
, heathrow_desktop_features
,
2111 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)",
2112 PMAC_TYPE_SILK
, heathrow_desktop_features
,
2115 { "PowerMac1,1", "Blue&White G3",
2116 PMAC_TYPE_YOSEMITE
, paddington_features
,
2119 { "PowerMac1,2", "PowerMac G4 PCI Graphics",
2120 PMAC_TYPE_YIKES
, paddington_features
,
2123 { "PowerMac2,1", "iMac FireWire",
2124 PMAC_TYPE_FW_IMAC
, core99_features
,
2125 PMAC_MB_MAY_SLEEP
| PMAC_MB_OLD_CORE99
2127 { "PowerMac2,2", "iMac FireWire",
2128 PMAC_TYPE_FW_IMAC
, core99_features
,
2129 PMAC_MB_MAY_SLEEP
| PMAC_MB_OLD_CORE99
2131 { "PowerMac3,1", "PowerMac G4 AGP Graphics",
2132 PMAC_TYPE_SAWTOOTH
, core99_features
,
2135 { "PowerMac3,2", "PowerMac G4 AGP Graphics",
2136 PMAC_TYPE_SAWTOOTH
, core99_features
,
2137 PMAC_MB_MAY_SLEEP
| PMAC_MB_OLD_CORE99
2139 { "PowerMac3,3", "PowerMac G4 AGP Graphics",
2140 PMAC_TYPE_SAWTOOTH
, core99_features
,
2141 PMAC_MB_MAY_SLEEP
| PMAC_MB_OLD_CORE99
2143 { "PowerMac3,4", "PowerMac G4 Silver",
2144 PMAC_TYPE_QUICKSILVER
, core99_features
,
2147 { "PowerMac3,5", "PowerMac G4 Silver",
2148 PMAC_TYPE_QUICKSILVER
, core99_features
,
2151 { "PowerMac3,6", "PowerMac G4 Windtunnel",
2152 PMAC_TYPE_WINDTUNNEL
, core99_features
,
2155 { "PowerMac4,1", "iMac \"Flower Power\"",
2156 PMAC_TYPE_PANGEA_IMAC
, pangea_features
,
2159 { "PowerMac4,2", "Flat panel iMac",
2160 PMAC_TYPE_FLAT_PANEL_IMAC
, pangea_features
,
2163 { "PowerMac4,4", "eMac",
2164 PMAC_TYPE_EMAC
, core99_features
,
2167 { "PowerMac5,1", "PowerMac G4 Cube",
2168 PMAC_TYPE_CUBE
, core99_features
,
2169 PMAC_MB_MAY_SLEEP
| PMAC_MB_OLD_CORE99
2171 { "PowerMac6,1", "Flat panel iMac",
2172 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2175 { "PowerMac6,3", "Flat panel iMac",
2176 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2179 { "PowerMac6,4", "eMac",
2180 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2183 { "PowerMac10,1", "Mac mini",
2184 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2187 { "PowerMac10,2", "Mac mini (Late 2005)",
2188 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2191 { "iMac,1", "iMac (first generation)",
2192 PMAC_TYPE_ORIG_IMAC
, paddington_features
,
2200 { "RackMac1,1", "XServe",
2201 PMAC_TYPE_RACKMAC
, rackmac_features
,
2204 { "RackMac1,2", "XServe rev. 2",
2205 PMAC_TYPE_RACKMAC
, rackmac_features
,
2213 { "AAPL,3400/2400", "PowerBook 3400",
2214 PMAC_TYPE_HOOPER
, ohare_features
,
2215 PMAC_MB_CAN_SLEEP
| PMAC_MB_MOBILE
2217 { "AAPL,3500", "PowerBook 3500",
2218 PMAC_TYPE_KANGA
, ohare_features
,
2219 PMAC_MB_CAN_SLEEP
| PMAC_MB_MOBILE
2221 { "AAPL,PowerBook1998", "PowerBook Wallstreet",
2222 PMAC_TYPE_WALLSTREET
, heathrow_laptop_features
,
2223 PMAC_MB_CAN_SLEEP
| PMAC_MB_MOBILE
2225 { "PowerBook1,1", "PowerBook 101 (Lombard)",
2226 PMAC_TYPE_101_PBOOK
, paddington_features
,
2227 PMAC_MB_CAN_SLEEP
| PMAC_MB_MOBILE
2229 { "PowerBook2,1", "iBook (first generation)",
2230 PMAC_TYPE_ORIG_IBOOK
, core99_features
,
2231 PMAC_MB_CAN_SLEEP
| PMAC_MB_OLD_CORE99
| PMAC_MB_MOBILE
2233 { "PowerBook2,2", "iBook FireWire",
2234 PMAC_TYPE_FW_IBOOK
, core99_features
,
2235 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
|
2236 PMAC_MB_OLD_CORE99
| PMAC_MB_MOBILE
2238 { "PowerBook3,1", "PowerBook Pismo",
2239 PMAC_TYPE_PISMO
, core99_features
,
2240 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
|
2241 PMAC_MB_OLD_CORE99
| PMAC_MB_MOBILE
2243 { "PowerBook3,2", "PowerBook Titanium",
2244 PMAC_TYPE_TITANIUM
, core99_features
,
2245 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
2247 { "PowerBook3,3", "PowerBook Titanium II",
2248 PMAC_TYPE_TITANIUM2
, core99_features
,
2249 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
2251 { "PowerBook3,4", "PowerBook Titanium III",
2252 PMAC_TYPE_TITANIUM3
, core99_features
,
2253 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
2255 { "PowerBook3,5", "PowerBook Titanium IV",
2256 PMAC_TYPE_TITANIUM4
, core99_features
,
2257 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
2259 { "PowerBook4,1", "iBook 2",
2260 PMAC_TYPE_IBOOK2
, pangea_features
,
2261 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
2263 { "PowerBook4,2", "iBook 2",
2264 PMAC_TYPE_IBOOK2
, pangea_features
,
2265 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
2267 { "PowerBook4,3", "iBook 2 rev. 2",
2268 PMAC_TYPE_IBOOK2
, pangea_features
,
2269 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
2271 { "PowerBook5,1", "PowerBook G4 17\"",
2272 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2273 PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2275 { "PowerBook5,2", "PowerBook G4 15\"",
2276 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2277 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2279 { "PowerBook5,3", "PowerBook G4 17\"",
2280 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2281 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2283 { "PowerBook5,4", "PowerBook G4 15\"",
2284 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2285 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2287 { "PowerBook5,5", "PowerBook G4 17\"",
2288 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2289 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2291 { "PowerBook5,6", "PowerBook G4 15\"",
2292 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2293 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2295 { "PowerBook5,7", "PowerBook G4 17\"",
2296 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2297 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2299 { "PowerBook5,8", "PowerBook G4 15\"",
2300 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2301 PMAC_MB_MAY_SLEEP
| PMAC_MB_MOBILE
,
2303 { "PowerBook5,9", "PowerBook G4 17\"",
2304 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2305 PMAC_MB_MAY_SLEEP
| PMAC_MB_MOBILE
,
2307 { "PowerBook6,1", "PowerBook G4 12\"",
2308 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2309 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2311 { "PowerBook6,2", "PowerBook G4",
2312 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2313 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2315 { "PowerBook6,3", "iBook G4",
2316 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2317 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2319 { "PowerBook6,4", "PowerBook G4 12\"",
2320 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2321 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2323 { "PowerBook6,5", "iBook G4",
2324 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2325 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2327 { "PowerBook6,7", "iBook G4",
2328 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2329 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2331 { "PowerBook6,8", "PowerBook G4 12\"",
2332 PMAC_TYPE_UNKNOWN_INTREPID
, intrepid_features
,
2333 PMAC_MB_MAY_SLEEP
| PMAC_MB_HAS_FW_POWER
| PMAC_MB_MOBILE
,
2335 #else /* CONFIG_PPC64 */
2336 { "PowerMac7,2", "PowerMac G5",
2337 PMAC_TYPE_POWERMAC_G5
, g5_features
,
2341 { "PowerMac7,3", "PowerMac G5",
2342 PMAC_TYPE_POWERMAC_G5
, g5_features
,
2345 { "PowerMac8,1", "iMac G5",
2346 PMAC_TYPE_IMAC_G5
, g5_features
,
2349 { "PowerMac9,1", "PowerMac G5",
2350 PMAC_TYPE_POWERMAC_G5_U3L
, g5_features
,
2353 { "PowerMac11,2", "PowerMac G5 Dual Core",
2354 PMAC_TYPE_POWERMAC_G5_U3L
, g5_features
,
2357 { "PowerMac12,1", "iMac G5 (iSight)",
2358 PMAC_TYPE_POWERMAC_G5_U3L
, g5_features
,
2361 { "RackMac3,1", "XServe G5",
2362 PMAC_TYPE_XSERVE_G5
, g5_features
,
2365 #endif /* CONFIG_PPC64 */
2366 #endif /* CONFIG_PPC64 */
2370 * The toplevel feature_call callback
2372 long pmac_do_feature_call(unsigned int selector
, ...)
2374 struct device_node
*node
;
2377 feature_call func
= NULL
;
2380 if (pmac_mb
.features
)
2381 for (i
=0; pmac_mb
.features
[i
].function
; i
++)
2382 if (pmac_mb
.features
[i
].selector
== selector
) {
2383 func
= pmac_mb
.features
[i
].function
;
2387 for (i
=0; any_features
[i
].function
; i
++)
2388 if (any_features
[i
].selector
== selector
) {
2389 func
= any_features
[i
].function
;
2395 va_start(args
, selector
);
2396 node
= (struct device_node
*)va_arg(args
, void*);
2397 param
= va_arg(args
, long);
2398 value
= va_arg(args
, long);
2401 return func(node
, param
, value
);
2404 static int __init
probe_motherboard(void)
2407 struct macio_chip
*macio
= &macio_chips
[0];
2408 const char *model
= NULL
;
2409 struct device_node
*dt
;
2412 /* Lookup known motherboard type in device-tree. First try an
2413 * exact match on the "model" property, then try a "compatible"
2414 * match is none is found.
2416 dt
= of_find_node_by_name(NULL
, "device-tree");
2418 model
= of_get_property(dt
, "model", NULL
);
2419 for(i
=0; model
&& i
<ARRAY_SIZE(pmac_mb_defs
); i
++) {
2420 if (strcmp(model
, pmac_mb_defs
[i
].model_string
) == 0) {
2421 pmac_mb
= pmac_mb_defs
[i
];
2425 for(i
=0; i
<ARRAY_SIZE(pmac_mb_defs
); i
++) {
2426 if (of_machine_is_compatible(pmac_mb_defs
[i
].model_string
)) {
2427 pmac_mb
= pmac_mb_defs
[i
];
2432 /* Fallback to selection depending on mac-io chip type */
2433 switch(macio
->type
) {
2434 #ifndef CONFIG_PPC64
2435 case macio_grand_central
:
2436 pmac_mb
.model_id
= PMAC_TYPE_PSURGE
;
2437 pmac_mb
.model_name
= "Unknown PowerSurge";
2440 pmac_mb
.model_id
= PMAC_TYPE_UNKNOWN_OHARE
;
2441 pmac_mb
.model_name
= "Unknown OHare-based";
2443 case macio_heathrow
:
2444 pmac_mb
.model_id
= PMAC_TYPE_UNKNOWN_HEATHROW
;
2445 pmac_mb
.model_name
= "Unknown Heathrow-based";
2446 pmac_mb
.features
= heathrow_desktop_features
;
2448 case macio_paddington
:
2449 pmac_mb
.model_id
= PMAC_TYPE_UNKNOWN_PADDINGTON
;
2450 pmac_mb
.model_name
= "Unknown Paddington-based";
2451 pmac_mb
.features
= paddington_features
;
2453 case macio_keylargo
:
2454 pmac_mb
.model_id
= PMAC_TYPE_UNKNOWN_CORE99
;
2455 pmac_mb
.model_name
= "Unknown Keylargo-based";
2456 pmac_mb
.features
= core99_features
;
2459 pmac_mb
.model_id
= PMAC_TYPE_UNKNOWN_PANGEA
;
2460 pmac_mb
.model_name
= "Unknown Pangea-based";
2461 pmac_mb
.features
= pangea_features
;
2463 case macio_intrepid
:
2464 pmac_mb
.model_id
= PMAC_TYPE_UNKNOWN_INTREPID
;
2465 pmac_mb
.model_name
= "Unknown Intrepid-based";
2466 pmac_mb
.features
= intrepid_features
;
2468 #else /* CONFIG_PPC64 */
2469 case macio_keylargo2
:
2470 pmac_mb
.model_id
= PMAC_TYPE_UNKNOWN_K2
;
2471 pmac_mb
.model_name
= "Unknown K2-based";
2472 pmac_mb
.features
= g5_features
;
2475 pmac_mb
.model_id
= PMAC_TYPE_UNKNOWN_SHASTA
;
2476 pmac_mb
.model_name
= "Unknown Shasta-based";
2477 pmac_mb
.features
= g5_features
;
2479 #endif /* CONFIG_PPC64 */
2485 #ifndef CONFIG_PPC64
2486 /* Fixup Hooper vs. Comet */
2487 if (pmac_mb
.model_id
== PMAC_TYPE_HOOPER
) {
2488 u32 __iomem
* mach_id_ptr
= ioremap(0xf3000034, 4);
2493 /* Here, I used to disable the media-bay on comet. It
2494 * appears this is wrong, the floppy connector is actually
2495 * a kind of media-bay and works with the current driver.
2497 if (__raw_readl(mach_id_ptr
) & 0x20000000UL
)
2498 pmac_mb
.model_id
= PMAC_TYPE_COMET
;
2499 iounmap(mach_id_ptr
);
2502 /* Set default value of powersave_nap on machines that support it.
2503 * It appears that uninorth rev 3 has a problem with it, we don't
2504 * enable it on those. In theory, the flush-on-lock property is
2505 * supposed to be set when not supported, but I'm not very confident
2506 * that all Apple OF revs did it properly, I do it the paranoid way.
2508 if (uninorth_base
&& uninorth_rev
> 3) {
2509 struct device_node
*np
;
2511 for_each_of_cpu_node(np
) {
2514 /* Nap mode not supported on SMP */
2515 if (of_get_property(np
, "flush-on-lock", NULL
) ||
2527 printk(KERN_DEBUG
"Processor NAP mode on idle enabled.\n");
2529 /* On CPUs that support it (750FX), lowspeed by default during
2532 powersave_lowspeed
= 1;
2534 #else /* CONFIG_PPC64 */
2536 #endif /* CONFIG_PPC64 */
2538 /* Check for "mobile" machine */
2539 if (model
&& (strncmp(model
, "PowerBook", 9) == 0
2540 || strncmp(model
, "iBook", 5) == 0))
2541 pmac_mb
.board_flags
|= PMAC_MB_MOBILE
;
2544 printk(KERN_INFO
"PowerMac motherboard: %s\n", pmac_mb
.model_name
);
2550 /* Initialize the Core99 UniNorth host bridge and memory controller
2552 static void __init
probe_uninorth(void)
2555 phys_addr_t address
;
2556 unsigned long actrl
;
2558 /* Locate core99 Uni-N */
2559 uninorth_node
= of_find_node_by_name(NULL
, "uni-n");
2563 if (uninorth_node
== NULL
) {
2564 uninorth_node
= of_find_node_by_name(NULL
, "u3");
2568 if (uninorth_node
== NULL
) {
2569 uninorth_node
= of_find_node_by_name(NULL
, "u4");
2572 if (uninorth_node
== NULL
) {
2577 addrp
= of_get_property(uninorth_node
, "reg", NULL
);
2580 address
= of_translate_address(uninorth_node
, addrp
);
2583 uninorth_base
= ioremap(address
, 0x40000);
2584 if (uninorth_base
== NULL
)
2586 uninorth_rev
= in_be32(UN_REG(UNI_N_VERSION
));
2587 if (uninorth_maj
== 3 || uninorth_maj
== 4) {
2588 u3_ht_base
= ioremap(address
+ U3_HT_CONFIG_BASE
, 0x1000);
2589 if (u3_ht_base
== NULL
) {
2590 iounmap(uninorth_base
);
2595 printk(KERN_INFO
"Found %s memory controller & host bridge"
2596 " @ 0x%08x revision: 0x%02x\n", uninorth_maj
== 3 ? "U3" :
2597 uninorth_maj
== 4 ? "U4" : "UniNorth",
2598 (unsigned int)address
, uninorth_rev
);
2599 printk(KERN_INFO
"Mapped at 0x%08lx\n", (unsigned long)uninorth_base
);
2601 /* Set the arbitrer QAck delay according to what Apple does
2603 if (uninorth_rev
< 0x11) {
2604 actrl
= UN_IN(UNI_N_ARB_CTRL
) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK
;
2605 actrl
|= ((uninorth_rev
< 3) ? UNI_N_ARB_CTRL_QACK_DELAY105
:
2606 UNI_N_ARB_CTRL_QACK_DELAY
) <<
2607 UNI_N_ARB_CTRL_QACK_DELAY_SHIFT
;
2608 UN_OUT(UNI_N_ARB_CTRL
, actrl
);
2611 /* Some more magic as done by them in recent MacOS X on UniNorth
2612 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
2615 if ((uninorth_rev
>= 0x11 && uninorth_rev
<= 0x24) ||
2616 uninorth_rev
== 0xc0)
2617 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2620 static void __init
probe_one_macio(const char *name
, const char *compat
, int type
)
2622 struct device_node
* node
;
2624 volatile u32 __iomem
*base
;
2625 const u32
*addrp
, *revp
;
2629 for_each_node_by_name(node
, name
) {
2632 if (of_device_is_compatible(node
, compat
))
2637 for(i
=0; i
<MAX_MACIO_CHIPS
; i
++) {
2638 if (!macio_chips
[i
].of_node
)
2640 if (macio_chips
[i
].of_node
== node
)
2644 if (i
>= MAX_MACIO_CHIPS
) {
2645 printk(KERN_ERR
"pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2646 printk(KERN_ERR
"pmac_feature: %pOF skipped\n", node
);
2649 addrp
= of_get_pci_address(node
, 0, &size
, NULL
);
2650 if (addrp
== NULL
) {
2651 printk(KERN_ERR
"pmac_feature: %pOF: can't find base !\n",
2655 addr
= of_translate_address(node
, addrp
);
2657 printk(KERN_ERR
"pmac_feature: %pOF, can't translate base !\n",
2661 base
= ioremap(addr
, (unsigned long)size
);
2663 printk(KERN_ERR
"pmac_feature: %pOF, can't map mac-io chip !\n",
2667 if (type
== macio_keylargo
|| type
== macio_keylargo2
) {
2668 const u32
*did
= of_get_property(node
, "device-id", NULL
);
2669 if (*did
== 0x00000025)
2670 type
= macio_pangea
;
2671 if (*did
== 0x0000003e)
2672 type
= macio_intrepid
;
2673 if (*did
== 0x0000004f)
2674 type
= macio_shasta
;
2676 macio_chips
[i
].of_node
= node
;
2677 macio_chips
[i
].type
= type
;
2678 macio_chips
[i
].base
= base
;
2679 macio_chips
[i
].flags
= MACIO_FLAG_SCCA_ON
| MACIO_FLAG_SCCB_ON
;
2680 macio_chips
[i
].name
= macio_names
[type
];
2681 revp
= of_get_property(node
, "revision-id", NULL
);
2683 macio_chips
[i
].rev
= *revp
;
2684 printk(KERN_INFO
"Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2685 macio_names
[type
], macio_chips
[i
].rev
, macio_chips
[i
].base
);
2691 /* Warning, ordering is important */
2692 probe_one_macio("gc", NULL
, macio_grand_central
);
2693 probe_one_macio("ohare", NULL
, macio_ohare
);
2694 probe_one_macio("pci106b,7", NULL
, macio_ohareII
);
2695 probe_one_macio("mac-io", "keylargo", macio_keylargo
);
2696 probe_one_macio("mac-io", "paddington", macio_paddington
);
2697 probe_one_macio("mac-io", "gatwick", macio_gatwick
);
2698 probe_one_macio("mac-io", "heathrow", macio_heathrow
);
2699 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2
);
2701 /* Make sure the "main" macio chip appear first */
2702 if (macio_chips
[0].type
== macio_gatwick
2703 && macio_chips
[1].type
== macio_heathrow
) {
2704 struct macio_chip temp
= macio_chips
[0];
2705 macio_chips
[0] = macio_chips
[1];
2706 macio_chips
[1] = temp
;
2708 if (macio_chips
[0].type
== macio_ohareII
2709 && macio_chips
[1].type
== macio_ohare
) {
2710 struct macio_chip temp
= macio_chips
[0];
2711 macio_chips
[0] = macio_chips
[1];
2712 macio_chips
[1] = temp
;
2714 macio_chips
[0].lbus
.index
= 0;
2715 macio_chips
[1].lbus
.index
= 1;
2717 return (macio_chips
[0].of_node
== NULL
) ? -ENODEV
: 0;
2721 initial_serial_shutdown(struct device_node
*np
)
2724 const struct slot_names_prop
{
2729 int port_type
= PMAC_SCC_ASYNC
;
2732 slots
= of_get_property(np
, "slot-names", &len
);
2733 conn
= of_get_property(np
, "AAPL,connector", &len
);
2734 if (conn
&& (strcmp(conn
, "infrared") == 0))
2735 port_type
= PMAC_SCC_IRDA
;
2736 else if (of_device_is_compatible(np
, "cobalt"))
2738 else if (slots
&& slots
->count
> 0) {
2739 if (strcmp(slots
->name
, "IrDA") == 0)
2740 port_type
= PMAC_SCC_IRDA
;
2741 else if (strcmp(slots
->name
, "Modem") == 0)
2745 pmac_call_feature(PMAC_FTR_MODEM_ENABLE
, np
, 0, 0);
2746 pmac_call_feature(PMAC_FTR_SCC_ENABLE
, np
, port_type
, 0);
2750 set_initial_features(void)
2752 struct device_node
*np
;
2754 /* That hack appears to be necessary for some StarMax motherboards
2755 * but I'm not too sure it was audited for side-effects on other
2756 * ohare based machines...
2757 * Since I still have difficulties figuring the right way to
2758 * differentiate them all and since that hack was there for a long
2759 * time, I'll keep it around
2761 if (macio_chips
[0].type
== macio_ohare
) {
2762 struct macio_chip
*macio
= &macio_chips
[0];
2763 np
= of_find_node_by_name(NULL
, "via-pmu");
2765 MACIO_BIS(OHARE_FCR
, OH_IOBUS_ENABLE
);
2767 MACIO_OUT32(OHARE_FCR
, STARMAX_FEATURES
);
2769 } else if (macio_chips
[1].type
== macio_ohare
) {
2770 struct macio_chip
*macio
= &macio_chips
[1];
2771 MACIO_BIS(OHARE_FCR
, OH_IOBUS_ENABLE
);
2775 if (macio_chips
[0].type
== macio_keylargo2
||
2776 macio_chips
[0].type
== macio_shasta
) {
2778 /* On SMP machines running UP, we have the second CPU eating
2779 * bus cycles. We need to take it off the bus. This is done
2780 * from pmac_smp for SMP kernels running on one CPU
2782 np
= of_find_node_by_type(NULL
, "cpu");
2784 np
= of_find_node_by_type(np
, "cpu");
2786 g5_phy_disable_cpu1();
2789 #endif /* CONFIG_SMP */
2790 /* Enable GMAC for now for PCI probing. It will be disabled
2791 * later on after PCI probe
2793 for_each_node_by_name(np
, "ethernet")
2794 if (of_device_is_compatible(np
, "K2-GMAC"))
2795 g5_gmac_enable(np
, 0, 1);
2797 /* Enable FW before PCI probe. Will be disabled later on
2798 * Note: We should have a batter way to check that we are
2799 * dealing with uninorth internal cell and not a PCI cell
2800 * on the external PCI. The code below works though.
2802 for_each_node_by_name(np
, "firewire") {
2803 if (of_device_is_compatible(np
, "pci106b,5811")) {
2804 macio_chips
[0].flags
|= MACIO_FLAG_FW_SUPPORTED
;
2805 g5_fw_enable(np
, 0, 1);
2809 #else /* CONFIG_PPC64 */
2811 if (macio_chips
[0].type
== macio_keylargo
||
2812 macio_chips
[0].type
== macio_pangea
||
2813 macio_chips
[0].type
== macio_intrepid
) {
2814 /* Enable GMAC for now for PCI probing. It will be disabled
2815 * later on after PCI probe
2817 for_each_node_by_name(np
, "ethernet") {
2819 && of_device_is_compatible(np
->parent
, "uni-north")
2820 && of_device_is_compatible(np
, "gmac"))
2821 core99_gmac_enable(np
, 0, 1);
2824 /* Enable FW before PCI probe. Will be disabled later on
2825 * Note: We should have a batter way to check that we are
2826 * dealing with uninorth internal cell and not a PCI cell
2827 * on the external PCI. The code below works though.
2829 for_each_node_by_name(np
, "firewire") {
2831 && of_device_is_compatible(np
->parent
, "uni-north")
2832 && (of_device_is_compatible(np
, "pci106b,18") ||
2833 of_device_is_compatible(np
, "pci106b,30") ||
2834 of_device_is_compatible(np
, "pci11c1,5811"))) {
2835 macio_chips
[0].flags
|= MACIO_FLAG_FW_SUPPORTED
;
2836 core99_firewire_enable(np
, 0, 1);
2840 /* Enable ATA-100 before PCI probe. */
2841 for_each_node_by_name(np
, "ata-6") {
2843 && of_device_is_compatible(np
->parent
, "uni-north")
2844 && of_device_is_compatible(np
, "kauai-ata")) {
2845 core99_ata100_enable(np
, 1);
2849 /* Switch airport off */
2850 for_each_node_by_name(np
, "radio") {
2851 if (np
->parent
== macio_chips
[0].of_node
) {
2852 macio_chips
[0].flags
|= MACIO_FLAG_AIRPORT_ON
;
2853 core99_airport_enable(np
, 0, 0);
2858 /* On all machines that support sound PM, switch sound off */
2859 if (macio_chips
[0].of_node
)
2860 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE
,
2861 macio_chips
[0].of_node
, 0, 0);
2863 /* While on some desktop G3s, we turn it back on */
2864 if (macio_chips
[0].of_node
&& macio_chips
[0].type
== macio_heathrow
2865 && (pmac_mb
.model_id
== PMAC_TYPE_GOSSAMER
||
2866 pmac_mb
.model_id
== PMAC_TYPE_SILK
)) {
2867 struct macio_chip
*macio
= &macio_chips
[0];
2868 MACIO_BIS(HEATHROW_FCR
, HRW_SOUND_CLK_ENABLE
);
2869 MACIO_BIC(HEATHROW_FCR
, HRW_SOUND_POWER_N
);
2872 #endif /* CONFIG_PPC64 */
2874 /* On all machines, switch modem & serial ports off */
2875 for_each_node_by_name(np
, "ch-a")
2876 initial_serial_shutdown(np
);
2877 for_each_node_by_name(np
, "ch-b")
2878 initial_serial_shutdown(np
);
2882 pmac_feature_init(void)
2884 /* Detect the UniNorth memory controller */
2887 /* Probe mac-io controllers */
2888 if (probe_macios()) {
2889 printk(KERN_WARNING
"No mac-io chip found\n");
2893 /* Probe machine type */
2894 if (probe_motherboard())
2895 printk(KERN_WARNING
"Unknown PowerMac !\n");
2897 /* Set some initial features (turn off some chips that will
2898 * be later turned on)
2900 set_initial_features();
2904 static void dump_HT_speeds(char *name
, u32 cfg
, u32 frq
)
2906 int freqs
[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
2907 int bits
[8] = { 8,16,0,32,2,4,0,0 };
2908 int freq
= (frq
>> 8) & 0xf;
2910 if (freqs
[freq
] == 0)
2911 printk("%s: Unknown HT link frequency %x\n", name
, freq
);
2913 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
2915 bits
[(cfg
>> 28) & 0x7], bits
[(cfg
>> 24) & 0x7]);
2918 void __init
pmac_check_ht_link(void)
2920 u32 ufreq
, freq
, ucfg
, cfg
;
2921 struct device_node
*pcix_node
;
2922 u8 px_bus
, px_devfn
;
2923 struct pci_controller
*px_hose
;
2925 (void)in_be32(u3_ht_base
+ U3_HT_LINK_COMMAND
);
2926 ucfg
= cfg
= in_be32(u3_ht_base
+ U3_HT_LINK_CONFIG
);
2927 ufreq
= freq
= in_be32(u3_ht_base
+ U3_HT_LINK_FREQ
);
2928 dump_HT_speeds("U3 HyperTransport", cfg
, freq
);
2930 pcix_node
= of_find_compatible_node(NULL
, "pci", "pci-x");
2931 if (pcix_node
== NULL
) {
2932 printk("No PCI-X bridge found\n");
2935 if (pci_device_from_OF_node(pcix_node
, &px_bus
, &px_devfn
) != 0) {
2936 printk("PCI-X bridge found but not matched to pci\n");
2939 px_hose
= pci_find_hose_for_OF_device(pcix_node
);
2940 if (px_hose
== NULL
) {
2941 printk("PCI-X bridge found but not matched to host\n");
2944 early_read_config_dword(px_hose
, px_bus
, px_devfn
, 0xc4, &cfg
);
2945 early_read_config_dword(px_hose
, px_bus
, px_devfn
, 0xcc, &freq
);
2946 dump_HT_speeds("PCI-X HT Uplink", cfg
, freq
);
2947 early_read_config_dword(px_hose
, px_bus
, px_devfn
, 0xc8, &cfg
);
2948 early_read_config_dword(px_hose
, px_bus
, px_devfn
, 0xd0, &freq
);
2949 dump_HT_speeds("PCI-X HT Downlink", cfg
, freq
);
2954 * Early video resume hook
2957 static void (*pmac_early_vresume_proc
)(void *data
);
2958 static void *pmac_early_vresume_data
;
2960 void pmac_set_early_video_resume(void (*proc
)(void *data
), void *data
)
2962 if (!machine_is(powermac
))
2965 pmac_early_vresume_proc
= proc
;
2966 pmac_early_vresume_data
= data
;
2969 EXPORT_SYMBOL(pmac_set_early_video_resume
);
2971 void pmac_call_early_video_resume(void)
2973 if (pmac_early_vresume_proc
)
2974 pmac_early_vresume_proc(pmac_early_vresume_data
);
2978 * AGP related suspend/resume code
2981 static struct pci_dev
*pmac_agp_bridge
;
2982 static int (*pmac_agp_suspend
)(struct pci_dev
*bridge
);
2983 static int (*pmac_agp_resume
)(struct pci_dev
*bridge
);
2985 void pmac_register_agp_pm(struct pci_dev
*bridge
,
2986 int (*suspend
)(struct pci_dev
*bridge
),
2987 int (*resume
)(struct pci_dev
*bridge
))
2989 if (suspend
|| resume
) {
2990 pmac_agp_bridge
= bridge
;
2991 pmac_agp_suspend
= suspend
;
2992 pmac_agp_resume
= resume
;
2995 if (bridge
!= pmac_agp_bridge
)
2997 pmac_agp_suspend
= pmac_agp_resume
= NULL
;
3000 EXPORT_SYMBOL(pmac_register_agp_pm
);
3002 void pmac_suspend_agp_for_card(struct pci_dev
*dev
)
3004 if (pmac_agp_bridge
== NULL
|| pmac_agp_suspend
== NULL
)
3006 if (pmac_agp_bridge
->bus
!= dev
->bus
)
3008 pmac_agp_suspend(pmac_agp_bridge
);
3010 EXPORT_SYMBOL(pmac_suspend_agp_for_card
);
3012 void pmac_resume_agp_for_card(struct pci_dev
*dev
)
3014 if (pmac_agp_bridge
== NULL
|| pmac_agp_resume
== NULL
)
3016 if (pmac_agp_bridge
->bus
!= dev
->bus
)
3018 pmac_agp_resume(pmac_agp_bridge
);
3020 EXPORT_SYMBOL(pmac_resume_agp_for_card
);
3022 int pmac_get_uninorth_variant(void)
3024 return uninorth_maj
;