2 * Support for PCI bridges found on Power Macintoshes.
4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/sections.h>
23 #include <asm/pci-bridge.h>
24 #include <asm/machdep.h>
25 #include <asm/pmac_feature.h>
26 #include <asm/grackle.h>
28 //#include <asm/iommu.h>
29 #include <asm/ppc-pci.h>
35 #define DBG(x...) printk(x)
40 static int add_bridge(struct device_node
*dev
);
42 /* XXX Could be per-controller, but I don't think we risk anything by
43 * assuming we won't have both UniNorth and Bandit */
44 static int has_uninorth
;
46 static struct pci_controller
*u3_agp
;
47 static struct pci_controller
*u4_pcie
;
48 static struct pci_controller
*u3_ht
;
49 #endif /* CONFIG_PPC64 */
51 extern u8 pci_cache_line_size
;
52 extern int pcibios_assign_bus_offset
;
54 struct device_node
*k2_skiplist
[2];
57 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
59 #define BANDIT_DEVID_2 8
60 #define BANDIT_REVID 3
62 #define BANDIT_DEVNUM 11
63 #define BANDIT_MAGIC 0x50
64 #define BANDIT_COHERENT 0x40
66 static int __init
fixup_one_level_bus_range(struct device_node
*node
, int higher
)
68 for (; node
!= 0;node
= node
->sibling
) {
70 unsigned int *class_code
;
73 /* For PCI<->PCI bridges or CardBus bridges, we go down */
74 class_code
= (unsigned int *) get_property(node
, "class-code", NULL
);
75 if (!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
76 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
))
78 bus_range
= (int *) get_property(node
, "bus-range", &len
);
79 if (bus_range
!= NULL
&& len
> 2 * sizeof(int)) {
80 if (bus_range
[1] > higher
)
81 higher
= bus_range
[1];
83 higher
= fixup_one_level_bus_range(node
->child
, higher
);
88 /* This routine fixes the "bus-range" property of all bridges in the
89 * system since they tend to have their "last" member wrong on macs
91 * Note that the bus numbers manipulated here are OF bus numbers, they
92 * are not Linux bus numbers.
94 static void __init
fixup_bus_range(struct device_node
*bridge
)
99 /* Lookup the "bus-range" property for the hose */
100 bus_range
= (int *) get_property(bridge
, "bus-range", &len
);
101 if (bus_range
== NULL
|| len
< 2 * sizeof(int))
103 bus_range
[1] = fixup_one_level_bus_range(bridge
->child
, bus_range
[1]);
107 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
109 * The "Bandit" version is present in all early PCI PowerMacs,
110 * and up to the first ones using Grackle. Some machines may
111 * have 2 bandit controllers (2 PCI busses).
113 * "Chaos" is used in some "Bandit"-type machines as a bridge
114 * for the separate display bus. It is accessed the same
115 * way as bandit, but cannot be probed for devices. It therefore
116 * has its own config access functions.
118 * The "UniNorth" version is present in all Core99 machines
119 * (iBook, G4, new IMacs, and all the recent Apple machines).
120 * It contains 3 controllers in one ASIC.
122 * The U3 is the bridge used on G5 machines. It contains an
123 * AGP bus which is dealt with the old UniNorth access routines
124 * and a HyperTransport bus which uses its own set of access
128 #define MACRISC_CFA0(devfn, off) \
129 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
130 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
131 | (((unsigned int)(off)) & 0xFCUL))
133 #define MACRISC_CFA1(bus, devfn, off) \
134 ((((unsigned int)(bus)) << 16) \
135 |(((unsigned int)(devfn)) << 8) \
136 |(((unsigned int)(off)) & 0xFCUL) \
139 static volatile void __iomem
*macrisc_cfg_access(struct pci_controller
* hose
,
140 u8 bus
, u8 dev_fn
, u8 offset
)
144 if (bus
== hose
->first_busno
) {
145 if (dev_fn
< (11 << 3))
147 caddr
= MACRISC_CFA0(dev_fn
, offset
);
149 caddr
= MACRISC_CFA1(bus
, dev_fn
, offset
);
151 /* Uninorth will return garbage if we don't read back the value ! */
153 out_le32(hose
->cfg_addr
, caddr
);
154 } while (in_le32(hose
->cfg_addr
) != caddr
);
156 offset
&= has_uninorth
? 0x07 : 0x03;
157 return hose
->cfg_data
+ offset
;
160 static int macrisc_read_config(struct pci_bus
*bus
, unsigned int devfn
,
161 int offset
, int len
, u32
*val
)
163 struct pci_controller
*hose
;
164 volatile void __iomem
*addr
;
166 hose
= pci_bus_to_host(bus
);
168 return PCIBIOS_DEVICE_NOT_FOUND
;
170 return PCIBIOS_BAD_REGISTER_NUMBER
;
171 addr
= macrisc_cfg_access(hose
, bus
->number
, devfn
, offset
);
173 return PCIBIOS_DEVICE_NOT_FOUND
;
175 * Note: the caller has already checked that offset is
176 * suitably aligned and that len is 1, 2 or 4.
183 *val
= in_le16(addr
);
186 *val
= in_le32(addr
);
189 return PCIBIOS_SUCCESSFUL
;
192 static int macrisc_write_config(struct pci_bus
*bus
, unsigned int devfn
,
193 int offset
, int len
, u32 val
)
195 struct pci_controller
*hose
;
196 volatile void __iomem
*addr
;
198 hose
= pci_bus_to_host(bus
);
200 return PCIBIOS_DEVICE_NOT_FOUND
;
202 return PCIBIOS_BAD_REGISTER_NUMBER
;
203 addr
= macrisc_cfg_access(hose
, bus
->number
, devfn
, offset
);
205 return PCIBIOS_DEVICE_NOT_FOUND
;
207 * Note: the caller has already checked that offset is
208 * suitably aligned and that len is 1, 2 or 4.
217 (void) in_le16(addr
);
221 (void) in_le32(addr
);
224 return PCIBIOS_SUCCESSFUL
;
227 static struct pci_ops macrisc_pci_ops
=
235 * Verify that a specific (bus, dev_fn) exists on chaos
237 static int chaos_validate_dev(struct pci_bus
*bus
, int devfn
, int offset
)
239 struct device_node
*np
;
240 u32
*vendor
, *device
;
243 return PCIBIOS_BAD_REGISTER_NUMBER
;
244 np
= pci_busdev_to_OF_node(bus
, devfn
);
246 return PCIBIOS_DEVICE_NOT_FOUND
;
248 vendor
= (u32
*)get_property(np
, "vendor-id", NULL
);
249 device
= (u32
*)get_property(np
, "device-id", NULL
);
250 if (vendor
== NULL
|| device
== NULL
)
251 return PCIBIOS_DEVICE_NOT_FOUND
;
253 if ((*vendor
== 0x106b) && (*device
== 3) && (offset
>= 0x10)
254 && (offset
!= 0x14) && (offset
!= 0x18) && (offset
<= 0x24))
255 return PCIBIOS_BAD_REGISTER_NUMBER
;
257 return PCIBIOS_SUCCESSFUL
;
261 chaos_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
264 int result
= chaos_validate_dev(bus
, devfn
, offset
);
265 if (result
== PCIBIOS_BAD_REGISTER_NUMBER
)
267 if (result
!= PCIBIOS_SUCCESSFUL
)
269 return macrisc_read_config(bus
, devfn
, offset
, len
, val
);
273 chaos_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
276 int result
= chaos_validate_dev(bus
, devfn
, offset
);
277 if (result
!= PCIBIOS_SUCCESSFUL
)
279 return macrisc_write_config(bus
, devfn
, offset
, len
, val
);
282 static struct pci_ops chaos_pci_ops
=
288 static void __init
setup_chaos(struct pci_controller
*hose
,
289 struct resource
*addr
)
291 /* assume a `chaos' bridge */
292 hose
->ops
= &chaos_pci_ops
;
293 hose
->cfg_addr
= ioremap(addr
->start
+ 0x800000, 0x1000);
294 hose
->cfg_data
= ioremap(addr
->start
+ 0xc00000, 0x1000);
296 #endif /* CONFIG_PPC32 */
300 * These versions of U3 HyperTransport config space access ops do not
301 * implement self-view of the HT host yet
305 * This function deals with some "special cases" devices.
307 * 0 -> No special case
308 * 1 -> Skip the device but act as if the access was successfull
309 * (return 0xff's on reads, eventually, cache config space
310 * accesses in a later version)
311 * -1 -> Hide the device (unsuccessful acess)
313 static int u3_ht_skip_device(struct pci_controller
*hose
,
314 struct pci_bus
*bus
, unsigned int devfn
)
316 struct device_node
*busdn
, *dn
;
319 /* We only allow config cycles to devices that are in OF device-tree
320 * as we are apparently having some weird things going on with some
321 * revs of K2 on recent G5s
324 busdn
= pci_device_to_OF_node(bus
->self
);
326 busdn
= hose
->arch_data
;
327 for (dn
= busdn
->child
; dn
; dn
= dn
->sibling
)
328 if (PCI_DN(dn
) && PCI_DN(dn
)->devfn
== devfn
)
334 * When a device in K2 is powered down, we die on config
335 * cycle accesses. Fix that here.
338 if (k2_skiplist
[i
] == dn
)
344 #define U3_HT_CFA0(devfn, off) \
345 ((((unsigned int)devfn) << 8) | offset)
346 #define U3_HT_CFA1(bus, devfn, off) \
347 (U3_HT_CFA0(devfn, off) \
348 + (((unsigned int)bus) << 16) \
351 static volatile void __iomem
*u3_ht_cfg_access(struct pci_controller
* hose
,
352 u8 bus
, u8 devfn
, u8 offset
)
354 if (bus
== hose
->first_busno
) {
355 /* For now, we don't self probe U3 HT bridge */
356 if (PCI_SLOT(devfn
) == 0)
358 return hose
->cfg_data
+ U3_HT_CFA0(devfn
, offset
);
360 return hose
->cfg_data
+ U3_HT_CFA1(bus
, devfn
, offset
);
363 static int u3_ht_read_config(struct pci_bus
*bus
, unsigned int devfn
,
364 int offset
, int len
, u32
*val
)
366 struct pci_controller
*hose
;
367 volatile void __iomem
*addr
;
369 hose
= pci_bus_to_host(bus
);
371 return PCIBIOS_DEVICE_NOT_FOUND
;
373 return PCIBIOS_BAD_REGISTER_NUMBER
;
374 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
376 return PCIBIOS_DEVICE_NOT_FOUND
;
378 switch (u3_ht_skip_device(hose
, bus
, devfn
)) {
386 *val
= 0xffff; break;
388 *val
= 0xfffffffful
; break;
390 return PCIBIOS_SUCCESSFUL
;
392 return PCIBIOS_DEVICE_NOT_FOUND
;
396 * Note: the caller has already checked that offset is
397 * suitably aligned and that len is 1, 2 or 4.
404 *val
= in_le16(addr
);
407 *val
= in_le32(addr
);
410 return PCIBIOS_SUCCESSFUL
;
413 static int u3_ht_write_config(struct pci_bus
*bus
, unsigned int devfn
,
414 int offset
, int len
, u32 val
)
416 struct pci_controller
*hose
;
417 volatile void __iomem
*addr
;
419 hose
= pci_bus_to_host(bus
);
421 return PCIBIOS_DEVICE_NOT_FOUND
;
423 return PCIBIOS_BAD_REGISTER_NUMBER
;
424 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
426 return PCIBIOS_DEVICE_NOT_FOUND
;
428 switch (u3_ht_skip_device(hose
, bus
, devfn
)) {
432 return PCIBIOS_SUCCESSFUL
;
434 return PCIBIOS_DEVICE_NOT_FOUND
;
438 * Note: the caller has already checked that offset is
439 * suitably aligned and that len is 1, 2 or 4.
448 (void) in_le16(addr
);
451 out_le32((u32 __iomem
*)addr
, val
);
452 (void) in_le32(addr
);
455 return PCIBIOS_SUCCESSFUL
;
458 static struct pci_ops u3_ht_pci_ops
=
464 #define U4_PCIE_CFA0(devfn, off) \
465 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
466 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
467 | ((((unsigned int)(off)) >> 8) << 28) \
468 | (((unsigned int)(off)) & 0xfcU))
470 #define U4_PCIE_CFA1(bus, devfn, off) \
471 ((((unsigned int)(bus)) << 16) \
472 |(((unsigned int)(devfn)) << 8) \
473 | ((((unsigned int)(off)) >> 8) << 28) \
474 |(((unsigned int)(off)) & 0xfcU) \
477 static volatile void __iomem
*u4_pcie_cfg_access(struct pci_controller
* hose
,
478 u8 bus
, u8 dev_fn
, int offset
)
482 if (bus
== hose
->first_busno
) {
483 caddr
= U4_PCIE_CFA0(dev_fn
, offset
);
485 caddr
= U4_PCIE_CFA1(bus
, dev_fn
, offset
);
487 /* Uninorth will return garbage if we don't read back the value ! */
489 out_le32(hose
->cfg_addr
, caddr
);
490 } while (in_le32(hose
->cfg_addr
) != caddr
);
493 return hose
->cfg_data
+ offset
;
496 static int u4_pcie_read_config(struct pci_bus
*bus
, unsigned int devfn
,
497 int offset
, int len
, u32
*val
)
499 struct pci_controller
*hose
;
500 volatile void __iomem
*addr
;
502 hose
= pci_bus_to_host(bus
);
504 return PCIBIOS_DEVICE_NOT_FOUND
;
505 if (offset
>= 0x1000)
506 return PCIBIOS_BAD_REGISTER_NUMBER
;
507 addr
= u4_pcie_cfg_access(hose
, bus
->number
, devfn
, offset
);
509 return PCIBIOS_DEVICE_NOT_FOUND
;
511 * Note: the caller has already checked that offset is
512 * suitably aligned and that len is 1, 2 or 4.
519 *val
= in_le16(addr
);
522 *val
= in_le32(addr
);
525 return PCIBIOS_SUCCESSFUL
;
528 static int u4_pcie_write_config(struct pci_bus
*bus
, unsigned int devfn
,
529 int offset
, int len
, u32 val
)
531 struct pci_controller
*hose
;
532 volatile void __iomem
*addr
;
534 hose
= pci_bus_to_host(bus
);
536 return PCIBIOS_DEVICE_NOT_FOUND
;
537 if (offset
>= 0x1000)
538 return PCIBIOS_BAD_REGISTER_NUMBER
;
539 addr
= u4_pcie_cfg_access(hose
, bus
->number
, devfn
, offset
);
541 return PCIBIOS_DEVICE_NOT_FOUND
;
543 * Note: the caller has already checked that offset is
544 * suitably aligned and that len is 1, 2 or 4.
553 (void) in_le16(addr
);
557 (void) in_le32(addr
);
560 return PCIBIOS_SUCCESSFUL
;
563 static struct pci_ops u4_pcie_pci_ops
=
569 #endif /* CONFIG_PPC64 */
573 * For a bandit bridge, turn on cache coherency if necessary.
574 * N.B. we could clean this up using the hose ops directly.
576 static void __init
init_bandit(struct pci_controller
*bp
)
578 unsigned int vendev
, magic
;
581 /* read the word at offset 0 in config space for device 11 */
582 out_le32(bp
->cfg_addr
, (1UL << BANDIT_DEVNUM
) + PCI_VENDOR_ID
);
584 vendev
= in_le32(bp
->cfg_data
);
585 if (vendev
== (PCI_DEVICE_ID_APPLE_BANDIT
<< 16) +
586 PCI_VENDOR_ID_APPLE
) {
587 /* read the revision id */
588 out_le32(bp
->cfg_addr
,
589 (1UL << BANDIT_DEVNUM
) + PCI_REVISION_ID
);
591 rev
= in_8(bp
->cfg_data
);
592 if (rev
!= BANDIT_REVID
)
594 "Unknown revision %d for bandit\n", rev
);
595 } else if (vendev
!= (BANDIT_DEVID_2
<< 16) + PCI_VENDOR_ID_APPLE
) {
596 printk(KERN_WARNING
"bandit isn't? (%x)\n", vendev
);
600 /* read the word at offset 0x50 */
601 out_le32(bp
->cfg_addr
, (1UL << BANDIT_DEVNUM
) + BANDIT_MAGIC
);
603 magic
= in_le32(bp
->cfg_data
);
604 if ((magic
& BANDIT_COHERENT
) != 0)
606 magic
|= BANDIT_COHERENT
;
608 out_le32(bp
->cfg_data
, magic
);
609 printk(KERN_INFO
"Cache coherency enabled for bandit/PSX\n");
613 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
615 static void __init
init_p2pbridge(void)
617 struct device_node
*p2pbridge
;
618 struct pci_controller
* hose
;
622 /* XXX it would be better here to identify the specific
623 PCI-PCI bridge chip we have. */
624 if ((p2pbridge
= find_devices("pci-bridge")) == 0
625 || p2pbridge
->parent
== NULL
626 || strcmp(p2pbridge
->parent
->name
, "pci") != 0)
628 if (pci_device_from_OF_node(p2pbridge
, &bus
, &devfn
) < 0) {
629 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
632 /* Warning: At this point, we have not yet renumbered all busses.
633 * So we must use OF walking to find out hose
635 hose
= pci_find_hose_for_OF_device(p2pbridge
);
637 DBG("Can't find hose for PCI<->PCI bridge\n");
640 if (early_read_config_word(hose
, bus
, devfn
,
641 PCI_BRIDGE_CONTROL
, &val
) < 0) {
642 printk(KERN_ERR
"init_p2pbridge: couldn't read bridge"
646 val
&= ~PCI_BRIDGE_CTL_MASTER_ABORT
;
647 early_write_config_word(hose
, bus
, devfn
, PCI_BRIDGE_CONTROL
, val
);
651 * Some Apple desktop machines have a NEC PD720100A USB2 controller
652 * on the motherboard. Open Firmware, on these, will disable the
653 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
654 * code re-enables it ;)
656 static void __init
fixup_nec_usb2(void)
658 struct device_node
*nec
;
660 for (nec
= NULL
; (nec
= of_find_node_by_name(nec
, "usb")) != NULL
;) {
661 struct pci_controller
*hose
;
665 prop
= (u32
*)get_property(nec
, "vendor-id", NULL
);
670 prop
= (u32
*)get_property(nec
, "device-id", NULL
);
675 prop
= (u32
*)get_property(nec
, "reg", NULL
);
678 devfn
= (prop
[0] >> 8) & 0xff;
679 bus
= (prop
[0] >> 16) & 0xff;
680 if (PCI_FUNC(devfn
) != 0)
682 hose
= pci_find_hose_for_OF_device(nec
);
685 early_read_config_dword(hose
, bus
, devfn
, 0xe4, &data
);
687 printk("Found NEC PD720100A USB2 chip with disabled"
688 " EHCI, fixing up...\n");
690 early_write_config_dword(hose
, bus
, devfn
, 0xe4, data
);
691 early_write_config_byte(hose
, bus
,
692 devfn
| 2, PCI_INTERRUPT_LINE
,
698 static void __init
setup_bandit(struct pci_controller
*hose
,
699 struct resource
*addr
)
701 hose
->ops
= ¯isc_pci_ops
;
702 hose
->cfg_addr
= ioremap(addr
->start
+ 0x800000, 0x1000);
703 hose
->cfg_data
= ioremap(addr
->start
+ 0xc00000, 0x1000);
707 static int __init
setup_uninorth(struct pci_controller
*hose
,
708 struct resource
*addr
)
710 pci_assign_all_buses
= 1;
712 hose
->ops
= ¯isc_pci_ops
;
713 hose
->cfg_addr
= ioremap(addr
->start
+ 0x800000, 0x1000);
714 hose
->cfg_data
= ioremap(addr
->start
+ 0xc00000, 0x1000);
715 /* We "know" that the bridge at f2000000 has the PCI slots. */
716 return addr
->start
== 0xf2000000;
718 #endif /* CONFIG_PPC32 */
721 static void __init
setup_u3_agp(struct pci_controller
* hose
)
723 /* On G5, we move AGP up to high bus number so we don't need
724 * to reassign bus numbers for HT. If we ever have P2P bridges
725 * on AGP, we'll have to move pci_assign_all_busses to the
726 * pci_controller structure so we enable it for AGP and not for
728 * We hard code the address because of the different size of
729 * the reg address cell, we shall fix that by killing struct
730 * reg_property and using some accessor functions instead
732 hose
->first_busno
= 0xf0;
733 hose
->last_busno
= 0xff;
735 hose
->ops
= ¯isc_pci_ops
;
736 hose
->cfg_addr
= ioremap(0xf0000000 + 0x800000, 0x1000);
737 hose
->cfg_data
= ioremap(0xf0000000 + 0xc00000, 0x1000);
741 static void __init
setup_u4_pcie(struct pci_controller
* hose
)
743 /* We currently only implement the "non-atomic" config space, to
744 * be optimised later.
746 hose
->ops
= &u4_pcie_pci_ops
;
747 hose
->cfg_addr
= ioremap(0xf0000000 + 0x800000, 0x1000);
748 hose
->cfg_data
= ioremap(0xf0000000 + 0xc00000, 0x1000);
750 /* The bus contains a bridge from root -> device, we need to
751 * make it visible on bus 0 so that we pick the right type
752 * of config cycles. If we didn't, we would have to force all
753 * config cycles to be type 1. So we override the "bus-range"
756 hose
->first_busno
= 0x00;
757 hose
->last_busno
= 0xff;
761 static void __init
setup_u3_ht(struct pci_controller
* hose
)
763 struct device_node
*np
= (struct device_node
*)hose
->arch_data
;
764 struct pci_controller
*other
= NULL
;
768 hose
->ops
= &u3_ht_pci_ops
;
770 /* We hard code the address because of the different size of
771 * the reg address cell, we shall fix that by killing struct
772 * reg_property and using some accessor functions instead
774 hose
->cfg_data
= ioremap(0xf2000000, 0x02000000);
777 * /ht node doesn't expose a "ranges" property, so we "remove"
778 * regions that have been allocated to AGP. So far, this version of
779 * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions
780 * to /ht. We need to fix that sooner or later by either parsing all
781 * child "ranges" properties or figuring out the U3 address space
782 * decoding logic and then read its configuration register (if any).
784 hose
->io_base_phys
= 0xf4000000;
785 hose
->pci_io_size
= 0x00400000;
786 hose
->io_resource
.name
= np
->full_name
;
787 hose
->io_resource
.start
= 0;
788 hose
->io_resource
.end
= 0x003fffff;
789 hose
->io_resource
.flags
= IORESOURCE_IO
;
790 hose
->pci_mem_offset
= 0;
791 hose
->first_busno
= 0;
792 hose
->last_busno
= 0xef;
793 hose
->mem_resources
[0].name
= np
->full_name
;
794 hose
->mem_resources
[0].start
= 0x80000000;
795 hose
->mem_resources
[0].end
= 0xefffffff;
796 hose
->mem_resources
[0].flags
= IORESOURCE_MEM
;
802 else if (u4_pcie
!= NULL
)
806 DBG("U3/4 has no AGP/PCIE, using full resource range\n");
810 /* Fixup bus range vs. PCIE */
812 hose
->last_busno
= u4_pcie
->first_busno
- 1;
814 /* We "remove" the AGP resources from the resources allocated to HT,
815 * that is we create "holes". However, that code does assumptions
816 * that so far happen to be true (cross fingers...), typically that
817 * resources in the AGP node are properly ordered
820 for (i
=0; i
<3; i
++) {
821 struct resource
*res
= &other
->mem_resources
[i
];
822 if (res
->flags
!= IORESOURCE_MEM
)
824 /* We don't care about "fine" resources */
825 if (res
->start
>= 0xf0000000)
827 /* Check if it's just a matter of "shrinking" us in one
830 if (hose
->mem_resources
[cur
].start
== res
->start
) {
831 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
832 cur
, hose
->mem_resources
[cur
].start
,
834 hose
->mem_resources
[cur
].start
= res
->end
+ 1;
837 if (hose
->mem_resources
[cur
].end
== res
->end
) {
838 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
839 cur
, hose
->mem_resources
[cur
].end
,
841 hose
->mem_resources
[cur
].end
= res
->start
- 1;
844 /* No, it's not the case, we need a hole */
846 /* not enough resources for a hole, we drop part
849 printk(KERN_WARNING
"Running out of resources"
850 " for /ht host !\n");
851 hose
->mem_resources
[cur
].end
= res
->start
- 1;
855 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
856 cur
-1, res
->start
- 1, cur
, res
->end
+ 1);
857 hose
->mem_resources
[cur
].name
= np
->full_name
;
858 hose
->mem_resources
[cur
].flags
= IORESOURCE_MEM
;
859 hose
->mem_resources
[cur
].start
= res
->end
+ 1;
860 hose
->mem_resources
[cur
].end
= hose
->mem_resources
[cur
-1].end
;
861 hose
->mem_resources
[cur
-1].end
= res
->start
- 1;
864 #endif /* CONFIG_PPC64 */
867 * We assume that if we have a G3 powermac, we have one bridge called
868 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
869 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
871 static int __init
add_bridge(struct device_node
*dev
)
874 struct pci_controller
*hose
;
875 struct resource rsrc
;
878 int primary
= 1, has_address
= 0;
880 DBG("Adding PCI host bridge %s\n", dev
->full_name
);
882 /* Fetch host bridge registers address */
883 has_address
= (of_address_to_resource(dev
, 0, &rsrc
) == 0);
885 /* Get bus range if any */
886 bus_range
= (int *) get_property(dev
, "bus-range", &len
);
887 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
888 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
889 " bus 0\n", dev
->full_name
);
892 /* XXX Different prototypes, to be merged */
894 hose
= pcibios_alloc_controller(dev
);
896 hose
= pcibios_alloc_controller();
900 hose
->arch_data
= dev
;
901 hose
->first_busno
= bus_range
? bus_range
[0] : 0;
902 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
906 /* 64 bits only bridges */
908 if (device_is_compatible(dev
, "u3-agp")) {
910 disp_name
= "U3-AGP";
912 } else if (device_is_compatible(dev
, "u3-ht")) {
916 } else if (device_is_compatible(dev
, "u4-pcie")) {
918 disp_name
= "U4-PCIE";
921 printk(KERN_INFO
"Found %s PCI host bridge. Firmware bus number:"
922 " %d->%d\n", disp_name
, hose
->first_busno
, hose
->last_busno
);
923 #endif /* CONFIG_PPC64 */
925 /* 32 bits only bridges */
927 if (device_is_compatible(dev
, "uni-north")) {
928 primary
= setup_uninorth(hose
, &rsrc
);
929 disp_name
= "UniNorth";
930 } else if (strcmp(dev
->name
, "pci") == 0) {
931 /* XXX assume this is a mpc106 (grackle) */
933 disp_name
= "Grackle (MPC106)";
934 } else if (strcmp(dev
->name
, "bandit") == 0) {
935 setup_bandit(hose
, &rsrc
);
936 disp_name
= "Bandit";
937 } else if (strcmp(dev
->name
, "chaos") == 0) {
938 setup_chaos(hose
, &rsrc
);
942 printk(KERN_INFO
"Found %s PCI host bridge at 0x%08lx. "
943 "Firmware bus number: %d->%d\n",
944 disp_name
, rsrc
.start
, hose
->first_busno
, hose
->last_busno
);
945 #endif /* CONFIG_PPC32 */
947 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
948 hose
, hose
->cfg_addr
, hose
->cfg_data
);
950 /* Interpret the "ranges" property */
951 /* This also maps the I/O region and sets isa_io/mem_base */
952 pci_process_bridge_OF_ranges(hose
, dev
, primary
);
954 /* Fixup "bus-range" OF property */
955 fixup_bus_range(dev
);
960 static void __init
pcibios_fixup_OF_interrupts(void)
962 struct pci_dev
* dev
= NULL
;
965 * Open Firmware often doesn't initialize the
966 * PCI_INTERRUPT_LINE config register properly, so we
967 * should find the device node and apply the interrupt
968 * obtained from the OF device-tree
970 for_each_pci_dev(dev
) {
971 struct device_node
*node
;
972 node
= pci_device_to_OF_node(dev
);
973 /* this is the node, see if it has interrupts */
974 if (node
&& node
->n_intrs
> 0)
975 dev
->irq
= node
->intrs
[0].line
;
976 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, dev
->irq
);
980 void __init
pmac_pcibios_fixup(void)
982 /* Fixup interrupts according to OF tree */
983 pcibios_fixup_OF_interrupts();
987 static void __init
pmac_fixup_phb_resources(void)
989 struct pci_controller
*hose
, *tmp
;
991 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
992 printk(KERN_INFO
"PCI Host %d, io start: %lx; io end: %lx\n",
994 hose
->io_resource
.start
, hose
->io_resource
.end
);
999 void __init
pmac_pci_init(void)
1001 struct device_node
*np
, *root
;
1002 struct device_node
*ht
= NULL
;
1004 root
= of_find_node_by_path("/");
1006 printk(KERN_CRIT
"pmac_pci_init: can't find root "
1007 "of device tree\n");
1010 for (np
= NULL
; (np
= of_get_next_child(root
, np
)) != NULL
;) {
1011 if (np
->name
== NULL
)
1013 if (strcmp(np
->name
, "bandit") == 0
1014 || strcmp(np
->name
, "chaos") == 0
1015 || strcmp(np
->name
, "pci") == 0) {
1016 if (add_bridge(np
) == 0)
1019 if (strcmp(np
->name
, "ht") == 0) {
1027 /* Probe HT last as it relies on the agp resources to be already
1030 if (ht
&& add_bridge(ht
) != 0)
1034 * We need to call pci_setup_phb_io for the HT bridge first
1035 * so it gets the I/O port numbers starting at 0, and we
1036 * need to call it for the AGP bridge after that so it gets
1037 * small positive I/O port numbers.
1040 pci_setup_phb_io(u3_ht
, 1);
1042 pci_setup_phb_io(u3_agp
, 0);
1044 pci_setup_phb_io(u4_pcie
, 0);
1047 * On ppc64, fixup the IO resources on our host bridges as
1048 * the common code does it only for children of the host bridges
1050 pmac_fixup_phb_resources();
1052 /* Setup the linkage between OF nodes and PHBs */
1053 pci_devs_phb_init();
1055 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
1056 * assume there is no P2P bridge on the AGP bus, which should be a
1057 * safe assumptions for now. We should do something better in the
1061 struct device_node
*np
= u3_agp
->arch_data
;
1062 PCI_DN(np
)->busno
= 0xf0;
1063 for (np
= np
->child
; np
; np
= np
->sibling
)
1064 PCI_DN(np
)->busno
= 0xf0;
1066 /* pmac_check_ht_link(); */
1068 /* Tell pci.c to not use the common resource allocation mechanism */
1074 #else /* CONFIG_PPC64 */
1078 /* We are still having some issues with the Xserve G4, enabling
1079 * some offset between bus number and domains for now when we
1080 * assign all busses should help for now
1082 if (pci_assign_all_buses
)
1083 pcibios_assign_bus_offset
= 0x10;
1088 pmac_pci_enable_device_hook(struct pci_dev
*dev
, int initial
)
1090 struct device_node
* node
;
1094 node
= pci_device_to_OF_node(dev
);
1096 /* We don't want to enable USB controllers absent from the OF tree
1097 * (iBook second controller)
1099 if (dev
->vendor
== PCI_VENDOR_ID_APPLE
1100 && dev
->class == PCI_CLASS_SERIAL_USB_OHCI
1102 printk(KERN_INFO
"Apple USB OHCI %s disabled by firmware\n",
1110 uninorth_child
= node
->parent
&&
1111 device_is_compatible(node
->parent
, "uni-north");
1113 /* Firewire & GMAC were disabled after PCI probe, the driver is
1114 * claiming them, we must re-enable them now.
1116 if (uninorth_child
&& !strcmp(node
->name
, "firewire") &&
1117 (device_is_compatible(node
, "pci106b,18") ||
1118 device_is_compatible(node
, "pci106b,30") ||
1119 device_is_compatible(node
, "pci11c1,5811"))) {
1120 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, node
, 0, 1);
1121 pmac_call_feature(PMAC_FTR_1394_ENABLE
, node
, 0, 1);
1124 if (uninorth_child
&& !strcmp(node
->name
, "ethernet") &&
1125 device_is_compatible(node
, "gmac")) {
1126 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, node
, 0, 1);
1134 * Make sure PCI is correctly configured
1136 * We use old pci_bios versions of the function since, by
1137 * default, gmac is not powered up, and so will be absent
1138 * from the kernel initial PCI lookup.
1140 * Should be replaced by 2.4 new PCI mechanisms and really
1141 * register the device.
1143 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1144 cmd
|= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
1145 | PCI_COMMAND_INVALIDATE
;
1146 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1147 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 16);
1148 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
,
1149 L1_CACHE_BYTES
>> 2);
1155 /* We power down some devices after they have been probed. They'll
1156 * be powered back on later on
1158 void __init
pmac_pcibios_after_init(void)
1160 struct device_node
* nd
;
1162 #ifdef CONFIG_BLK_DEV_IDE
1163 struct pci_dev
*dev
= NULL
;
1165 /* OF fails to initialize IDE controllers on macs
1166 * (and maybe other machines)
1168 * Ideally, this should be moved to the IDE layer, but we need
1169 * to check specifically with Andre Hedrick how to do it cleanly
1170 * since the common IDE code seem to care about the fact that the
1171 * BIOS may have disabled a controller.
1175 for_each_pci_dev(dev
) {
1176 if ((dev
->class >> 16) == PCI_BASE_CLASS_STORAGE
)
1177 pci_enable_device(dev
);
1179 #endif /* CONFIG_BLK_DEV_IDE */
1181 nd
= find_devices("firewire");
1183 if (nd
->parent
&& (device_is_compatible(nd
, "pci106b,18") ||
1184 device_is_compatible(nd
, "pci106b,30") ||
1185 device_is_compatible(nd
, "pci11c1,5811"))
1186 && device_is_compatible(nd
->parent
, "uni-north")) {
1187 pmac_call_feature(PMAC_FTR_1394_ENABLE
, nd
, 0, 0);
1188 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, nd
, 0, 0);
1192 nd
= find_devices("ethernet");
1194 if (nd
->parent
&& device_is_compatible(nd
, "gmac")
1195 && device_is_compatible(nd
->parent
, "uni-north"))
1196 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, nd
, 0, 0);
1202 void pmac_pci_fixup_cardbus(struct pci_dev
* dev
)
1204 if (!machine_is(powermac
))
1207 * Fix the interrupt routing on the various cardbus bridges
1208 * used on powerbooks
1210 if (dev
->vendor
!= PCI_VENDOR_ID_TI
)
1212 if (dev
->device
== PCI_DEVICE_ID_TI_1130
||
1213 dev
->device
== PCI_DEVICE_ID_TI_1131
) {
1215 /* Enable PCI interrupt */
1216 if (pci_read_config_byte(dev
, 0x91, &val
) == 0)
1217 pci_write_config_byte(dev
, 0x91, val
| 0x30);
1218 /* Disable ISA interrupt mode */
1219 if (pci_read_config_byte(dev
, 0x92, &val
) == 0)
1220 pci_write_config_byte(dev
, 0x92, val
& ~0x06);
1222 if (dev
->device
== PCI_DEVICE_ID_TI_1210
||
1223 dev
->device
== PCI_DEVICE_ID_TI_1211
||
1224 dev
->device
== PCI_DEVICE_ID_TI_1410
||
1225 dev
->device
== PCI_DEVICE_ID_TI_1510
) {
1227 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1228 signal out the MFUNC0 pin */
1229 if (pci_read_config_byte(dev
, 0x8c, &val
) == 0)
1230 pci_write_config_byte(dev
, 0x8c, (val
& ~0x0f) | 2);
1231 /* Disable ISA interrupt mode */
1232 if (pci_read_config_byte(dev
, 0x92, &val
) == 0)
1233 pci_write_config_byte(dev
, 0x92, val
& ~0x06);
1237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_ANY_ID
, pmac_pci_fixup_cardbus
);
1239 void pmac_pci_fixup_pciata(struct pci_dev
* dev
)
1244 * On PowerMacs, we try to switch any PCI ATA controller to
1247 if (!machine_is(powermac
))
1250 /* Some controllers don't have the class IDE */
1251 if (dev
->vendor
== PCI_VENDOR_ID_PROMISE
)
1252 switch(dev
->device
) {
1253 case PCI_DEVICE_ID_PROMISE_20246
:
1254 case PCI_DEVICE_ID_PROMISE_20262
:
1255 case PCI_DEVICE_ID_PROMISE_20263
:
1256 case PCI_DEVICE_ID_PROMISE_20265
:
1257 case PCI_DEVICE_ID_PROMISE_20267
:
1258 case PCI_DEVICE_ID_PROMISE_20268
:
1259 case PCI_DEVICE_ID_PROMISE_20269
:
1260 case PCI_DEVICE_ID_PROMISE_20270
:
1261 case PCI_DEVICE_ID_PROMISE_20271
:
1262 case PCI_DEVICE_ID_PROMISE_20275
:
1263 case PCI_DEVICE_ID_PROMISE_20276
:
1264 case PCI_DEVICE_ID_PROMISE_20277
:
1267 /* Others, check PCI class */
1268 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
1271 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1272 if ((progif
& 5) != 5) {
1273 printk(KERN_INFO
"Forcing PCI IDE into native mode: %s\n",
1275 (void) pci_write_config_byte(dev
, PCI_CLASS_PROG
, progif
|5);
1276 if (pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
) ||
1278 printk(KERN_ERR
"Rewrite of PROGIF failed !\n");
1281 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, pmac_pci_fixup_pciata
);
1285 * Disable second function on K2-SATA, it's broken
1286 * and disable IO BARs on first one
1288 static void fixup_k2_sata(struct pci_dev
* dev
)
1293 if (PCI_FUNC(dev
->devfn
) > 0) {
1294 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1295 cmd
&= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
);
1296 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1297 for (i
= 0; i
< 6; i
++) {
1298 dev
->resource
[i
].start
= dev
->resource
[i
].end
= 0;
1299 dev
->resource
[i
].flags
= 0;
1300 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
+ 4 * i
,
1304 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1305 cmd
&= ~PCI_COMMAND_IO
;
1306 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1307 for (i
= 0; i
< 5; i
++) {
1308 dev
->resource
[i
].start
= dev
->resource
[i
].end
= 0;
1309 dev
->resource
[i
].flags
= 0;
1310 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
+ 4 * i
,
1315 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
, 0x0240, fixup_k2_sata
);