arch/powerpc/platforms/powermac/sleep.S

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * This file contains sleep low-level functions for PowerBook G3.
   4  *    Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   5  *    and Paul Mackerras (paulus@samba.org).
   6  */
   7
   8 #include <asm/processor.h>
   9 #include <asm/page.h>
  10 #include <asm/ppc_asm.h>
  11 #include <asm/cputable.h>
  12 #include <asm/cache.h>
  13 #include <asm/thread_info.h>
  14 #include <asm/asm-offsets.h>
  15 #include <asm/mmu.h>
  16 #include <asm/feature-fixups.h>
  17
  18 #define MAGIC   0x4c617273      /* 'Lars' */
  19
  20 /*
  21  * Structure for storing CPU registers on the stack.
  22  */
  23 #define SL_SP           0
  24 #define SL_PC           4
  25 #define SL_MSR          8
  26 #define SL_SDR1         0xc
  27 #define SL_SPRG0        0x10    /* 4 sprg's */
  28 #define SL_DBAT0        0x20
  29 #define SL_IBAT0        0x28
  30 #define SL_DBAT1        0x30
  31 #define SL_IBAT1        0x38
  32 #define SL_DBAT2        0x40
  33 #define SL_IBAT2        0x48
  34 #define SL_DBAT3        0x50
  35 #define SL_IBAT3        0x58
  36 #define SL_TB           0x60
  37 #define SL_R2           0x68
  38 #define SL_CR           0x6c
  39 #define SL_R12          0x70    /* r12 to r31 */
  40 #define SL_SIZE         (SL_R12 + 80)
  41
  42         .section .text
  43         .align  5
  44
  45 #if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
  46     (defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
  47
  48 /* This gets called by via-pmu.c late during the sleep process.
  49  * The PMU was already send the sleep command and will shut us down
  50  * soon. We need to save all that is needed and setup the wakeup
  51  * vector that will be called by the ROM on wakeup
  52  */
  53 _GLOBAL(low_sleep_handler)
  54 #ifndef CONFIG_PPC_BOOK3S_32
  55         blr
  56 #else
  57         mflr    r0
  58         stw     r0,4(r1)
  59         stwu    r1,-SL_SIZE(r1)
  60         mfcr    r0
  61         stw     r0,SL_CR(r1)
  62         stw     r2,SL_R2(r1)
  63         stmw    r12,SL_R12(r1)
  64
  65         /* Save MSR & SDR1 */
  66         mfmsr   r4
  67         stw     r4,SL_MSR(r1)
  68         mfsdr1  r4
  69         stw     r4,SL_SDR1(r1)
  70
  71         /* Get a stable timebase and save it */
  72 1:      mftbu   r4
  73         stw     r4,SL_TB(r1)
  74         mftb    r5
  75         stw     r5,SL_TB+4(r1)
  76         mftbu   r3
  77         cmpw    r3,r4
  78         bne     1b
  79
  80         /* Save SPRGs */
  81         mfsprg  r4,0
  82         stw     r4,SL_SPRG0(r1)
  83         mfsprg  r4,1
  84         stw     r4,SL_SPRG0+4(r1)
  85         mfsprg  r4,2
  86         stw     r4,SL_SPRG0+8(r1)
  87         mfsprg  r4,3
  88         stw     r4,SL_SPRG0+12(r1)
  89
  90         /* Save BATs */
  91         mfdbatu r4,0
  92         stw     r4,SL_DBAT0(r1)
  93         mfdbatl r4,0
  94         stw     r4,SL_DBAT0+4(r1)
  95         mfdbatu r4,1
  96         stw     r4,SL_DBAT1(r1)
  97         mfdbatl r4,1
  98         stw     r4,SL_DBAT1+4(r1)
  99         mfdbatu r4,2
 100         stw     r4,SL_DBAT2(r1)
 101         mfdbatl r4,2
 102         stw     r4,SL_DBAT2+4(r1)
 103         mfdbatu r4,3
 104         stw     r4,SL_DBAT3(r1)
 105         mfdbatl r4,3
 106         stw     r4,SL_DBAT3+4(r1)
 107         mfibatu r4,0
 108         stw     r4,SL_IBAT0(r1)
 109         mfibatl r4,0
 110         stw     r4,SL_IBAT0+4(r1)
 111         mfibatu r4,1
 112         stw     r4,SL_IBAT1(r1)
 113         mfibatl r4,1
 114         stw     r4,SL_IBAT1+4(r1)
 115         mfibatu r4,2
 116         stw     r4,SL_IBAT2(r1)
 117         mfibatl r4,2
 118         stw     r4,SL_IBAT2+4(r1)
 119         mfibatu r4,3
 120         stw     r4,SL_IBAT3(r1)
 121         mfibatl r4,3
 122         stw     r4,SL_IBAT3+4(r1)
 123
 124         /* Backup various CPU config stuffs */
 125         bl      __save_cpu_setup
 126
 127         /* The ROM can wake us up via 2 different vectors:
 128          *  - On wallstreet & lombard, we must write a magic
 129          *    value 'Lars' at address 4 and a pointer to a
 130          *    memory location containing the PC to resume from
 131          *    at address 0.
 132          *  - On Core99, we must store the wakeup vector at
 133          *    address 0x80 and eventually it's parameters
 134          *    at address 0x84. I've have some trouble with those
 135          *    parameters however and I no longer use them.
 136          */
 137         lis     r5,grackle_wake_up@ha
 138         addi    r5,r5,grackle_wake_up@l
 139         tophys(r5,r5)
 140         stw     r5,SL_PC(r1)
 141         lis     r4,KERNELBASE@h
 142         tophys(r5,r1)
 143         addi    r5,r5,SL_PC
 144         lis     r6,MAGIC@ha
 145         addi    r6,r6,MAGIC@l
 146         stw     r5,0(r4)
 147         stw     r6,4(r4)
 148         /* Setup stuffs at 0x80-0x84 for Core99 */
 149         lis     r3,core99_wake_up@ha
 150         addi    r3,r3,core99_wake_up@l
 151         tophys(r3,r3)
 152         stw     r3,0x80(r4)
 153         stw     r5,0x84(r4)
 154         /* Store a pointer to our backup storage into
 155          * a kernel global
 156          */
 157         lis r3,sleep_storage@ha
 158         addi r3,r3,sleep_storage@l
 159         stw r5,0(r3)
 160
 161         .globl  low_cpu_die
 162 low_cpu_die:
 163         /* Flush & disable all caches */
 164         bl      flush_disable_caches
 165
 166         /* Turn off data relocation. */
 167         mfmsr   r3              /* Save MSR in r7 */
 168         rlwinm  r3,r3,0,28,26   /* Turn off DR bit */
 169         sync
 170         mtmsr   r3
 171         isync
 172
 173 BEGIN_FTR_SECTION
 174         /* Flush any pending L2 data prefetches to work around HW bug */
 175         sync
 176         lis     r3,0xfff0
 177         lwz     r0,0(r3)        /* perform cache-inhibited load to ROM */
 178         sync                    /* (caches are disabled at this point) */
 179 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
 180
 181 /*
 182  * Set the HID0 and MSR for sleep.
 183  */
 184         mfspr   r2,SPRN_HID0
 185         rlwinm  r2,r2,0,10,7    /* clear doze, nap */
 186         oris    r2,r2,HID0_SLEEP@h
 187         sync
 188         isync
 189         mtspr   SPRN_HID0,r2
 190         sync
 191
 192 /* This loop puts us back to sleep in case we have a spurrious
 193  * wakeup so that the host bridge properly stays asleep. The
 194  * CPU will be turned off, either after a known time (about 1
 195  * second) on wallstreet & lombard, or as soon as the CPU enters
 196  * SLEEP mode on core99
 197  */
 198         mfmsr   r2
 199         oris    r2,r2,MSR_POW@h
 200 1:      sync
 201         mtmsr   r2
 202         isync
 203         b       1b
 204
 205 /*
 206  * Here is the resume code.
 207  */
 208
 209
 210 /*
 211  * Core99 machines resume here
 212  * r4 has the physical address of SL_PC(sp) (unused)
 213  */
 214 _GLOBAL(core99_wake_up)
 215         /* Make sure HID0 no longer contains any sleep bit and that data cache
 216          * is disabled
 217          */
 218         mfspr   r3,SPRN_HID0
 219         rlwinm  r3,r3,0,11,7            /* clear SLEEP, NAP, DOZE bits */
 220         rlwinm  3,r3,0,18,15            /* clear DCE, ICE */
 221         mtspr   SPRN_HID0,r3
 222         sync
 223         isync
 224
 225         /* sanitize MSR */
 226         mfmsr   r3
 227         ori     r3,r3,MSR_EE|MSR_IP
 228         xori    r3,r3,MSR_EE|MSR_IP
 229         sync
 230         isync
 231         mtmsr   r3
 232         sync
 233         isync
 234
 235         /* Recover sleep storage */
 236         lis     r3,sleep_storage@ha
 237         addi    r3,r3,sleep_storage@l
 238         tophys(r3,r3)
 239         lwz     r1,0(r3)
 240
 241         /* Pass thru to older resume code ... */
 242 /*
 243  * Here is the resume code for older machines.
 244  * r1 has the physical address of SL_PC(sp).
 245  */
 246
 247 grackle_wake_up:
 248
 249         /* Restore the kernel's segment registers before
 250          * we do any r1 memory access as we are not sure they
 251          * are in a sane state above the first 256Mb region
 252          */
 253         li      r0,16           /* load up segment register values */
 254         mtctr   r0              /* for context 0 */
 255         lis     r3,0x2000       /* Ku = 1, VSID = 0 */
 256         li      r4,0
 257 3:      mtsrin  r3,r4
 258         addi    r3,r3,0x111     /* increment VSID */
 259         addis   r4,r4,0x1000    /* address of next segment */
 260         bdnz    3b
 261         sync
 262         isync
 263
 264         subi    r1,r1,SL_PC
 265
 266         /* Restore various CPU config stuffs */
 267         bl      __restore_cpu_setup
 268
 269         /* Make sure all FPRs have been initialized */
 270         bl      reloc_offset
 271         bl      __init_fpu_registers
 272
 273         /* Invalidate & enable L1 cache, we don't care about
 274          * whatever the ROM may have tried to write to memory
 275          */
 276         bl      __inval_enable_L1
 277
 278         /* Restore the BATs, and SDR1.  Then we can turn on the MMU. */
 279         lwz     r4,SL_SDR1(r1)
 280         mtsdr1  r4
 281         lwz     r4,SL_SPRG0(r1)
 282         mtsprg  0,r4
 283         lwz     r4,SL_SPRG0+4(r1)
 284         mtsprg  1,r4
 285         lwz     r4,SL_SPRG0+8(r1)
 286         mtsprg  2,r4
 287         lwz     r4,SL_SPRG0+12(r1)
 288         mtsprg  3,r4
 289
 290         lwz     r4,SL_DBAT0(r1)
 291         mtdbatu 0,r4
 292         lwz     r4,SL_DBAT0+4(r1)
 293         mtdbatl 0,r4
 294         lwz     r4,SL_DBAT1(r1)
 295         mtdbatu 1,r4
 296         lwz     r4,SL_DBAT1+4(r1)
 297         mtdbatl 1,r4
 298         lwz     r4,SL_DBAT2(r1)
 299         mtdbatu 2,r4
 300         lwz     r4,SL_DBAT2+4(r1)
 301         mtdbatl 2,r4
 302         lwz     r4,SL_DBAT3(r1)
 303         mtdbatu 3,r4
 304         lwz     r4,SL_DBAT3+4(r1)
 305         mtdbatl 3,r4
 306         lwz     r4,SL_IBAT0(r1)
 307         mtibatu 0,r4
 308         lwz     r4,SL_IBAT0+4(r1)
 309         mtibatl 0,r4
 310         lwz     r4,SL_IBAT1(r1)
 311         mtibatu 1,r4
 312         lwz     r4,SL_IBAT1+4(r1)
 313         mtibatl 1,r4
 314         lwz     r4,SL_IBAT2(r1)
 315         mtibatu 2,r4
 316         lwz     r4,SL_IBAT2+4(r1)
 317         mtibatl 2,r4
 318         lwz     r4,SL_IBAT3(r1)
 319         mtibatu 3,r4
 320         lwz     r4,SL_IBAT3+4(r1)
 321         mtibatl 3,r4
 322
 323 BEGIN_MMU_FTR_SECTION
 324         li      r4,0
 325         mtspr   SPRN_DBAT4U,r4
 326         mtspr   SPRN_DBAT4L,r4
 327         mtspr   SPRN_DBAT5U,r4
 328         mtspr   SPRN_DBAT5L,r4
 329         mtspr   SPRN_DBAT6U,r4
 330         mtspr   SPRN_DBAT6L,r4
 331         mtspr   SPRN_DBAT7U,r4
 332         mtspr   SPRN_DBAT7L,r4
 333         mtspr   SPRN_IBAT4U,r4
 334         mtspr   SPRN_IBAT4L,r4
 335         mtspr   SPRN_IBAT5U,r4
 336         mtspr   SPRN_IBAT5L,r4
 337         mtspr   SPRN_IBAT6U,r4
 338         mtspr   SPRN_IBAT6L,r4
 339         mtspr   SPRN_IBAT7U,r4
 340         mtspr   SPRN_IBAT7L,r4
 341 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
 342
 343         /* Flush all TLBs */
 344         lis     r4,0x1000
 345 1:      addic.  r4,r4,-0x1000
 346         tlbie   r4
 347         blt     1b
 348         sync
 349
 350         /* restore the MSR and turn on the MMU */
 351         lwz     r3,SL_MSR(r1)
 352         bl      turn_on_mmu
 353
 354         /* get back the stack pointer */
 355         tovirt(r1,r1)
 356
 357         /* Restore TB */
 358         li      r3,0
 359         mttbl   r3
 360         lwz     r3,SL_TB(r1)
 361         lwz     r4,SL_TB+4(r1)
 362         mttbu   r3
 363         mttbl   r4
 364
 365         /* Restore the callee-saved registers and return */
 366         lwz     r0,SL_CR(r1)
 367         mtcr    r0
 368         lwz     r2,SL_R2(r1)
 369         lmw     r12,SL_R12(r1)
 370         addi    r1,r1,SL_SIZE
 371         lwz     r0,4(r1)
 372         mtlr    r0
 373         blr
 374
 375 turn_on_mmu:
 376         mflr    r4
 377         tovirt(r4,r4)
 378         mtsrr0  r4
 379         mtsrr1  r3
 380         sync
 381         isync
 382         rfi
 383
 384 #endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
 385
 386         .section .data
 387         .balign L1_CACHE_BYTES
 388 sleep_storage:
 389         .long 0
 390         .balign L1_CACHE_BYTES, 0
 391
 392 #endif /* CONFIG_PPC_BOOK3S_32 */
 393         .section .text