1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains sleep low-level functions for PowerBook G3.
4 * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 * and Paul Mackerras (paulus@samba.org).
8 #include <asm/processor.h>
10 #include <asm/ppc_asm.h>
11 #include <asm/cputable.h>
12 #include <asm/cache.h>
13 #include <asm/thread_info.h>
14 #include <asm/asm-offsets.h>
16 #include <asm/feature-fixups.h>
18 #define MAGIC 0x4c617273 /* 'Lars' */
21 * Structure for storing CPU registers on the stack.
27 #define SL_SPRG0 0x10 /* 4 sprg's */
39 #define SL_R12 0x70 /* r12 to r31 */
40 #define SL_SIZE (SL_R12 + 80)
45 #if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
46 (defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
48 /* This gets called by via-pmu.c late during the sleep process.
49 * The PMU was already send the sleep command and will shut us down
50 * soon. We need to save all that is needed and setup the wakeup
51 * vector that will be called by the ROM on wakeup
53 _GLOBAL(low_sleep_handler)
54 #ifndef CONFIG_PPC_BOOK3S_32
71 /* Get a stable timebase and save it */
88 stw r4,SL_SPRG0+12(r1)
102 stw r4,SL_DBAT2+4(r1)
106 stw r4,SL_DBAT3+4(r1)
110 stw r4,SL_IBAT0+4(r1)
114 stw r4,SL_IBAT1+4(r1)
118 stw r4,SL_IBAT2+4(r1)
122 stw r4,SL_IBAT3+4(r1)
124 /* Backup various CPU config stuffs */
127 /* The ROM can wake us up via 2 different vectors:
128 * - On wallstreet & lombard, we must write a magic
129 * value 'Lars' at address 4 and a pointer to a
130 * memory location containing the PC to resume from
132 * - On Core99, we must store the wakeup vector at
133 * address 0x80 and eventually it's parameters
134 * at address 0x84. I've have some trouble with those
135 * parameters however and I no longer use them.
137 lis r5,grackle_wake_up@ha
138 addi r5,r5,grackle_wake_up@l
148 /* Setup stuffs at 0x80-0x84 for Core99 */
149 lis r3,core99_wake_up@ha
150 addi r3,r3,core99_wake_up@l
154 /* Store a pointer to our backup storage into
157 lis r3,sleep_storage@ha
158 addi r3,r3,sleep_storage@l
163 /* Flush & disable all caches */
164 bl flush_disable_caches
166 /* Turn off data relocation. */
167 mfmsr r3 /* Save MSR in r7 */
168 rlwinm r3,r3,0,28,26 /* Turn off DR bit */
174 /* Flush any pending L2 data prefetches to work around HW bug */
177 lwz r0,0(r3) /* perform cache-inhibited load to ROM */
178 sync /* (caches are disabled at this point) */
179 END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
182 * Set the HID0 and MSR for sleep.
185 rlwinm r2,r2,0,10,7 /* clear doze, nap */
186 oris r2,r2,HID0_SLEEP@h
192 /* This loop puts us back to sleep in case we have a spurrious
193 * wakeup so that the host bridge properly stays asleep. The
194 * CPU will be turned off, either after a known time (about 1
195 * second) on wallstreet & lombard, or as soon as the CPU enters
196 * SLEEP mode on core99
206 * Here is the resume code.
211 * Core99 machines resume here
212 * r4 has the physical address of SL_PC(sp) (unused)
214 _GLOBAL(core99_wake_up)
215 /* Make sure HID0 no longer contains any sleep bit and that data cache
219 rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */
220 rlwinm 3,r3,0,18,15 /* clear DCE, ICE */
227 ori r3,r3,MSR_EE|MSR_IP
228 xori r3,r3,MSR_EE|MSR_IP
235 /* Recover sleep storage */
236 lis r3,sleep_storage@ha
237 addi r3,r3,sleep_storage@l
241 /* Pass thru to older resume code ... */
243 * Here is the resume code for older machines.
244 * r1 has the physical address of SL_PC(sp).
249 /* Restore the kernel's segment registers before
250 * we do any r1 memory access as we are not sure they
251 * are in a sane state above the first 256Mb region
253 li r0,16 /* load up segment register values */
254 mtctr r0 /* for context 0 */
255 lis r3,0x2000 /* Ku = 1, VSID = 0 */
258 addi r3,r3,0x111 /* increment VSID */
259 addis r4,r4,0x1000 /* address of next segment */
266 /* Restore various CPU config stuffs */
267 bl __restore_cpu_setup
269 /* Make sure all FPRs have been initialized */
271 bl __init_fpu_registers
273 /* Invalidate & enable L1 cache, we don't care about
274 * whatever the ROM may have tried to write to memory
278 /* Restore the BATs, and SDR1. Then we can turn on the MMU. */
283 lwz r4,SL_SPRG0+4(r1)
285 lwz r4,SL_SPRG0+8(r1)
287 lwz r4,SL_SPRG0+12(r1)
292 lwz r4,SL_DBAT0+4(r1)
296 lwz r4,SL_DBAT1+4(r1)
300 lwz r4,SL_DBAT2+4(r1)
304 lwz r4,SL_DBAT3+4(r1)
308 lwz r4,SL_IBAT0+4(r1)
312 lwz r4,SL_IBAT1+4(r1)
316 lwz r4,SL_IBAT2+4(r1)
320 lwz r4,SL_IBAT3+4(r1)
323 BEGIN_MMU_FTR_SECTION
341 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
345 1: addic. r4,r4,-0x1000
350 /* restore the MSR and turn on the MMU */
354 /* get back the stack pointer */
365 /* Restore the callee-saved registers and return */
384 #endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
387 .balign L1_CACHE_BYTES
390 .balign L1_CACHE_BYTES, 0
392 #endif /* CONFIG_PPC_BOOK3S_32 */