2 * SMP support for power macintosh.
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/smp.h>
27 #include <linux/interrupt.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/hardirq.h>
34 #include <linux/cpu.h>
35 #include <linux/compiler.h>
37 #include <asm/ptrace.h>
38 #include <asm/atomic.h>
39 #include <asm/code-patching.h>
42 #include <asm/pgtable.h>
43 #include <asm/sections.h>
47 #include <asm/machdep.h>
48 #include <asm/pmac_feature.h>
51 #include <asm/cacheflush.h>
52 #include <asm/keylargo.h>
53 #include <asm/pmac_low_i2c.h>
54 #include <asm/pmac_pfunc.h>
61 #define DBG(fmt...) udbg_printf(fmt)
66 extern void __secondary_start_pmac_0(void);
67 extern int pmac_pfunc_base_install(void);
69 static void (*pmac_tb_freeze
)(int freeze
);
76 * Powersurge (old powermac SMP) support.
79 /* Addresses for powersurge registers */
80 #define HAMMERHEAD_BASE 0xf8000000
81 #define HHEAD_CONFIG 0x90
82 #define HHEAD_SEC_INTR 0xc0
84 /* register for interrupting the primary processor on the powersurge */
85 /* N.B. this is actually the ethernet ROM! */
86 #define PSURGE_PRI_INTR 0xf3019000
88 /* register for storing the start address for the secondary processor */
89 /* N.B. this is the PCI config space address register for the 1st bridge */
90 #define PSURGE_START 0xf2800000
92 /* Daystar/XLR8 4-CPU card */
93 #define PSURGE_QUAD_REG_ADDR 0xf8800000
95 #define PSURGE_QUAD_IRQ_SET 0
96 #define PSURGE_QUAD_IRQ_CLR 1
97 #define PSURGE_QUAD_IRQ_PRIMARY 2
98 #define PSURGE_QUAD_CKSTOP_CTL 3
99 #define PSURGE_QUAD_PRIMARY_ARB 4
100 #define PSURGE_QUAD_BOARD_ID 6
101 #define PSURGE_QUAD_WHICH_CPU 7
102 #define PSURGE_QUAD_CKSTOP_RDBK 8
103 #define PSURGE_QUAD_RESET_CTL 11
105 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
106 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
107 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
108 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
110 /* virtual addresses for the above */
111 static volatile u8 __iomem
*hhead_base
;
112 static volatile u8 __iomem
*quad_base
;
113 static volatile u32 __iomem
*psurge_pri_intr
;
114 static volatile u8 __iomem
*psurge_sec_intr
;
115 static volatile u32 __iomem
*psurge_start
;
117 /* values for psurge_type */
118 #define PSURGE_NONE -1
119 #define PSURGE_DUAL 0
120 #define PSURGE_QUAD_OKEE 1
121 #define PSURGE_QUAD_COTTON 2
122 #define PSURGE_QUAD_ICEGRASS 3
124 /* what sort of powersurge board we have */
125 static int psurge_type
= PSURGE_NONE
;
128 * Set and clear IPIs for powersurge.
130 static inline void psurge_set_ipi(int cpu
)
132 if (psurge_type
== PSURGE_NONE
)
135 in_be32(psurge_pri_intr
);
136 else if (psurge_type
== PSURGE_DUAL
)
137 out_8(psurge_sec_intr
, 0);
139 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET
, 1 << cpu
);
142 static inline void psurge_clr_ipi(int cpu
)
145 switch(psurge_type
) {
147 out_8(psurge_sec_intr
, ~0);
151 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, 1 << cpu
);
157 * On powersurge (old SMP powermac architecture) we don't have
158 * separate IPIs for separate messages like openpic does. Instead
159 * we have a bitmap for each processor, where a 1 bit means that
160 * the corresponding message is pending for that processor.
161 * Ideally each cpu's entry would be in a different cache line.
164 static unsigned long psurge_smp_message
[NR_CPUS
];
166 void psurge_smp_message_recv(void)
168 int cpu
= smp_processor_id();
171 /* clear interrupt */
174 if (num_online_cpus() < 2)
177 /* make sure there is a message there */
178 for (msg
= 0; msg
< 4; msg
++)
179 if (test_and_clear_bit(msg
, &psurge_smp_message
[cpu
]))
180 smp_message_recv(msg
);
183 irqreturn_t
psurge_primary_intr(int irq
, void *d
)
185 psurge_smp_message_recv();
189 static void smp_psurge_message_pass(int target
, int msg
)
193 if (num_online_cpus() < 2)
196 for_each_online_cpu(i
) {
197 if (target
== MSG_ALL
198 || (target
== MSG_ALL_BUT_SELF
&& i
!= smp_processor_id())
200 set_bit(msg
, &psurge_smp_message
[i
]);
207 * Determine a quad card presence. We read the board ID register, we
208 * force the data bus to change to something else, and we read it again.
209 * It it's stable, then the register probably exist (ugh !)
211 static int __init
psurge_quad_probe(void)
216 type
= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
);
217 if (type
< PSURGE_QUAD_OKEE
|| type
> PSURGE_QUAD_ICEGRASS
218 || type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
221 /* looks OK, try a slightly more rigorous test */
222 /* bogus is not necessarily cacheline-aligned,
223 though I don't suppose that really matters. -- paulus */
224 for (i
= 0; i
< 100; i
++) {
225 volatile u32 bogus
[8];
226 bogus
[(0+i
)%8] = 0x00000000;
227 bogus
[(1+i
)%8] = 0x55555555;
228 bogus
[(2+i
)%8] = 0xFFFFFFFF;
229 bogus
[(3+i
)%8] = 0xAAAAAAAA;
230 bogus
[(4+i
)%8] = 0x33333333;
231 bogus
[(5+i
)%8] = 0xCCCCCCCC;
232 bogus
[(6+i
)%8] = 0xCCCCCCCC;
233 bogus
[(7+i
)%8] = 0x33333333;
235 asm volatile("dcbf 0,%0" : : "r" (bogus
) : "memory");
237 if (type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
243 static void __init
psurge_quad_init(void)
247 if (ppc_md
.progress
) ppc_md
.progress("psurge_quad_init", 0x351);
248 procbits
= ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU
);
249 if (psurge_type
== PSURGE_QUAD_ICEGRASS
)
250 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
252 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
254 out_8(psurge_sec_intr
, ~0);
255 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, procbits
);
256 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
257 if (psurge_type
!= PSURGE_QUAD_ICEGRASS
)
258 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
259 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
261 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL
, procbits
);
263 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
267 static int __init
smp_psurge_probe(void)
270 struct device_node
*dn
;
272 /* We don't do SMP on the PPC601 -- paulus */
273 if (PVR_VER(mfspr(SPRN_PVR
)) == 1)
277 * The powersurge cpu board can be used in the generation
278 * of powermacs that have a socket for an upgradeable cpu card,
279 * including the 7500, 8500, 9500, 9600.
280 * The device tree doesn't tell you if you have 2 cpus because
281 * OF doesn't know anything about the 2nd processor.
282 * Instead we look for magic bits in magic registers,
283 * in the hammerhead memory controller in the case of the
284 * dual-cpu powersurge board. -- paulus.
286 dn
= of_find_node_by_name(NULL
, "hammerhead");
291 hhead_base
= ioremap(HAMMERHEAD_BASE
, 0x800);
292 quad_base
= ioremap(PSURGE_QUAD_REG_ADDR
, 1024);
293 psurge_sec_intr
= hhead_base
+ HHEAD_SEC_INTR
;
295 psurge_type
= psurge_quad_probe();
296 if (psurge_type
!= PSURGE_DUAL
) {
298 /* All released cards using this HW design have 4 CPUs */
300 /* No sure how timebase sync works on those, let's use SW */
301 smp_ops
->give_timebase
= smp_generic_give_timebase
;
302 smp_ops
->take_timebase
= smp_generic_take_timebase
;
305 if ((in_8(hhead_base
+ HHEAD_CONFIG
) & 0x02) == 0) {
306 /* not a dual-cpu card */
308 psurge_type
= PSURGE_NONE
;
314 psurge_start
= ioremap(PSURGE_START
, 4);
315 psurge_pri_intr
= ioremap(PSURGE_PRI_INTR
, 4);
317 /* This is necessary because OF doesn't know about the
318 * secondary cpu(s), and thus there aren't nodes in the
319 * device tree for them, and smp_setup_cpu_maps hasn't
320 * set their bits in cpu_present_mask.
324 for (i
= 1; i
< ncpus
; ++i
)
325 set_cpu_present(i
, true);
327 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_probe - done", 0x352);
332 static int __init
smp_psurge_kick_cpu(int nr
)
334 unsigned long start
= __pa(__secondary_start_pmac_0
) + nr
* 8;
335 unsigned long a
, flags
;
338 /* Defining this here is evil ... but I prefer hiding that
339 * crap to avoid giving people ideas that they can do the
342 extern volatile unsigned int cpu_callin_map
[NR_CPUS
];
344 /* may need to flush here if secondary bats aren't setup */
345 for (a
= KERNELBASE
; a
< KERNELBASE
+ 0x800000; a
+= 32)
346 asm volatile("dcbf 0,%0" : : "r" (a
) : "memory");
347 asm volatile("sync");
349 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu", 0x353);
351 /* This is going to freeze the timeebase, we disable interrupts */
352 local_irq_save(flags
);
354 out_be32(psurge_start
, start
);
360 * We can't use udelay here because the timebase is now frozen.
362 for (i
= 0; i
< 2000; ++i
)
363 asm volatile("nop" : : : "memory");
367 * Also, because the timebase is frozen, we must not return to the
368 * caller which will try to do udelay's etc... Instead, we wait -here-
369 * for the CPU to callin.
371 for (i
= 0; i
< 100000 && !cpu_callin_map
[nr
]; ++i
) {
372 for (j
= 1; j
< 10000; j
++)
373 asm volatile("nop" : : : "memory");
374 asm volatile("sync" : : : "memory");
376 if (!cpu_callin_map
[nr
])
379 /* And we do the TB sync here too for standard dual CPU cards */
380 if (psurge_type
== PSURGE_DUAL
) {
392 /* now interrupt the secondary, restarting both TBs */
393 if (psurge_type
== PSURGE_DUAL
)
396 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu - done", 0x354);
401 static struct irqaction psurge_irqaction
= {
402 .handler
= psurge_primary_intr
,
403 .flags
= IRQF_DISABLED
,
404 .name
= "primary IPI",
407 static void __init
smp_psurge_setup_cpu(int cpu_nr
)
412 /* reset the entry point so if we get another intr we won't
413 * try to startup again */
414 out_be32(psurge_start
, 0x100);
415 if (setup_irq(irq_create_mapping(NULL
, 30), &psurge_irqaction
))
416 printk(KERN_ERR
"Couldn't get primary IPI interrupt");
419 void __init
smp_psurge_take_timebase(void)
421 if (psurge_type
!= PSURGE_DUAL
)
429 set_tb(timebase
>> 32, timebase
& 0xffffffff);
432 set_dec(tb_ticks_per_jiffy
/2);
435 void __init
smp_psurge_give_timebase(void)
437 /* Nothing to do here */
440 /* PowerSurge-style Macs */
441 struct smp_ops_t psurge_smp_ops
= {
442 .message_pass
= smp_psurge_message_pass
,
443 .probe
= smp_psurge_probe
,
444 .kick_cpu
= smp_psurge_kick_cpu
,
445 .setup_cpu
= smp_psurge_setup_cpu
,
446 .give_timebase
= smp_psurge_give_timebase
,
447 .take_timebase
= smp_psurge_take_timebase
,
449 #endif /* CONFIG_PPC32 - actually powersurge support */
452 * Core 99 and later support
456 static void smp_core99_give_timebase(void)
460 local_irq_save(flags
);
465 (*pmac_tb_freeze
)(1);
472 (*pmac_tb_freeze
)(0);
475 local_irq_restore(flags
);
479 static void __devinit
smp_core99_take_timebase(void)
483 local_irq_save(flags
);
490 set_tb(timebase
>> 32, timebase
& 0xffffffff);
494 local_irq_restore(flags
);
499 * G5s enable/disable the timebase via an i2c-connected clock chip.
501 static struct pmac_i2c_bus
*pmac_tb_clock_chip_host
;
502 static u8 pmac_tb_pulsar_addr
;
504 static void smp_core99_cypress_tb_freeze(int freeze
)
509 /* Strangely, the device-tree says address is 0xd2, but darwin
512 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
513 pmac_i2c_mode_combined
);
514 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
515 0xd0 | pmac_i2c_read
,
520 data
= (data
& 0xf3) | (freeze
? 0x00 : 0x0c);
522 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
523 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
524 0xd0 | pmac_i2c_write
,
529 printk("Cypress Timebase %s rc: %d\n",
530 freeze
? "freeze" : "unfreeze", rc
);
531 panic("Timebase freeze failed !\n");
536 static void smp_core99_pulsar_tb_freeze(int freeze
)
541 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
542 pmac_i2c_mode_combined
);
543 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
544 pmac_tb_pulsar_addr
| pmac_i2c_read
,
549 data
= (data
& 0x88) | (freeze
? 0x11 : 0x22);
551 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
552 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
553 pmac_tb_pulsar_addr
| pmac_i2c_write
,
557 printk(KERN_ERR
"Pulsar Timebase %s rc: %d\n",
558 freeze
? "freeze" : "unfreeze", rc
);
559 panic("Timebase freeze failed !\n");
563 static void __init
smp_core99_setup_i2c_hwsync(int ncpus
)
565 struct device_node
*cc
= NULL
;
566 struct device_node
*p
;
567 const char *name
= NULL
;
571 /* Look for the clock chip */
572 while ((cc
= of_find_node_by_name(cc
, "i2c-hwclock")) != NULL
) {
573 p
= of_get_parent(cc
);
574 ok
= p
&& of_device_is_compatible(p
, "uni-n-i2c");
579 pmac_tb_clock_chip_host
= pmac_i2c_find_bus(cc
);
580 if (pmac_tb_clock_chip_host
== NULL
)
582 reg
= of_get_property(cc
, "reg", NULL
);
587 if (of_device_is_compatible(cc
,"pulsar-legacy-slewing")) {
588 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
589 pmac_tb_pulsar_addr
= 0xd2;
591 } else if (of_device_is_compatible(cc
, "cy28508")) {
592 pmac_tb_freeze
= smp_core99_cypress_tb_freeze
;
597 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
598 pmac_tb_pulsar_addr
= 0xd4;
602 if (pmac_tb_freeze
!= NULL
)
605 if (pmac_tb_freeze
!= NULL
) {
606 /* Open i2c bus for synchronous access */
607 if (pmac_i2c_open(pmac_tb_clock_chip_host
, 1)) {
608 printk(KERN_ERR
"Failed top open i2c bus for clock"
609 " sync, fallback to software sync !\n");
612 printk(KERN_INFO
"Processor timebase sync using %s i2c clock\n",
617 pmac_tb_freeze
= NULL
;
618 pmac_tb_clock_chip_host
= NULL
;
624 * Newer G5s uses a platform function
627 static void smp_core99_pfunc_tb_freeze(int freeze
)
629 struct device_node
*cpus
;
630 struct pmf_args args
;
632 cpus
= of_find_node_by_path("/cpus");
633 BUG_ON(cpus
== NULL
);
635 args
.u
[0].v
= !freeze
;
636 pmf_call_function(cpus
, "cpu-timebase", &args
);
640 #else /* CONFIG_PPC64 */
643 * SMP G4 use a GPIO to enable/disable the timebase.
646 static unsigned int core99_tb_gpio
; /* Timebase freeze GPIO */
648 static void smp_core99_gpio_tb_freeze(int freeze
)
651 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 4);
653 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 0);
654 pmac_call_feature(PMAC_FTR_READ_GPIO
, NULL
, core99_tb_gpio
, 0);
658 #endif /* !CONFIG_PPC64 */
660 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
661 volatile static long int core99_l2_cache
;
662 volatile static long int core99_l3_cache
;
664 static void __devinit
core99_init_caches(int cpu
)
667 if (!cpu_has_feature(CPU_FTR_L2CR
))
671 core99_l2_cache
= _get_L2CR();
672 printk("CPU0: L2CR is %lx\n", core99_l2_cache
);
674 printk("CPU%d: L2CR was %lx\n", cpu
, _get_L2CR());
676 _set_L2CR(core99_l2_cache
);
677 printk("CPU%d: L2CR set to %lx\n", cpu
, core99_l2_cache
);
680 if (!cpu_has_feature(CPU_FTR_L3CR
))
684 core99_l3_cache
= _get_L3CR();
685 printk("CPU0: L3CR is %lx\n", core99_l3_cache
);
687 printk("CPU%d: L3CR was %lx\n", cpu
, _get_L3CR());
689 _set_L3CR(core99_l3_cache
);
690 printk("CPU%d: L3CR set to %lx\n", cpu
, core99_l3_cache
);
692 #endif /* !CONFIG_PPC64 */
695 static void __init
smp_core99_setup(int ncpus
)
699 /* i2c based HW sync on some G5s */
700 if (of_machine_is_compatible("PowerMac7,2") ||
701 of_machine_is_compatible("PowerMac7,3") ||
702 of_machine_is_compatible("RackMac3,1"))
703 smp_core99_setup_i2c_hwsync(ncpus
);
705 /* pfunc based HW sync on recent G5s */
706 if (pmac_tb_freeze
== NULL
) {
707 struct device_node
*cpus
=
708 of_find_node_by_path("/cpus");
710 of_get_property(cpus
, "platform-cpu-timebase", NULL
)) {
711 pmac_tb_freeze
= smp_core99_pfunc_tb_freeze
;
712 printk(KERN_INFO
"Processor timebase sync using"
713 " platform function\n");
717 #else /* CONFIG_PPC64 */
719 /* GPIO based HW sync on ppc32 Core99 */
720 if (pmac_tb_freeze
== NULL
&& !of_machine_is_compatible("MacRISC4")) {
721 struct device_node
*cpu
;
722 const u32
*tbprop
= NULL
;
724 core99_tb_gpio
= KL_GPIO_TB_ENABLE
; /* default value */
725 cpu
= of_find_node_by_type(NULL
, "cpu");
727 tbprop
= of_get_property(cpu
, "timebase-enable", NULL
);
729 core99_tb_gpio
= *tbprop
;
732 pmac_tb_freeze
= smp_core99_gpio_tb_freeze
;
733 printk(KERN_INFO
"Processor timebase sync using"
734 " GPIO 0x%02x\n", core99_tb_gpio
);
737 #endif /* CONFIG_PPC64 */
739 /* No timebase sync, fallback to software */
740 if (pmac_tb_freeze
== NULL
) {
741 smp_ops
->give_timebase
= smp_generic_give_timebase
;
742 smp_ops
->take_timebase
= smp_generic_take_timebase
;
743 printk(KERN_INFO
"Processor timebase sync using software\n");
750 /* XXX should get this from reg properties */
751 for (i
= 1; i
< ncpus
; ++i
)
752 set_hard_smp_processor_id(i
, i
);
756 /* 32 bits SMP can't NAP */
757 if (!of_machine_is_compatible("MacRISC4"))
761 static int __init
smp_core99_probe(void)
763 struct device_node
*cpus
;
766 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_probe", 0x345);
768 /* Count CPUs in the device-tree */
769 for (cpus
= NULL
; (cpus
= of_find_node_by_type(cpus
, "cpu")) != NULL
;)
772 printk(KERN_INFO
"PowerMac SMP probe found %d cpus\n", ncpus
);
774 /* Nothing more to do if less than 2 of them */
778 /* We need to perform some early initialisations before we can start
779 * setting up SMP as we are running before initcalls
781 pmac_pfunc_base_install();
784 /* Setup various bits like timebase sync method, ability to nap, ... */
785 smp_core99_setup(ncpus
);
790 /* Collect l2cr and l3cr values from CPU 0 */
791 core99_init_caches(0);
796 static int __devinit
smp_core99_kick_cpu(int nr
)
798 unsigned int save_vector
;
799 unsigned long target
, flags
;
800 unsigned int *vector
= (unsigned int *)(PAGE_OFFSET
+0x100);
802 if (nr
< 0 || nr
> 3)
806 ppc_md
.progress("smp_core99_kick_cpu", 0x346);
808 local_irq_save(flags
);
810 /* Save reset vector */
811 save_vector
= *vector
;
813 /* Setup fake reset vector that does
814 * b __secondary_start_pmac_0 + nr*8
816 target
= (unsigned long) __secondary_start_pmac_0
+ nr
* 8;
817 patch_branch(vector
, target
, BRANCH_SET_LINK
);
819 /* Put some life in our friend */
820 pmac_call_feature(PMAC_FTR_RESET_CPU
, NULL
, nr
, 0);
822 /* FIXME: We wait a bit for the CPU to take the exception, I should
823 * instead wait for the entry code to set something for me. Well,
824 * ideally, all that crap will be done in prom.c and the CPU left
825 * in a RAM-based wait loop like CHRP.
829 /* Restore our exception vector */
830 *vector
= save_vector
;
831 flush_icache_range((unsigned long) vector
, (unsigned long) vector
+ 4);
833 local_irq_restore(flags
);
834 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_kick_cpu done", 0x347);
839 static void __devinit
smp_core99_setup_cpu(int cpu_nr
)
843 core99_init_caches(cpu_nr
);
846 mpic_setup_this_cpu();
850 #ifdef CONFIG_HOTPLUG_CPU
851 static int smp_core99_cpu_notify(struct notifier_block
*self
,
852 unsigned long action
, void *hcpu
)
858 case CPU_UP_PREPARE_FROZEN
:
859 /* Open i2c bus if it was used for tb sync */
860 if (pmac_tb_clock_chip_host
) {
861 rc
= pmac_i2c_open(pmac_tb_clock_chip_host
, 1);
863 pr_err("Failed to open i2c bus for time sync\n");
864 return notifier_from_errno(rc
);
869 case CPU_UP_CANCELED
:
870 /* Close i2c bus if it was used for tb sync */
871 if (pmac_tb_clock_chip_host
)
872 pmac_i2c_close(pmac_tb_clock_chip_host
);
880 static struct notifier_block __cpuinitdata smp_core99_cpu_nb
= {
881 .notifier_call
= smp_core99_cpu_notify
,
883 #endif /* CONFIG_HOTPLUG_CPU */
885 static void __init
smp_core99_bringup_done(void)
887 extern void g5_phy_disable_cpu1(void);
889 /* Close i2c bus if it was used for tb sync */
890 if (pmac_tb_clock_chip_host
)
891 pmac_i2c_close(pmac_tb_clock_chip_host
);
893 /* If we didn't start the second CPU, we must take
896 if (of_machine_is_compatible("MacRISC4") &&
897 num_online_cpus() < 2) {
898 set_cpu_present(1, false);
899 g5_phy_disable_cpu1();
901 #ifdef CONFIG_HOTPLUG_CPU
902 register_cpu_notifier(&smp_core99_cpu_nb
);
906 ppc_md
.progress("smp_core99_bringup_done", 0x349);
908 #endif /* CONFIG_PPC64 */
910 #ifdef CONFIG_HOTPLUG_CPU
912 static int smp_core99_cpu_disable(void)
914 int rc
= generic_cpu_disable();
918 mpic_cpu_set_priority(0xf);
925 static void pmac_cpu_die(void)
927 int cpu
= smp_processor_id();
931 pr_debug("CPU%d offline\n", cpu
);
932 generic_set_cpu_dead(cpu
);
938 #else /* CONFIG_PPC32 */
940 static void pmac_cpu_die(void)
942 int cpu
= smp_processor_id();
948 * turn off as much as possible, we'll be
949 * kicked out as this will only be invoked
950 * on core99 platforms for now ...
953 printk(KERN_INFO
"CPU#%d offline\n", cpu
);
954 generic_set_cpu_dead(cpu
);
958 * Re-enable interrupts. The NAP code needs to enable them
959 * anyways, do it now so we deal with the case where one already
960 * happened while soft-disabled.
961 * We shouldn't get any external interrupts, only decrementer, and the
962 * decrementer handler is safe for use on offline CPUs
967 /* let's not take timer interrupts too often ... */
975 #endif /* else CONFIG_PPC32 */
976 #endif /* CONFIG_HOTPLUG_CPU */
978 /* Core99 Macs (dual G4s and G5s) */
979 struct smp_ops_t core99_smp_ops
= {
980 .message_pass
= smp_mpic_message_pass
,
981 .probe
= smp_core99_probe
,
983 .bringup_done
= smp_core99_bringup_done
,
985 .kick_cpu
= smp_core99_kick_cpu
,
986 .setup_cpu
= smp_core99_setup_cpu
,
987 .give_timebase
= smp_core99_give_timebase
,
988 .take_timebase
= smp_core99_take_timebase
,
989 #if defined(CONFIG_HOTPLUG_CPU)
990 .cpu_disable
= smp_core99_cpu_disable
,
991 .cpu_die
= generic_cpu_die
,
995 void __init
pmac_setup_smp(void)
997 struct device_node
*np
;
999 /* Check for Core99 */
1000 np
= of_find_node_by_name(NULL
, "uni-n");
1002 np
= of_find_node_by_name(NULL
, "u3");
1004 np
= of_find_node_by_name(NULL
, "u4");
1007 smp_ops
= &core99_smp_ops
;
1011 /* We have to set bits in cpu_possible_mask here since the
1012 * secondary CPU(s) aren't in the device tree. Various
1013 * things won't be initialized for CPUs not in the possible
1014 * map, so we really need to fix it up here.
1018 for (cpu
= 1; cpu
< 4 && cpu
< NR_CPUS
; ++cpu
)
1019 set_cpu_possible(cpu
, true);
1020 smp_ops
= &psurge_smp_ops
;
1022 #endif /* CONFIG_PPC32 */
1024 #ifdef CONFIG_HOTPLUG_CPU
1025 ppc_md
.cpu_die
= pmac_cpu_die
;