2 * SMP support for power macintosh.
4 * We support both the old "powersurge" SMP architecture
5 * and the current Core99 (G4 PowerMac) machines.
7 * Note that we don't support the very first rev. of
8 * Apple/DayStar 2 CPUs board, the one with the funky
9 * watchdog. Hopefully, none of these should be there except
10 * maybe internally to Apple. I should probably still add some
11 * code to detect this card though and disable SMP. --BenH.
13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14 * and Ben Herrenschmidt <benh@kernel.crashing.org>.
16 * Support for DayStar quad CPU cards
17 * Copyright (C) XLR8, Inc. 1994-2000
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/sched/hotplug.h>
27 #include <linux/smp.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/delay.h>
31 #include <linux/init.h>
32 #include <linux/spinlock.h>
33 #include <linux/errno.h>
34 #include <linux/hardirq.h>
35 #include <linux/cpu.h>
36 #include <linux/compiler.h>
38 #include <asm/ptrace.h>
39 #include <linux/atomic.h>
40 #include <asm/code-patching.h>
43 #include <asm/pgtable.h>
44 #include <asm/sections.h>
48 #include <asm/machdep.h>
49 #include <asm/pmac_feature.h>
52 #include <asm/cacheflush.h>
53 #include <asm/keylargo.h>
54 #include <asm/pmac_low_i2c.h>
55 #include <asm/pmac_pfunc.h>
62 #define DBG(fmt...) udbg_printf(fmt)
67 extern void __secondary_start_pmac_0(void);
68 extern int pmac_pfunc_base_install(void);
70 static void (*pmac_tb_freeze
)(int freeze
);
74 #ifdef CONFIG_PPC_PMAC32_PSURGE
77 * Powersurge (old powermac SMP) support.
80 /* Addresses for powersurge registers */
81 #define HAMMERHEAD_BASE 0xf8000000
82 #define HHEAD_CONFIG 0x90
83 #define HHEAD_SEC_INTR 0xc0
85 /* register for interrupting the primary processor on the powersurge */
86 /* N.B. this is actually the ethernet ROM! */
87 #define PSURGE_PRI_INTR 0xf3019000
89 /* register for storing the start address for the secondary processor */
90 /* N.B. this is the PCI config space address register for the 1st bridge */
91 #define PSURGE_START 0xf2800000
93 /* Daystar/XLR8 4-CPU card */
94 #define PSURGE_QUAD_REG_ADDR 0xf8800000
96 #define PSURGE_QUAD_IRQ_SET 0
97 #define PSURGE_QUAD_IRQ_CLR 1
98 #define PSURGE_QUAD_IRQ_PRIMARY 2
99 #define PSURGE_QUAD_CKSTOP_CTL 3
100 #define PSURGE_QUAD_PRIMARY_ARB 4
101 #define PSURGE_QUAD_BOARD_ID 6
102 #define PSURGE_QUAD_WHICH_CPU 7
103 #define PSURGE_QUAD_CKSTOP_RDBK 8
104 #define PSURGE_QUAD_RESET_CTL 11
106 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v)))
107 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f)
108 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
109 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
111 /* virtual addresses for the above */
112 static volatile u8 __iomem
*hhead_base
;
113 static volatile u8 __iomem
*quad_base
;
114 static volatile u32 __iomem
*psurge_pri_intr
;
115 static volatile u8 __iomem
*psurge_sec_intr
;
116 static volatile u32 __iomem
*psurge_start
;
118 /* values for psurge_type */
119 #define PSURGE_NONE -1
120 #define PSURGE_DUAL 0
121 #define PSURGE_QUAD_OKEE 1
122 #define PSURGE_QUAD_COTTON 2
123 #define PSURGE_QUAD_ICEGRASS 3
125 /* what sort of powersurge board we have */
126 static int psurge_type
= PSURGE_NONE
;
128 /* irq for secondary cpus to report */
129 static struct irq_domain
*psurge_host
;
130 int psurge_secondary_virq
;
133 * Set and clear IPIs for powersurge.
135 static inline void psurge_set_ipi(int cpu
)
137 if (psurge_type
== PSURGE_NONE
)
140 in_be32(psurge_pri_intr
);
141 else if (psurge_type
== PSURGE_DUAL
)
142 out_8(psurge_sec_intr
, 0);
144 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET
, 1 << cpu
);
147 static inline void psurge_clr_ipi(int cpu
)
150 switch(psurge_type
) {
152 out_8(psurge_sec_intr
, ~0);
156 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, 1 << cpu
);
162 * On powersurge (old SMP powermac architecture) we don't have
163 * separate IPIs for separate messages like openpic does. Instead
164 * use the generic demux helpers
167 static irqreturn_t
psurge_ipi_intr(int irq
, void *d
)
169 psurge_clr_ipi(smp_processor_id());
175 static void smp_psurge_cause_ipi(int cpu
, unsigned long data
)
180 static int psurge_host_map(struct irq_domain
*h
, unsigned int virq
,
183 irq_set_chip_and_handler(virq
, &dummy_irq_chip
, handle_percpu_irq
);
188 static const struct irq_domain_ops psurge_host_ops
= {
189 .map
= psurge_host_map
,
192 static int psurge_secondary_ipi_init(void)
196 psurge_host
= irq_domain_add_nomap(NULL
, ~0, &psurge_host_ops
, NULL
);
199 psurge_secondary_virq
= irq_create_direct_mapping(psurge_host
);
201 if (psurge_secondary_virq
)
202 rc
= request_irq(psurge_secondary_virq
, psurge_ipi_intr
,
203 IRQF_PERCPU
| IRQF_NO_THREAD
, "IPI", NULL
);
206 pr_err("Failed to setup secondary cpu IPI\n");
212 * Determine a quad card presence. We read the board ID register, we
213 * force the data bus to change to something else, and we read it again.
214 * It it's stable, then the register probably exist (ugh !)
216 static int __init
psurge_quad_probe(void)
221 type
= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
);
222 if (type
< PSURGE_QUAD_OKEE
|| type
> PSURGE_QUAD_ICEGRASS
223 || type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
226 /* looks OK, try a slightly more rigorous test */
227 /* bogus is not necessarily cacheline-aligned,
228 though I don't suppose that really matters. -- paulus */
229 for (i
= 0; i
< 100; i
++) {
230 volatile u32 bogus
[8];
231 bogus
[(0+i
)%8] = 0x00000000;
232 bogus
[(1+i
)%8] = 0x55555555;
233 bogus
[(2+i
)%8] = 0xFFFFFFFF;
234 bogus
[(3+i
)%8] = 0xAAAAAAAA;
235 bogus
[(4+i
)%8] = 0x33333333;
236 bogus
[(5+i
)%8] = 0xCCCCCCCC;
237 bogus
[(6+i
)%8] = 0xCCCCCCCC;
238 bogus
[(7+i
)%8] = 0x33333333;
240 asm volatile("dcbf 0,%0" : : "r" (bogus
) : "memory");
242 if (type
!= PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID
))
248 static void __init
psurge_quad_init(void)
252 if (ppc_md
.progress
) ppc_md
.progress("psurge_quad_init", 0x351);
253 procbits
= ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU
);
254 if (psurge_type
== PSURGE_QUAD_ICEGRASS
)
255 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
257 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
259 out_8(psurge_sec_intr
, ~0);
260 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR
, procbits
);
261 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL
, procbits
);
262 if (psurge_type
!= PSURGE_QUAD_ICEGRASS
)
263 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL
, procbits
);
264 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
266 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL
, procbits
);
268 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB
, procbits
);
272 static void __init
smp_psurge_probe(void)
275 struct device_node
*dn
;
277 /* We don't do SMP on the PPC601 -- paulus */
278 if (PVR_VER(mfspr(SPRN_PVR
)) == 1)
282 * The powersurge cpu board can be used in the generation
283 * of powermacs that have a socket for an upgradeable cpu card,
284 * including the 7500, 8500, 9500, 9600.
285 * The device tree doesn't tell you if you have 2 cpus because
286 * OF doesn't know anything about the 2nd processor.
287 * Instead we look for magic bits in magic registers,
288 * in the hammerhead memory controller in the case of the
289 * dual-cpu powersurge board. -- paulus.
291 dn
= of_find_node_by_name(NULL
, "hammerhead");
296 hhead_base
= ioremap(HAMMERHEAD_BASE
, 0x800);
297 quad_base
= ioremap(PSURGE_QUAD_REG_ADDR
, 1024);
298 psurge_sec_intr
= hhead_base
+ HHEAD_SEC_INTR
;
300 psurge_type
= psurge_quad_probe();
301 if (psurge_type
!= PSURGE_DUAL
) {
303 /* All released cards using this HW design have 4 CPUs */
305 /* No sure how timebase sync works on those, let's use SW */
306 smp_ops
->give_timebase
= smp_generic_give_timebase
;
307 smp_ops
->take_timebase
= smp_generic_take_timebase
;
310 if ((in_8(hhead_base
+ HHEAD_CONFIG
) & 0x02) == 0) {
311 /* not a dual-cpu card */
313 psurge_type
= PSURGE_NONE
;
319 if (psurge_secondary_ipi_init())
322 psurge_start
= ioremap(PSURGE_START
, 4);
323 psurge_pri_intr
= ioremap(PSURGE_PRI_INTR
, 4);
325 /* This is necessary because OF doesn't know about the
326 * secondary cpu(s), and thus there aren't nodes in the
327 * device tree for them, and smp_setup_cpu_maps hasn't
328 * set their bits in cpu_present_mask.
332 for (i
= 1; i
< ncpus
; ++i
)
333 set_cpu_present(i
, true);
335 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_probe - done", 0x352);
338 static int __init
smp_psurge_kick_cpu(int nr
)
340 unsigned long start
= __pa(__secondary_start_pmac_0
) + nr
* 8;
341 unsigned long a
, flags
;
344 /* Defining this here is evil ... but I prefer hiding that
345 * crap to avoid giving people ideas that they can do the
348 extern volatile unsigned int cpu_callin_map
[NR_CPUS
];
350 /* may need to flush here if secondary bats aren't setup */
351 for (a
= KERNELBASE
; a
< KERNELBASE
+ 0x800000; a
+= 32)
352 asm volatile("dcbf 0,%0" : : "r" (a
) : "memory");
353 asm volatile("sync");
355 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu", 0x353);
357 /* This is going to freeze the timeebase, we disable interrupts */
358 local_irq_save(flags
);
360 out_be32(psurge_start
, start
);
366 * We can't use udelay here because the timebase is now frozen.
368 for (i
= 0; i
< 2000; ++i
)
369 asm volatile("nop" : : : "memory");
373 * Also, because the timebase is frozen, we must not return to the
374 * caller which will try to do udelay's etc... Instead, we wait -here-
375 * for the CPU to callin.
377 for (i
= 0; i
< 100000 && !cpu_callin_map
[nr
]; ++i
) {
378 for (j
= 1; j
< 10000; j
++)
379 asm volatile("nop" : : : "memory");
380 asm volatile("sync" : : : "memory");
382 if (!cpu_callin_map
[nr
])
385 /* And we do the TB sync here too for standard dual CPU cards */
386 if (psurge_type
== PSURGE_DUAL
) {
398 /* now interrupt the secondary, restarting both TBs */
399 if (psurge_type
== PSURGE_DUAL
)
402 if (ppc_md
.progress
) ppc_md
.progress("smp_psurge_kick_cpu - done", 0x354);
407 static struct irqaction psurge_irqaction
= {
408 .handler
= psurge_ipi_intr
,
409 .flags
= IRQF_PERCPU
| IRQF_NO_THREAD
,
410 .name
= "primary IPI",
413 static void __init
smp_psurge_setup_cpu(int cpu_nr
)
415 if (cpu_nr
!= 0 || !psurge_start
)
418 /* reset the entry point so if we get another intr we won't
419 * try to startup again */
420 out_be32(psurge_start
, 0x100);
421 if (setup_irq(irq_create_mapping(NULL
, 30), &psurge_irqaction
))
422 printk(KERN_ERR
"Couldn't get primary IPI interrupt");
425 void __init
smp_psurge_take_timebase(void)
427 if (psurge_type
!= PSURGE_DUAL
)
435 set_tb(timebase
>> 32, timebase
& 0xffffffff);
438 set_dec(tb_ticks_per_jiffy
/2);
441 void __init
smp_psurge_give_timebase(void)
443 /* Nothing to do here */
446 /* PowerSurge-style Macs */
447 struct smp_ops_t psurge_smp_ops
= {
448 .message_pass
= NULL
, /* Use smp_muxed_ipi_message_pass */
449 .cause_ipi
= smp_psurge_cause_ipi
,
450 .probe
= smp_psurge_probe
,
451 .kick_cpu
= smp_psurge_kick_cpu
,
452 .setup_cpu
= smp_psurge_setup_cpu
,
453 .give_timebase
= smp_psurge_give_timebase
,
454 .take_timebase
= smp_psurge_take_timebase
,
456 #endif /* CONFIG_PPC_PMAC32_PSURGE */
459 * Core 99 and later support
463 static void smp_core99_give_timebase(void)
467 local_irq_save(flags
);
472 (*pmac_tb_freeze
)(1);
479 (*pmac_tb_freeze
)(0);
482 local_irq_restore(flags
);
486 static void smp_core99_take_timebase(void)
490 local_irq_save(flags
);
497 set_tb(timebase
>> 32, timebase
& 0xffffffff);
501 local_irq_restore(flags
);
506 * G5s enable/disable the timebase via an i2c-connected clock chip.
508 static struct pmac_i2c_bus
*pmac_tb_clock_chip_host
;
509 static u8 pmac_tb_pulsar_addr
;
511 static void smp_core99_cypress_tb_freeze(int freeze
)
516 /* Strangely, the device-tree says address is 0xd2, but darwin
519 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
520 pmac_i2c_mode_combined
);
521 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
522 0xd0 | pmac_i2c_read
,
527 data
= (data
& 0xf3) | (freeze
? 0x00 : 0x0c);
529 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
530 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
531 0xd0 | pmac_i2c_write
,
536 printk("Cypress Timebase %s rc: %d\n",
537 freeze
? "freeze" : "unfreeze", rc
);
538 panic("Timebase freeze failed !\n");
543 static void smp_core99_pulsar_tb_freeze(int freeze
)
548 pmac_i2c_setmode(pmac_tb_clock_chip_host
,
549 pmac_i2c_mode_combined
);
550 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
551 pmac_tb_pulsar_addr
| pmac_i2c_read
,
556 data
= (data
& 0x88) | (freeze
? 0x11 : 0x22);
558 pmac_i2c_setmode(pmac_tb_clock_chip_host
, pmac_i2c_mode_stdsub
);
559 rc
= pmac_i2c_xfer(pmac_tb_clock_chip_host
,
560 pmac_tb_pulsar_addr
| pmac_i2c_write
,
564 printk(KERN_ERR
"Pulsar Timebase %s rc: %d\n",
565 freeze
? "freeze" : "unfreeze", rc
);
566 panic("Timebase freeze failed !\n");
570 static void __init
smp_core99_setup_i2c_hwsync(int ncpus
)
572 struct device_node
*cc
= NULL
;
573 struct device_node
*p
;
574 const char *name
= NULL
;
578 /* Look for the clock chip */
579 for_each_node_by_name(cc
, "i2c-hwclock") {
580 p
= of_get_parent(cc
);
581 ok
= p
&& of_device_is_compatible(p
, "uni-n-i2c");
586 pmac_tb_clock_chip_host
= pmac_i2c_find_bus(cc
);
587 if (pmac_tb_clock_chip_host
== NULL
)
589 reg
= of_get_property(cc
, "reg", NULL
);
594 if (of_device_is_compatible(cc
,"pulsar-legacy-slewing")) {
595 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
596 pmac_tb_pulsar_addr
= 0xd2;
598 } else if (of_device_is_compatible(cc
, "cy28508")) {
599 pmac_tb_freeze
= smp_core99_cypress_tb_freeze
;
604 pmac_tb_freeze
= smp_core99_pulsar_tb_freeze
;
605 pmac_tb_pulsar_addr
= 0xd4;
609 if (pmac_tb_freeze
!= NULL
)
612 if (pmac_tb_freeze
!= NULL
) {
613 /* Open i2c bus for synchronous access */
614 if (pmac_i2c_open(pmac_tb_clock_chip_host
, 1)) {
615 printk(KERN_ERR
"Failed top open i2c bus for clock"
616 " sync, fallback to software sync !\n");
619 printk(KERN_INFO
"Processor timebase sync using %s i2c clock\n",
624 pmac_tb_freeze
= NULL
;
625 pmac_tb_clock_chip_host
= NULL
;
631 * Newer G5s uses a platform function
634 static void smp_core99_pfunc_tb_freeze(int freeze
)
636 struct device_node
*cpus
;
637 struct pmf_args args
;
639 cpus
= of_find_node_by_path("/cpus");
640 BUG_ON(cpus
== NULL
);
642 args
.u
[0].v
= !freeze
;
643 pmf_call_function(cpus
, "cpu-timebase", &args
);
647 #else /* CONFIG_PPC64 */
650 * SMP G4 use a GPIO to enable/disable the timebase.
653 static unsigned int core99_tb_gpio
; /* Timebase freeze GPIO */
655 static void smp_core99_gpio_tb_freeze(int freeze
)
658 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 4);
660 pmac_call_feature(PMAC_FTR_WRITE_GPIO
, NULL
, core99_tb_gpio
, 0);
661 pmac_call_feature(PMAC_FTR_READ_GPIO
, NULL
, core99_tb_gpio
, 0);
665 #endif /* !CONFIG_PPC64 */
667 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
668 volatile static long int core99_l2_cache
;
669 volatile static long int core99_l3_cache
;
671 static void core99_init_caches(int cpu
)
674 if (!cpu_has_feature(CPU_FTR_L2CR
))
678 core99_l2_cache
= _get_L2CR();
679 printk("CPU0: L2CR is %lx\n", core99_l2_cache
);
681 printk("CPU%d: L2CR was %lx\n", cpu
, _get_L2CR());
683 _set_L2CR(core99_l2_cache
);
684 printk("CPU%d: L2CR set to %lx\n", cpu
, core99_l2_cache
);
687 if (!cpu_has_feature(CPU_FTR_L3CR
))
691 core99_l3_cache
= _get_L3CR();
692 printk("CPU0: L3CR is %lx\n", core99_l3_cache
);
694 printk("CPU%d: L3CR was %lx\n", cpu
, _get_L3CR());
696 _set_L3CR(core99_l3_cache
);
697 printk("CPU%d: L3CR set to %lx\n", cpu
, core99_l3_cache
);
699 #endif /* !CONFIG_PPC64 */
702 static void __init
smp_core99_setup(int ncpus
)
706 /* i2c based HW sync on some G5s */
707 if (of_machine_is_compatible("PowerMac7,2") ||
708 of_machine_is_compatible("PowerMac7,3") ||
709 of_machine_is_compatible("RackMac3,1"))
710 smp_core99_setup_i2c_hwsync(ncpus
);
712 /* pfunc based HW sync on recent G5s */
713 if (pmac_tb_freeze
== NULL
) {
714 struct device_node
*cpus
=
715 of_find_node_by_path("/cpus");
717 of_get_property(cpus
, "platform-cpu-timebase", NULL
)) {
718 pmac_tb_freeze
= smp_core99_pfunc_tb_freeze
;
719 printk(KERN_INFO
"Processor timebase sync using"
720 " platform function\n");
724 #else /* CONFIG_PPC64 */
726 /* GPIO based HW sync on ppc32 Core99 */
727 if (pmac_tb_freeze
== NULL
&& !of_machine_is_compatible("MacRISC4")) {
728 struct device_node
*cpu
;
729 const u32
*tbprop
= NULL
;
731 core99_tb_gpio
= KL_GPIO_TB_ENABLE
; /* default value */
732 cpu
= of_find_node_by_type(NULL
, "cpu");
734 tbprop
= of_get_property(cpu
, "timebase-enable", NULL
);
736 core99_tb_gpio
= *tbprop
;
739 pmac_tb_freeze
= smp_core99_gpio_tb_freeze
;
740 printk(KERN_INFO
"Processor timebase sync using"
741 " GPIO 0x%02x\n", core99_tb_gpio
);
744 #endif /* CONFIG_PPC64 */
746 /* No timebase sync, fallback to software */
747 if (pmac_tb_freeze
== NULL
) {
748 smp_ops
->give_timebase
= smp_generic_give_timebase
;
749 smp_ops
->take_timebase
= smp_generic_take_timebase
;
750 printk(KERN_INFO
"Processor timebase sync using software\n");
757 /* XXX should get this from reg properties */
758 for (i
= 1; i
< ncpus
; ++i
)
759 set_hard_smp_processor_id(i
, i
);
763 /* 32 bits SMP can't NAP */
764 if (!of_machine_is_compatible("MacRISC4"))
768 static void __init
smp_core99_probe(void)
770 struct device_node
*cpus
;
773 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_probe", 0x345);
775 /* Count CPUs in the device-tree */
776 for (cpus
= NULL
; (cpus
= of_find_node_by_type(cpus
, "cpu")) != NULL
;)
779 printk(KERN_INFO
"PowerMac SMP probe found %d cpus\n", ncpus
);
781 /* Nothing more to do if less than 2 of them */
785 /* We need to perform some early initialisations before we can start
786 * setting up SMP as we are running before initcalls
788 pmac_pfunc_base_install();
791 /* Setup various bits like timebase sync method, ability to nap, ... */
792 smp_core99_setup(ncpus
);
797 /* Collect l2cr and l3cr values from CPU 0 */
798 core99_init_caches(0);
801 static int smp_core99_kick_cpu(int nr
)
803 unsigned int save_vector
;
804 unsigned long target
, flags
;
805 unsigned int *vector
= (unsigned int *)(PAGE_OFFSET
+0x100);
807 if (nr
< 0 || nr
> 3)
811 ppc_md
.progress("smp_core99_kick_cpu", 0x346);
813 local_irq_save(flags
);
815 /* Save reset vector */
816 save_vector
= *vector
;
818 /* Setup fake reset vector that does
819 * b __secondary_start_pmac_0 + nr*8
821 target
= (unsigned long) __secondary_start_pmac_0
+ nr
* 8;
822 patch_branch(vector
, target
, BRANCH_SET_LINK
);
824 /* Put some life in our friend */
825 pmac_call_feature(PMAC_FTR_RESET_CPU
, NULL
, nr
, 0);
827 /* FIXME: We wait a bit for the CPU to take the exception, I should
828 * instead wait for the entry code to set something for me. Well,
829 * ideally, all that crap will be done in prom.c and the CPU left
830 * in a RAM-based wait loop like CHRP.
834 /* Restore our exception vector */
835 *vector
= save_vector
;
836 flush_icache_range((unsigned long) vector
, (unsigned long) vector
+ 4);
838 local_irq_restore(flags
);
839 if (ppc_md
.progress
) ppc_md
.progress("smp_core99_kick_cpu done", 0x347);
844 static void smp_core99_setup_cpu(int cpu_nr
)
848 core99_init_caches(cpu_nr
);
851 mpic_setup_this_cpu();
855 #ifdef CONFIG_HOTPLUG_CPU
856 static unsigned int smp_core99_host_open
;
858 static int smp_core99_cpu_prepare(unsigned int cpu
)
862 /* Open i2c bus if it was used for tb sync */
863 if (pmac_tb_clock_chip_host
&& !smp_core99_host_open
) {
864 rc
= pmac_i2c_open(pmac_tb_clock_chip_host
, 1);
866 pr_err("Failed to open i2c bus for time sync\n");
867 return notifier_from_errno(rc
);
869 smp_core99_host_open
= 1;
874 static int smp_core99_cpu_online(unsigned int cpu
)
876 /* Close i2c bus if it was used for tb sync */
877 if (pmac_tb_clock_chip_host
&& smp_core99_host_open
) {
878 pmac_i2c_close(pmac_tb_clock_chip_host
);
879 smp_core99_host_open
= 0;
883 #endif /* CONFIG_HOTPLUG_CPU */
885 static void __init
smp_core99_bringup_done(void)
887 extern void g5_phy_disable_cpu1(void);
889 /* Close i2c bus if it was used for tb sync */
890 if (pmac_tb_clock_chip_host
)
891 pmac_i2c_close(pmac_tb_clock_chip_host
);
893 /* If we didn't start the second CPU, we must take
896 if (of_machine_is_compatible("MacRISC4") &&
897 num_online_cpus() < 2) {
898 set_cpu_present(1, false);
899 g5_phy_disable_cpu1();
901 #ifdef CONFIG_HOTPLUG_CPU
902 cpuhp_setup_state_nocalls(CPUHP_POWERPC_PMAC_PREPARE
,
903 "powerpc/pmac:prepare", smp_core99_cpu_prepare
,
905 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN
, "powerpc/pmac:online",
906 smp_core99_cpu_online
, NULL
);
910 ppc_md
.progress("smp_core99_bringup_done", 0x349);
912 #endif /* CONFIG_PPC64 */
914 #ifdef CONFIG_HOTPLUG_CPU
916 static int smp_core99_cpu_disable(void)
918 int rc
= generic_cpu_disable();
922 mpic_cpu_set_priority(0xf);
929 static void pmac_cpu_die(void)
931 int cpu
= smp_processor_id();
935 pr_debug("CPU%d offline\n", cpu
);
936 generic_set_cpu_dead(cpu
);
942 #else /* CONFIG_PPC32 */
944 static void pmac_cpu_die(void)
946 int cpu
= smp_processor_id();
952 * turn off as much as possible, we'll be
953 * kicked out as this will only be invoked
954 * on core99 platforms for now ...
957 printk(KERN_INFO
"CPU#%d offline\n", cpu
);
958 generic_set_cpu_dead(cpu
);
962 * Re-enable interrupts. The NAP code needs to enable them
963 * anyways, do it now so we deal with the case where one already
964 * happened while soft-disabled.
965 * We shouldn't get any external interrupts, only decrementer, and the
966 * decrementer handler is safe for use on offline CPUs
971 /* let's not take timer interrupts too often ... */
979 #endif /* else CONFIG_PPC32 */
980 #endif /* CONFIG_HOTPLUG_CPU */
982 /* Core99 Macs (dual G4s and G5s) */
983 static struct smp_ops_t core99_smp_ops
= {
984 .message_pass
= smp_mpic_message_pass
,
985 .probe
= smp_core99_probe
,
987 .bringup_done
= smp_core99_bringup_done
,
989 .kick_cpu
= smp_core99_kick_cpu
,
990 .setup_cpu
= smp_core99_setup_cpu
,
991 .give_timebase
= smp_core99_give_timebase
,
992 .take_timebase
= smp_core99_take_timebase
,
993 #if defined(CONFIG_HOTPLUG_CPU)
994 .cpu_disable
= smp_core99_cpu_disable
,
995 .cpu_die
= generic_cpu_die
,
999 void __init
pmac_setup_smp(void)
1001 struct device_node
*np
;
1003 /* Check for Core99 */
1004 np
= of_find_node_by_name(NULL
, "uni-n");
1006 np
= of_find_node_by_name(NULL
, "u3");
1008 np
= of_find_node_by_name(NULL
, "u4");
1011 smp_ops
= &core99_smp_ops
;
1013 #ifdef CONFIG_PPC_PMAC32_PSURGE
1015 /* We have to set bits in cpu_possible_mask here since the
1016 * secondary CPU(s) aren't in the device tree. Various
1017 * things won't be initialized for CPUs not in the possible
1018 * map, so we really need to fix it up here.
1022 for (cpu
= 1; cpu
< 4 && cpu
< NR_CPUS
; ++cpu
)
1023 set_cpu_possible(cpu
, true);
1024 smp_ops
= &psurge_smp_ops
;
1026 #endif /* CONFIG_PPC_PMAC32_PSURGE */
1028 #ifdef CONFIG_HOTPLUG_CPU
1029 ppc_md
.cpu_die
= pmac_cpu_die
;