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[mirror_ubuntu-artful-kernel.git] / arch / powerpc / platforms / powernv / pci-ioda.c
1 /*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #undef DEBUG
13
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/msi.h>
24 #include <linux/memblock.h>
25 #include <linux/iommu.h>
26 #include <linux/rculist.h>
27 #include <linux/sizes.h>
28
29 #include <asm/sections.h>
30 #include <asm/io.h>
31 #include <asm/prom.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/machdep.h>
34 #include <asm/msi_bitmap.h>
35 #include <asm/ppc-pci.h>
36 #include <asm/opal.h>
37 #include <asm/iommu.h>
38 #include <asm/tce.h>
39 #include <asm/xics.h>
40 #include <asm/debugfs.h>
41 #include <asm/firmware.h>
42 #include <asm/pnv-pci.h>
43 #include <asm/mmzone.h>
44
45 #include <misc/cxl-base.h>
46
47 #include "powernv.h"
48 #include "pci.h"
49
50 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
51 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
53
54 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
55 #define POWERNV_IOMMU_MAX_LEVELS 5
56
57 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" };
58 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
59
60 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
61 const char *fmt, ...)
62 {
63 struct va_format vaf;
64 va_list args;
65 char pfix[32];
66
67 va_start(args, fmt);
68
69 vaf.fmt = fmt;
70 vaf.va = &args;
71
72 if (pe->flags & PNV_IODA_PE_DEV)
73 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
74 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
75 sprintf(pfix, "%04x:%02x ",
76 pci_domain_nr(pe->pbus), pe->pbus->number);
77 #ifdef CONFIG_PCI_IOV
78 else if (pe->flags & PNV_IODA_PE_VF)
79 sprintf(pfix, "%04x:%02x:%2x.%d",
80 pci_domain_nr(pe->parent_dev->bus),
81 (pe->rid & 0xff00) >> 8,
82 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
83 #endif /* CONFIG_PCI_IOV*/
84
85 printk("%spci %s: [PE# %.2x] %pV",
86 level, pfix, pe->pe_number, &vaf);
87
88 va_end(args);
89 }
90
91 static bool pnv_iommu_bypass_disabled __read_mostly;
92
93 static int __init iommu_setup(char *str)
94 {
95 if (!str)
96 return -EINVAL;
97
98 while (*str) {
99 if (!strncmp(str, "nobypass", 8)) {
100 pnv_iommu_bypass_disabled = true;
101 pr_info("PowerNV: IOMMU bypass window disabled.\n");
102 break;
103 }
104 str += strcspn(str, ",");
105 if (*str == ',')
106 str++;
107 }
108
109 return 0;
110 }
111 early_param("iommu", iommu_setup);
112
113 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
114 {
115 /*
116 * WARNING: We cannot rely on the resource flags. The Linux PCI
117 * allocation code sometimes decides to put a 64-bit prefetchable
118 * BAR in the 32-bit window, so we have to compare the addresses.
119 *
120 * For simplicity we only test resource start.
121 */
122 return (r->start >= phb->ioda.m64_base &&
123 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
124 }
125
126 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
127 {
128 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
129
130 return (resource_flags & flags) == flags;
131 }
132
133 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
134 {
135 s64 rc;
136
137 phb->ioda.pe_array[pe_no].phb = phb;
138 phb->ioda.pe_array[pe_no].pe_number = pe_no;
139
140 /*
141 * Clear the PE frozen state as it might be put into frozen state
142 * in the last PCI remove path. It's not harmful to do so when the
143 * PE is already in unfrozen state.
144 */
145 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
146 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
147 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
148 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
149 __func__, rc, phb->hose->global_number, pe_no);
150
151 return &phb->ioda.pe_array[pe_no];
152 }
153
154 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
155 {
156 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
157 pr_warn("%s: Invalid PE %x on PHB#%x\n",
158 __func__, pe_no, phb->hose->global_number);
159 return;
160 }
161
162 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
163 pr_debug("%s: PE %x was reserved on PHB#%x\n",
164 __func__, pe_no, phb->hose->global_number);
165
166 pnv_ioda_init_pe(phb, pe_no);
167 }
168
169 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
170 {
171 long pe;
172
173 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
174 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
175 return pnv_ioda_init_pe(phb, pe);
176 }
177
178 return NULL;
179 }
180
181 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
182 {
183 struct pnv_phb *phb = pe->phb;
184 unsigned int pe_num = pe->pe_number;
185
186 WARN_ON(pe->pdev);
187
188 memset(pe, 0, sizeof(struct pnv_ioda_pe));
189 clear_bit(pe_num, phb->ioda.pe_alloc);
190 }
191
192 /* The default M64 BAR is shared by all PEs */
193 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
194 {
195 const char *desc;
196 struct resource *r;
197 s64 rc;
198
199 /* Configure the default M64 BAR */
200 rc = opal_pci_set_phb_mem_window(phb->opal_id,
201 OPAL_M64_WINDOW_TYPE,
202 phb->ioda.m64_bar_idx,
203 phb->ioda.m64_base,
204 0, /* unused */
205 phb->ioda.m64_size);
206 if (rc != OPAL_SUCCESS) {
207 desc = "configuring";
208 goto fail;
209 }
210
211 /* Enable the default M64 BAR */
212 rc = opal_pci_phb_mmio_enable(phb->opal_id,
213 OPAL_M64_WINDOW_TYPE,
214 phb->ioda.m64_bar_idx,
215 OPAL_ENABLE_M64_SPLIT);
216 if (rc != OPAL_SUCCESS) {
217 desc = "enabling";
218 goto fail;
219 }
220
221 /*
222 * Exclude the segments for reserved and root bus PE, which
223 * are first or last two PEs.
224 */
225 r = &phb->hose->mem_resources[1];
226 if (phb->ioda.reserved_pe_idx == 0)
227 r->start += (2 * phb->ioda.m64_segsize);
228 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
229 r->end -= (2 * phb->ioda.m64_segsize);
230 else
231 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
232 phb->ioda.reserved_pe_idx);
233
234 return 0;
235
236 fail:
237 pr_warn(" Failure %lld %s M64 BAR#%d\n",
238 rc, desc, phb->ioda.m64_bar_idx);
239 opal_pci_phb_mmio_enable(phb->opal_id,
240 OPAL_M64_WINDOW_TYPE,
241 phb->ioda.m64_bar_idx,
242 OPAL_DISABLE_M64);
243 return -EIO;
244 }
245
246 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
247 unsigned long *pe_bitmap)
248 {
249 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
250 struct pnv_phb *phb = hose->private_data;
251 struct resource *r;
252 resource_size_t base, sgsz, start, end;
253 int segno, i;
254
255 base = phb->ioda.m64_base;
256 sgsz = phb->ioda.m64_segsize;
257 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
258 r = &pdev->resource[i];
259 if (!r->parent || !pnv_pci_is_m64(phb, r))
260 continue;
261
262 start = _ALIGN_DOWN(r->start - base, sgsz);
263 end = _ALIGN_UP(r->end - base, sgsz);
264 for (segno = start / sgsz; segno < end / sgsz; segno++) {
265 if (pe_bitmap)
266 set_bit(segno, pe_bitmap);
267 else
268 pnv_ioda_reserve_pe(phb, segno);
269 }
270 }
271 }
272
273 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
274 {
275 struct resource *r;
276 int index;
277
278 /*
279 * There are 16 M64 BARs, each of which has 8 segments. So
280 * there are as many M64 segments as the maximum number of
281 * PEs, which is 128.
282 */
283 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
284 unsigned long base, segsz = phb->ioda.m64_segsize;
285 int64_t rc;
286
287 base = phb->ioda.m64_base +
288 index * PNV_IODA1_M64_SEGS * segsz;
289 rc = opal_pci_set_phb_mem_window(phb->opal_id,
290 OPAL_M64_WINDOW_TYPE, index, base, 0,
291 PNV_IODA1_M64_SEGS * segsz);
292 if (rc != OPAL_SUCCESS) {
293 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
294 rc, phb->hose->global_number, index);
295 goto fail;
296 }
297
298 rc = opal_pci_phb_mmio_enable(phb->opal_id,
299 OPAL_M64_WINDOW_TYPE, index,
300 OPAL_ENABLE_M64_SPLIT);
301 if (rc != OPAL_SUCCESS) {
302 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
303 rc, phb->hose->global_number, index);
304 goto fail;
305 }
306 }
307
308 /*
309 * Exclude the segments for reserved and root bus PE, which
310 * are first or last two PEs.
311 */
312 r = &phb->hose->mem_resources[1];
313 if (phb->ioda.reserved_pe_idx == 0)
314 r->start += (2 * phb->ioda.m64_segsize);
315 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
316 r->end -= (2 * phb->ioda.m64_segsize);
317 else
318 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
319 phb->ioda.reserved_pe_idx, phb->hose->global_number);
320
321 return 0;
322
323 fail:
324 for ( ; index >= 0; index--)
325 opal_pci_phb_mmio_enable(phb->opal_id,
326 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
327
328 return -EIO;
329 }
330
331 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
332 unsigned long *pe_bitmap,
333 bool all)
334 {
335 struct pci_dev *pdev;
336
337 list_for_each_entry(pdev, &bus->devices, bus_list) {
338 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
339
340 if (all && pdev->subordinate)
341 pnv_ioda_reserve_m64_pe(pdev->subordinate,
342 pe_bitmap, all);
343 }
344 }
345
346 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
347 {
348 struct pci_controller *hose = pci_bus_to_host(bus);
349 struct pnv_phb *phb = hose->private_data;
350 struct pnv_ioda_pe *master_pe, *pe;
351 unsigned long size, *pe_alloc;
352 int i;
353
354 /* Root bus shouldn't use M64 */
355 if (pci_is_root_bus(bus))
356 return NULL;
357
358 /* Allocate bitmap */
359 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
360 pe_alloc = kzalloc(size, GFP_KERNEL);
361 if (!pe_alloc) {
362 pr_warn("%s: Out of memory !\n",
363 __func__);
364 return NULL;
365 }
366
367 /* Figure out reserved PE numbers by the PE */
368 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
369
370 /*
371 * the current bus might not own M64 window and that's all
372 * contributed by its child buses. For the case, we needn't
373 * pick M64 dependent PE#.
374 */
375 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
376 kfree(pe_alloc);
377 return NULL;
378 }
379
380 /*
381 * Figure out the master PE and put all slave PEs to master
382 * PE's list to form compound PE.
383 */
384 master_pe = NULL;
385 i = -1;
386 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
387 phb->ioda.total_pe_num) {
388 pe = &phb->ioda.pe_array[i];
389
390 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
391 if (!master_pe) {
392 pe->flags |= PNV_IODA_PE_MASTER;
393 INIT_LIST_HEAD(&pe->slaves);
394 master_pe = pe;
395 } else {
396 pe->flags |= PNV_IODA_PE_SLAVE;
397 pe->master = master_pe;
398 list_add_tail(&pe->list, &master_pe->slaves);
399 }
400
401 /*
402 * P7IOC supports M64DT, which helps mapping M64 segment
403 * to one particular PE#. However, PHB3 has fixed mapping
404 * between M64 segment and PE#. In order to have same logic
405 * for P7IOC and PHB3, we enforce fixed mapping between M64
406 * segment and PE# on P7IOC.
407 */
408 if (phb->type == PNV_PHB_IODA1) {
409 int64_t rc;
410
411 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
412 pe->pe_number, OPAL_M64_WINDOW_TYPE,
413 pe->pe_number / PNV_IODA1_M64_SEGS,
414 pe->pe_number % PNV_IODA1_M64_SEGS);
415 if (rc != OPAL_SUCCESS)
416 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
417 __func__, rc, phb->hose->global_number,
418 pe->pe_number);
419 }
420 }
421
422 kfree(pe_alloc);
423 return master_pe;
424 }
425
426 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
427 {
428 struct pci_controller *hose = phb->hose;
429 struct device_node *dn = hose->dn;
430 struct resource *res;
431 u32 m64_range[2], i;
432 const __be32 *r;
433 u64 pci_addr;
434
435 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
436 pr_info(" Not support M64 window\n");
437 return;
438 }
439
440 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
441 pr_info(" Firmware too old to support M64 window\n");
442 return;
443 }
444
445 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
446 if (!r) {
447 pr_info(" No <ibm,opal-m64-window> on %s\n",
448 dn->full_name);
449 return;
450 }
451
452 /*
453 * Find the available M64 BAR range and pickup the last one for
454 * covering the whole 64-bits space. We support only one range.
455 */
456 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
457 m64_range, 2)) {
458 /* In absence of the property, assume 0..15 */
459 m64_range[0] = 0;
460 m64_range[1] = 16;
461 }
462 /* We only support 64 bits in our allocator */
463 if (m64_range[1] > 63) {
464 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
465 __func__, m64_range[1], phb->hose->global_number);
466 m64_range[1] = 63;
467 }
468 /* Empty range, no m64 */
469 if (m64_range[1] <= m64_range[0]) {
470 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
471 __func__, phb->hose->global_number);
472 return;
473 }
474
475 /* Configure M64 informations */
476 res = &hose->mem_resources[1];
477 res->name = dn->full_name;
478 res->start = of_translate_address(dn, r + 2);
479 res->end = res->start + of_read_number(r + 4, 2) - 1;
480 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
481 pci_addr = of_read_number(r, 2);
482 hose->mem_offset[1] = res->start - pci_addr;
483
484 phb->ioda.m64_size = resource_size(res);
485 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
486 phb->ioda.m64_base = pci_addr;
487
488 /* This lines up nicely with the display from processing OF ranges */
489 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
490 res->start, res->end, pci_addr, m64_range[0],
491 m64_range[0] + m64_range[1] - 1);
492
493 /* Mark all M64 used up by default */
494 phb->ioda.m64_bar_alloc = (unsigned long)-1;
495
496 /* Use last M64 BAR to cover M64 window */
497 m64_range[1]--;
498 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
499
500 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
501
502 /* Mark remaining ones free */
503 for (i = m64_range[0]; i < m64_range[1]; i++)
504 clear_bit(i, &phb->ioda.m64_bar_alloc);
505
506 /*
507 * Setup init functions for M64 based on IODA version, IODA3 uses
508 * the IODA2 code.
509 */
510 if (phb->type == PNV_PHB_IODA1)
511 phb->init_m64 = pnv_ioda1_init_m64;
512 else
513 phb->init_m64 = pnv_ioda2_init_m64;
514 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
515 phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
516 }
517
518 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
519 {
520 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
521 struct pnv_ioda_pe *slave;
522 s64 rc;
523
524 /* Fetch master PE */
525 if (pe->flags & PNV_IODA_PE_SLAVE) {
526 pe = pe->master;
527 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
528 return;
529
530 pe_no = pe->pe_number;
531 }
532
533 /* Freeze master PE */
534 rc = opal_pci_eeh_freeze_set(phb->opal_id,
535 pe_no,
536 OPAL_EEH_ACTION_SET_FREEZE_ALL);
537 if (rc != OPAL_SUCCESS) {
538 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
539 __func__, rc, phb->hose->global_number, pe_no);
540 return;
541 }
542
543 /* Freeze slave PEs */
544 if (!(pe->flags & PNV_IODA_PE_MASTER))
545 return;
546
547 list_for_each_entry(slave, &pe->slaves, list) {
548 rc = opal_pci_eeh_freeze_set(phb->opal_id,
549 slave->pe_number,
550 OPAL_EEH_ACTION_SET_FREEZE_ALL);
551 if (rc != OPAL_SUCCESS)
552 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
553 __func__, rc, phb->hose->global_number,
554 slave->pe_number);
555 }
556 }
557
558 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
559 {
560 struct pnv_ioda_pe *pe, *slave;
561 s64 rc;
562
563 /* Find master PE */
564 pe = &phb->ioda.pe_array[pe_no];
565 if (pe->flags & PNV_IODA_PE_SLAVE) {
566 pe = pe->master;
567 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
568 pe_no = pe->pe_number;
569 }
570
571 /* Clear frozen state for master PE */
572 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
573 if (rc != OPAL_SUCCESS) {
574 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
575 __func__, rc, opt, phb->hose->global_number, pe_no);
576 return -EIO;
577 }
578
579 if (!(pe->flags & PNV_IODA_PE_MASTER))
580 return 0;
581
582 /* Clear frozen state for slave PEs */
583 list_for_each_entry(slave, &pe->slaves, list) {
584 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
585 slave->pe_number,
586 opt);
587 if (rc != OPAL_SUCCESS) {
588 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
589 __func__, rc, opt, phb->hose->global_number,
590 slave->pe_number);
591 return -EIO;
592 }
593 }
594
595 return 0;
596 }
597
598 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
599 {
600 struct pnv_ioda_pe *slave, *pe;
601 u8 fstate, state;
602 __be16 pcierr;
603 s64 rc;
604
605 /* Sanity check on PE number */
606 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
607 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
608
609 /*
610 * Fetch the master PE and the PE instance might be
611 * not initialized yet.
612 */
613 pe = &phb->ioda.pe_array[pe_no];
614 if (pe->flags & PNV_IODA_PE_SLAVE) {
615 pe = pe->master;
616 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
617 pe_no = pe->pe_number;
618 }
619
620 /* Check the master PE */
621 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
622 &state, &pcierr, NULL);
623 if (rc != OPAL_SUCCESS) {
624 pr_warn("%s: Failure %lld getting "
625 "PHB#%x-PE#%x state\n",
626 __func__, rc,
627 phb->hose->global_number, pe_no);
628 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
629 }
630
631 /* Check the slave PE */
632 if (!(pe->flags & PNV_IODA_PE_MASTER))
633 return state;
634
635 list_for_each_entry(slave, &pe->slaves, list) {
636 rc = opal_pci_eeh_freeze_status(phb->opal_id,
637 slave->pe_number,
638 &fstate,
639 &pcierr,
640 NULL);
641 if (rc != OPAL_SUCCESS) {
642 pr_warn("%s: Failure %lld getting "
643 "PHB#%x-PE#%x state\n",
644 __func__, rc,
645 phb->hose->global_number, slave->pe_number);
646 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
647 }
648
649 /*
650 * Override the result based on the ascending
651 * priority.
652 */
653 if (fstate > state)
654 state = fstate;
655 }
656
657 return state;
658 }
659
660 /* Currently those 2 are only used when MSIs are enabled, this will change
661 * but in the meantime, we need to protect them to avoid warnings
662 */
663 #ifdef CONFIG_PCI_MSI
664 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
665 {
666 struct pci_controller *hose = pci_bus_to_host(dev->bus);
667 struct pnv_phb *phb = hose->private_data;
668 struct pci_dn *pdn = pci_get_pdn(dev);
669
670 if (!pdn)
671 return NULL;
672 if (pdn->pe_number == IODA_INVALID_PE)
673 return NULL;
674 return &phb->ioda.pe_array[pdn->pe_number];
675 }
676 #endif /* CONFIG_PCI_MSI */
677
678 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
679 struct pnv_ioda_pe *parent,
680 struct pnv_ioda_pe *child,
681 bool is_add)
682 {
683 const char *desc = is_add ? "adding" : "removing";
684 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
685 OPAL_REMOVE_PE_FROM_DOMAIN;
686 struct pnv_ioda_pe *slave;
687 long rc;
688
689 /* Parent PE affects child PE */
690 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
691 child->pe_number, op);
692 if (rc != OPAL_SUCCESS) {
693 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
694 rc, desc);
695 return -ENXIO;
696 }
697
698 if (!(child->flags & PNV_IODA_PE_MASTER))
699 return 0;
700
701 /* Compound case: parent PE affects slave PEs */
702 list_for_each_entry(slave, &child->slaves, list) {
703 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
704 slave->pe_number, op);
705 if (rc != OPAL_SUCCESS) {
706 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
707 rc, desc);
708 return -ENXIO;
709 }
710 }
711
712 return 0;
713 }
714
715 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
716 struct pnv_ioda_pe *pe,
717 bool is_add)
718 {
719 struct pnv_ioda_pe *slave;
720 struct pci_dev *pdev = NULL;
721 int ret;
722
723 /*
724 * Clear PE frozen state. If it's master PE, we need
725 * clear slave PE frozen state as well.
726 */
727 if (is_add) {
728 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
729 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
730 if (pe->flags & PNV_IODA_PE_MASTER) {
731 list_for_each_entry(slave, &pe->slaves, list)
732 opal_pci_eeh_freeze_clear(phb->opal_id,
733 slave->pe_number,
734 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
735 }
736 }
737
738 /*
739 * Associate PE in PELT. We need add the PE into the
740 * corresponding PELT-V as well. Otherwise, the error
741 * originated from the PE might contribute to other
742 * PEs.
743 */
744 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
745 if (ret)
746 return ret;
747
748 /* For compound PEs, any one affects all of them */
749 if (pe->flags & PNV_IODA_PE_MASTER) {
750 list_for_each_entry(slave, &pe->slaves, list) {
751 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
752 if (ret)
753 return ret;
754 }
755 }
756
757 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
758 pdev = pe->pbus->self;
759 else if (pe->flags & PNV_IODA_PE_DEV)
760 pdev = pe->pdev->bus->self;
761 #ifdef CONFIG_PCI_IOV
762 else if (pe->flags & PNV_IODA_PE_VF)
763 pdev = pe->parent_dev;
764 #endif /* CONFIG_PCI_IOV */
765 while (pdev) {
766 struct pci_dn *pdn = pci_get_pdn(pdev);
767 struct pnv_ioda_pe *parent;
768
769 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
770 parent = &phb->ioda.pe_array[pdn->pe_number];
771 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
772 if (ret)
773 return ret;
774 }
775
776 pdev = pdev->bus->self;
777 }
778
779 return 0;
780 }
781
782 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
783 {
784 struct pci_dev *parent;
785 uint8_t bcomp, dcomp, fcomp;
786 int64_t rc;
787 long rid_end, rid;
788
789 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
790 if (pe->pbus) {
791 int count;
792
793 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
794 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
795 parent = pe->pbus->self;
796 if (pe->flags & PNV_IODA_PE_BUS_ALL)
797 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
798 else
799 count = 1;
800
801 switch(count) {
802 case 1: bcomp = OpalPciBusAll; break;
803 case 2: bcomp = OpalPciBus7Bits; break;
804 case 4: bcomp = OpalPciBus6Bits; break;
805 case 8: bcomp = OpalPciBus5Bits; break;
806 case 16: bcomp = OpalPciBus4Bits; break;
807 case 32: bcomp = OpalPciBus3Bits; break;
808 default:
809 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
810 count);
811 /* Do an exact match only */
812 bcomp = OpalPciBusAll;
813 }
814 rid_end = pe->rid + (count << 8);
815 } else {
816 #ifdef CONFIG_PCI_IOV
817 if (pe->flags & PNV_IODA_PE_VF)
818 parent = pe->parent_dev;
819 else
820 #endif
821 parent = pe->pdev->bus->self;
822 bcomp = OpalPciBusAll;
823 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
824 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
825 rid_end = pe->rid + 1;
826 }
827
828 /* Clear the reverse map */
829 for (rid = pe->rid; rid < rid_end; rid++)
830 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
831
832 /* Release from all parents PELT-V */
833 while (parent) {
834 struct pci_dn *pdn = pci_get_pdn(parent);
835 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
836 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
837 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
838 /* XXX What to do in case of error ? */
839 }
840 parent = parent->bus->self;
841 }
842
843 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
844 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
845
846 /* Disassociate PE in PELT */
847 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
848 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
849 if (rc)
850 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
851 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
852 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
853 if (rc)
854 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
855
856 pe->pbus = NULL;
857 pe->pdev = NULL;
858 #ifdef CONFIG_PCI_IOV
859 pe->parent_dev = NULL;
860 #endif
861
862 return 0;
863 }
864
865 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
866 {
867 struct pci_dev *parent;
868 uint8_t bcomp, dcomp, fcomp;
869 long rc, rid_end, rid;
870
871 /* Bus validation ? */
872 if (pe->pbus) {
873 int count;
874
875 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
876 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
877 parent = pe->pbus->self;
878 if (pe->flags & PNV_IODA_PE_BUS_ALL)
879 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
880 else
881 count = 1;
882
883 switch(count) {
884 case 1: bcomp = OpalPciBusAll; break;
885 case 2: bcomp = OpalPciBus7Bits; break;
886 case 4: bcomp = OpalPciBus6Bits; break;
887 case 8: bcomp = OpalPciBus5Bits; break;
888 case 16: bcomp = OpalPciBus4Bits; break;
889 case 32: bcomp = OpalPciBus3Bits; break;
890 default:
891 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
892 count);
893 /* Do an exact match only */
894 bcomp = OpalPciBusAll;
895 }
896 rid_end = pe->rid + (count << 8);
897 } else {
898 #ifdef CONFIG_PCI_IOV
899 if (pe->flags & PNV_IODA_PE_VF)
900 parent = pe->parent_dev;
901 else
902 #endif /* CONFIG_PCI_IOV */
903 parent = pe->pdev->bus->self;
904 bcomp = OpalPciBusAll;
905 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
906 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
907 rid_end = pe->rid + 1;
908 }
909
910 /*
911 * Associate PE in PELT. We need add the PE into the
912 * corresponding PELT-V as well. Otherwise, the error
913 * originated from the PE might contribute to other
914 * PEs.
915 */
916 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
917 bcomp, dcomp, fcomp, OPAL_MAP_PE);
918 if (rc) {
919 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
920 return -ENXIO;
921 }
922
923 /*
924 * Configure PELTV. NPUs don't have a PELTV table so skip
925 * configuration on them.
926 */
927 if (phb->type != PNV_PHB_NPU)
928 pnv_ioda_set_peltv(phb, pe, true);
929
930 /* Setup reverse map */
931 for (rid = pe->rid; rid < rid_end; rid++)
932 phb->ioda.pe_rmap[rid] = pe->pe_number;
933
934 /* Setup one MVTs on IODA1 */
935 if (phb->type != PNV_PHB_IODA1) {
936 pe->mve_number = 0;
937 goto out;
938 }
939
940 pe->mve_number = pe->pe_number;
941 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
942 if (rc != OPAL_SUCCESS) {
943 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
944 rc, pe->mve_number);
945 pe->mve_number = -1;
946 } else {
947 rc = opal_pci_set_mve_enable(phb->opal_id,
948 pe->mve_number, OPAL_ENABLE_MVE);
949 if (rc) {
950 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
951 rc, pe->mve_number);
952 pe->mve_number = -1;
953 }
954 }
955
956 out:
957 return 0;
958 }
959
960 #ifdef CONFIG_PCI_IOV
961 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
962 {
963 struct pci_dn *pdn = pci_get_pdn(dev);
964 int i;
965 struct resource *res, res2;
966 resource_size_t size;
967 u16 num_vfs;
968
969 if (!dev->is_physfn)
970 return -EINVAL;
971
972 /*
973 * "offset" is in VFs. The M64 windows are sized so that when they
974 * are segmented, each segment is the same size as the IOV BAR.
975 * Each segment is in a separate PE, and the high order bits of the
976 * address are the PE number. Therefore, each VF's BAR is in a
977 * separate PE, and changing the IOV BAR start address changes the
978 * range of PEs the VFs are in.
979 */
980 num_vfs = pdn->num_vfs;
981 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
982 res = &dev->resource[i + PCI_IOV_RESOURCES];
983 if (!res->flags || !res->parent)
984 continue;
985
986 /*
987 * The actual IOV BAR range is determined by the start address
988 * and the actual size for num_vfs VFs BAR. This check is to
989 * make sure that after shifting, the range will not overlap
990 * with another device.
991 */
992 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
993 res2.flags = res->flags;
994 res2.start = res->start + (size * offset);
995 res2.end = res2.start + (size * num_vfs) - 1;
996
997 if (res2.end > res->end) {
998 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
999 i, &res2, res, num_vfs, offset);
1000 return -EBUSY;
1001 }
1002 }
1003
1004 /*
1005 * After doing so, there would be a "hole" in the /proc/iomem when
1006 * offset is a positive value. It looks like the device return some
1007 * mmio back to the system, which actually no one could use it.
1008 */
1009 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1010 res = &dev->resource[i + PCI_IOV_RESOURCES];
1011 if (!res->flags || !res->parent)
1012 continue;
1013
1014 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1015 res2 = *res;
1016 res->start += size * offset;
1017
1018 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1019 i, &res2, res, (offset > 0) ? "En" : "Dis",
1020 num_vfs, offset);
1021 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1022 }
1023 return 0;
1024 }
1025 #endif /* CONFIG_PCI_IOV */
1026
1027 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1028 {
1029 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1030 struct pnv_phb *phb = hose->private_data;
1031 struct pci_dn *pdn = pci_get_pdn(dev);
1032 struct pnv_ioda_pe *pe;
1033
1034 if (!pdn) {
1035 pr_err("%s: Device tree node not associated properly\n",
1036 pci_name(dev));
1037 return NULL;
1038 }
1039 if (pdn->pe_number != IODA_INVALID_PE)
1040 return NULL;
1041
1042 pe = pnv_ioda_alloc_pe(phb);
1043 if (!pe) {
1044 pr_warning("%s: Not enough PE# available, disabling device\n",
1045 pci_name(dev));
1046 return NULL;
1047 }
1048
1049 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1050 * pointer in the PE data structure, both should be destroyed at the
1051 * same time. However, this needs to be looked at more closely again
1052 * once we actually start removing things (Hotplug, SR-IOV, ...)
1053 *
1054 * At some point we want to remove the PDN completely anyways
1055 */
1056 pci_dev_get(dev);
1057 pdn->pcidev = dev;
1058 pdn->pe_number = pe->pe_number;
1059 pe->flags = PNV_IODA_PE_DEV;
1060 pe->pdev = dev;
1061 pe->pbus = NULL;
1062 pe->mve_number = -1;
1063 pe->rid = dev->bus->number << 8 | pdn->devfn;
1064
1065 pe_info(pe, "Associated device to PE\n");
1066
1067 if (pnv_ioda_configure_pe(phb, pe)) {
1068 /* XXX What do we do here ? */
1069 pnv_ioda_free_pe(pe);
1070 pdn->pe_number = IODA_INVALID_PE;
1071 pe->pdev = NULL;
1072 pci_dev_put(dev);
1073 return NULL;
1074 }
1075
1076 /* Put PE to the list */
1077 list_add_tail(&pe->list, &phb->ioda.pe_list);
1078
1079 return pe;
1080 }
1081
1082 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1083 {
1084 struct pci_dev *dev;
1085
1086 list_for_each_entry(dev, &bus->devices, bus_list) {
1087 struct pci_dn *pdn = pci_get_pdn(dev);
1088
1089 if (pdn == NULL) {
1090 pr_warn("%s: No device node associated with device !\n",
1091 pci_name(dev));
1092 continue;
1093 }
1094
1095 /*
1096 * In partial hotplug case, the PCI device might be still
1097 * associated with the PE and needn't attach it to the PE
1098 * again.
1099 */
1100 if (pdn->pe_number != IODA_INVALID_PE)
1101 continue;
1102
1103 pe->device_count++;
1104 pdn->pcidev = dev;
1105 pdn->pe_number = pe->pe_number;
1106 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1107 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1108 }
1109 }
1110
1111 /*
1112 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1113 * single PCI bus. Another one that contains the primary PCI bus and its
1114 * subordinate PCI devices and buses. The second type of PE is normally
1115 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1116 */
1117 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1118 {
1119 struct pci_controller *hose = pci_bus_to_host(bus);
1120 struct pnv_phb *phb = hose->private_data;
1121 struct pnv_ioda_pe *pe = NULL;
1122 unsigned int pe_num;
1123
1124 /*
1125 * In partial hotplug case, the PE instance might be still alive.
1126 * We should reuse it instead of allocating a new one.
1127 */
1128 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1129 if (pe_num != IODA_INVALID_PE) {
1130 pe = &phb->ioda.pe_array[pe_num];
1131 pnv_ioda_setup_same_PE(bus, pe);
1132 return NULL;
1133 }
1134
1135 /* PE number for root bus should have been reserved */
1136 if (pci_is_root_bus(bus) &&
1137 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1138 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1139
1140 /* Check if PE is determined by M64 */
1141 if (!pe && phb->pick_m64_pe)
1142 pe = phb->pick_m64_pe(bus, all);
1143
1144 /* The PE number isn't pinned by M64 */
1145 if (!pe)
1146 pe = pnv_ioda_alloc_pe(phb);
1147
1148 if (!pe) {
1149 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1150 __func__, pci_domain_nr(bus), bus->number);
1151 return NULL;
1152 }
1153
1154 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1155 pe->pbus = bus;
1156 pe->pdev = NULL;
1157 pe->mve_number = -1;
1158 pe->rid = bus->busn_res.start << 8;
1159
1160 if (all)
1161 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1162 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1163 else
1164 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1165 bus->busn_res.start, pe->pe_number);
1166
1167 if (pnv_ioda_configure_pe(phb, pe)) {
1168 /* XXX What do we do here ? */
1169 pnv_ioda_free_pe(pe);
1170 pe->pbus = NULL;
1171 return NULL;
1172 }
1173
1174 /* Associate it with all child devices */
1175 pnv_ioda_setup_same_PE(bus, pe);
1176
1177 /* Put PE to the list */
1178 list_add_tail(&pe->list, &phb->ioda.pe_list);
1179
1180 return pe;
1181 }
1182
1183 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1184 {
1185 int pe_num, found_pe = false, rc;
1186 long rid;
1187 struct pnv_ioda_pe *pe;
1188 struct pci_dev *gpu_pdev;
1189 struct pci_dn *npu_pdn;
1190 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1191 struct pnv_phb *phb = hose->private_data;
1192
1193 /*
1194 * Due to a hardware errata PE#0 on the NPU is reserved for
1195 * error handling. This means we only have three PEs remaining
1196 * which need to be assigned to four links, implying some
1197 * links must share PEs.
1198 *
1199 * To achieve this we assign PEs such that NPUs linking the
1200 * same GPU get assigned the same PE.
1201 */
1202 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1203 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1204 pe = &phb->ioda.pe_array[pe_num];
1205 if (!pe->pdev)
1206 continue;
1207
1208 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1209 /*
1210 * This device has the same peer GPU so should
1211 * be assigned the same PE as the existing
1212 * peer NPU.
1213 */
1214 dev_info(&npu_pdev->dev,
1215 "Associating to existing PE %x\n", pe_num);
1216 pci_dev_get(npu_pdev);
1217 npu_pdn = pci_get_pdn(npu_pdev);
1218 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1219 npu_pdn->pcidev = npu_pdev;
1220 npu_pdn->pe_number = pe_num;
1221 phb->ioda.pe_rmap[rid] = pe->pe_number;
1222
1223 /* Map the PE to this link */
1224 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1225 OpalPciBusAll,
1226 OPAL_COMPARE_RID_DEVICE_NUMBER,
1227 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1228 OPAL_MAP_PE);
1229 WARN_ON(rc != OPAL_SUCCESS);
1230 found_pe = true;
1231 break;
1232 }
1233 }
1234
1235 if (!found_pe)
1236 /*
1237 * Could not find an existing PE so allocate a new
1238 * one.
1239 */
1240 return pnv_ioda_setup_dev_PE(npu_pdev);
1241 else
1242 return pe;
1243 }
1244
1245 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1246 {
1247 struct pci_dev *pdev;
1248
1249 list_for_each_entry(pdev, &bus->devices, bus_list)
1250 pnv_ioda_setup_npu_PE(pdev);
1251 }
1252
1253 static void pnv_pci_ioda_setup_PEs(void)
1254 {
1255 struct pci_controller *hose, *tmp;
1256 struct pnv_phb *phb;
1257
1258 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1259 phb = hose->private_data;
1260 if (phb->type == PNV_PHB_NPU) {
1261 /* PE#0 is needed for error reporting */
1262 pnv_ioda_reserve_pe(phb, 0);
1263 pnv_ioda_setup_npu_PEs(hose->bus);
1264 if (phb->model == PNV_PHB_MODEL_NPU2)
1265 pnv_npu2_init(phb);
1266 }
1267 }
1268 }
1269
1270 #ifdef CONFIG_PCI_IOV
1271 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1272 {
1273 struct pci_bus *bus;
1274 struct pci_controller *hose;
1275 struct pnv_phb *phb;
1276 struct pci_dn *pdn;
1277 int i, j;
1278 int m64_bars;
1279
1280 bus = pdev->bus;
1281 hose = pci_bus_to_host(bus);
1282 phb = hose->private_data;
1283 pdn = pci_get_pdn(pdev);
1284
1285 if (pdn->m64_single_mode)
1286 m64_bars = num_vfs;
1287 else
1288 m64_bars = 1;
1289
1290 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1291 for (j = 0; j < m64_bars; j++) {
1292 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1293 continue;
1294 opal_pci_phb_mmio_enable(phb->opal_id,
1295 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1296 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1297 pdn->m64_map[j][i] = IODA_INVALID_M64;
1298 }
1299
1300 kfree(pdn->m64_map);
1301 return 0;
1302 }
1303
1304 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1305 {
1306 struct pci_bus *bus;
1307 struct pci_controller *hose;
1308 struct pnv_phb *phb;
1309 struct pci_dn *pdn;
1310 unsigned int win;
1311 struct resource *res;
1312 int i, j;
1313 int64_t rc;
1314 int total_vfs;
1315 resource_size_t size, start;
1316 int pe_num;
1317 int m64_bars;
1318
1319 bus = pdev->bus;
1320 hose = pci_bus_to_host(bus);
1321 phb = hose->private_data;
1322 pdn = pci_get_pdn(pdev);
1323 total_vfs = pci_sriov_get_totalvfs(pdev);
1324
1325 if (pdn->m64_single_mode)
1326 m64_bars = num_vfs;
1327 else
1328 m64_bars = 1;
1329
1330 pdn->m64_map = kmalloc_array(m64_bars,
1331 sizeof(*pdn->m64_map),
1332 GFP_KERNEL);
1333 if (!pdn->m64_map)
1334 return -ENOMEM;
1335 /* Initialize the m64_map to IODA_INVALID_M64 */
1336 for (i = 0; i < m64_bars ; i++)
1337 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1338 pdn->m64_map[i][j] = IODA_INVALID_M64;
1339
1340
1341 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1342 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1343 if (!res->flags || !res->parent)
1344 continue;
1345
1346 for (j = 0; j < m64_bars; j++) {
1347 do {
1348 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1349 phb->ioda.m64_bar_idx + 1, 0);
1350
1351 if (win >= phb->ioda.m64_bar_idx + 1)
1352 goto m64_failed;
1353 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1354
1355 pdn->m64_map[j][i] = win;
1356
1357 if (pdn->m64_single_mode) {
1358 size = pci_iov_resource_size(pdev,
1359 PCI_IOV_RESOURCES + i);
1360 start = res->start + size * j;
1361 } else {
1362 size = resource_size(res);
1363 start = res->start;
1364 }
1365
1366 /* Map the M64 here */
1367 if (pdn->m64_single_mode) {
1368 pe_num = pdn->pe_num_map[j];
1369 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1370 pe_num, OPAL_M64_WINDOW_TYPE,
1371 pdn->m64_map[j][i], 0);
1372 }
1373
1374 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1375 OPAL_M64_WINDOW_TYPE,
1376 pdn->m64_map[j][i],
1377 start,
1378 0, /* unused */
1379 size);
1380
1381
1382 if (rc != OPAL_SUCCESS) {
1383 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1384 win, rc);
1385 goto m64_failed;
1386 }
1387
1388 if (pdn->m64_single_mode)
1389 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1390 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1391 else
1392 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1393 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1394
1395 if (rc != OPAL_SUCCESS) {
1396 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1397 win, rc);
1398 goto m64_failed;
1399 }
1400 }
1401 }
1402 return 0;
1403
1404 m64_failed:
1405 pnv_pci_vf_release_m64(pdev, num_vfs);
1406 return -EBUSY;
1407 }
1408
1409 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1410 int num);
1411 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
1412
1413 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1414 {
1415 struct iommu_table *tbl;
1416 int64_t rc;
1417
1418 tbl = pe->table_group.tables[0];
1419 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1420 if (rc)
1421 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1422
1423 pnv_pci_ioda2_set_bypass(pe, false);
1424 if (pe->table_group.group) {
1425 iommu_group_put(pe->table_group.group);
1426 BUG_ON(pe->table_group.group);
1427 }
1428 iommu_tce_table_put(tbl);
1429 }
1430
1431 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1432 {
1433 struct pci_bus *bus;
1434 struct pci_controller *hose;
1435 struct pnv_phb *phb;
1436 struct pnv_ioda_pe *pe, *pe_n;
1437 struct pci_dn *pdn;
1438
1439 bus = pdev->bus;
1440 hose = pci_bus_to_host(bus);
1441 phb = hose->private_data;
1442 pdn = pci_get_pdn(pdev);
1443
1444 if (!pdev->is_physfn)
1445 return;
1446
1447 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1448 if (pe->parent_dev != pdev)
1449 continue;
1450
1451 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1452
1453 /* Remove from list */
1454 mutex_lock(&phb->ioda.pe_list_mutex);
1455 list_del(&pe->list);
1456 mutex_unlock(&phb->ioda.pe_list_mutex);
1457
1458 pnv_ioda_deconfigure_pe(phb, pe);
1459
1460 pnv_ioda_free_pe(pe);
1461 }
1462 }
1463
1464 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1465 {
1466 struct pci_bus *bus;
1467 struct pci_controller *hose;
1468 struct pnv_phb *phb;
1469 struct pnv_ioda_pe *pe;
1470 struct pci_dn *pdn;
1471 u16 num_vfs, i;
1472
1473 bus = pdev->bus;
1474 hose = pci_bus_to_host(bus);
1475 phb = hose->private_data;
1476 pdn = pci_get_pdn(pdev);
1477 num_vfs = pdn->num_vfs;
1478
1479 /* Release VF PEs */
1480 pnv_ioda_release_vf_PE(pdev);
1481
1482 if (phb->type == PNV_PHB_IODA2) {
1483 if (!pdn->m64_single_mode)
1484 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1485
1486 /* Release M64 windows */
1487 pnv_pci_vf_release_m64(pdev, num_vfs);
1488
1489 /* Release PE numbers */
1490 if (pdn->m64_single_mode) {
1491 for (i = 0; i < num_vfs; i++) {
1492 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1493 continue;
1494
1495 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1496 pnv_ioda_free_pe(pe);
1497 }
1498 } else
1499 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1500 /* Releasing pe_num_map */
1501 kfree(pdn->pe_num_map);
1502 }
1503 }
1504
1505 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1506 struct pnv_ioda_pe *pe);
1507 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1508 {
1509 struct pci_bus *bus;
1510 struct pci_controller *hose;
1511 struct pnv_phb *phb;
1512 struct pnv_ioda_pe *pe;
1513 int pe_num;
1514 u16 vf_index;
1515 struct pci_dn *pdn;
1516
1517 bus = pdev->bus;
1518 hose = pci_bus_to_host(bus);
1519 phb = hose->private_data;
1520 pdn = pci_get_pdn(pdev);
1521
1522 if (!pdev->is_physfn)
1523 return;
1524
1525 /* Reserve PE for each VF */
1526 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1527 if (pdn->m64_single_mode)
1528 pe_num = pdn->pe_num_map[vf_index];
1529 else
1530 pe_num = *pdn->pe_num_map + vf_index;
1531
1532 pe = &phb->ioda.pe_array[pe_num];
1533 pe->pe_number = pe_num;
1534 pe->phb = phb;
1535 pe->flags = PNV_IODA_PE_VF;
1536 pe->pbus = NULL;
1537 pe->parent_dev = pdev;
1538 pe->mve_number = -1;
1539 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1540 pci_iov_virtfn_devfn(pdev, vf_index);
1541
1542 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1543 hose->global_number, pdev->bus->number,
1544 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1545 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1546
1547 if (pnv_ioda_configure_pe(phb, pe)) {
1548 /* XXX What do we do here ? */
1549 pnv_ioda_free_pe(pe);
1550 pe->pdev = NULL;
1551 continue;
1552 }
1553
1554 /* Put PE to the list */
1555 mutex_lock(&phb->ioda.pe_list_mutex);
1556 list_add_tail(&pe->list, &phb->ioda.pe_list);
1557 mutex_unlock(&phb->ioda.pe_list_mutex);
1558
1559 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1560 }
1561 }
1562
1563 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1564 {
1565 struct pci_bus *bus;
1566 struct pci_controller *hose;
1567 struct pnv_phb *phb;
1568 struct pnv_ioda_pe *pe;
1569 struct pci_dn *pdn;
1570 int ret;
1571 u16 i;
1572
1573 bus = pdev->bus;
1574 hose = pci_bus_to_host(bus);
1575 phb = hose->private_data;
1576 pdn = pci_get_pdn(pdev);
1577
1578 if (phb->type == PNV_PHB_IODA2) {
1579 if (!pdn->vfs_expanded) {
1580 dev_info(&pdev->dev, "don't support this SRIOV device"
1581 " with non 64bit-prefetchable IOV BAR\n");
1582 return -ENOSPC;
1583 }
1584
1585 /*
1586 * When M64 BARs functions in Single PE mode, the number of VFs
1587 * could be enabled must be less than the number of M64 BARs.
1588 */
1589 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1590 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1591 return -EBUSY;
1592 }
1593
1594 /* Allocating pe_num_map */
1595 if (pdn->m64_single_mode)
1596 pdn->pe_num_map = kmalloc_array(num_vfs,
1597 sizeof(*pdn->pe_num_map),
1598 GFP_KERNEL);
1599 else
1600 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1601
1602 if (!pdn->pe_num_map)
1603 return -ENOMEM;
1604
1605 if (pdn->m64_single_mode)
1606 for (i = 0; i < num_vfs; i++)
1607 pdn->pe_num_map[i] = IODA_INVALID_PE;
1608
1609 /* Calculate available PE for required VFs */
1610 if (pdn->m64_single_mode) {
1611 for (i = 0; i < num_vfs; i++) {
1612 pe = pnv_ioda_alloc_pe(phb);
1613 if (!pe) {
1614 ret = -EBUSY;
1615 goto m64_failed;
1616 }
1617
1618 pdn->pe_num_map[i] = pe->pe_number;
1619 }
1620 } else {
1621 mutex_lock(&phb->ioda.pe_alloc_mutex);
1622 *pdn->pe_num_map = bitmap_find_next_zero_area(
1623 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1624 0, num_vfs, 0);
1625 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1626 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1627 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1628 kfree(pdn->pe_num_map);
1629 return -EBUSY;
1630 }
1631 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1632 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1633 }
1634 pdn->num_vfs = num_vfs;
1635
1636 /* Assign M64 window accordingly */
1637 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1638 if (ret) {
1639 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1640 goto m64_failed;
1641 }
1642
1643 /*
1644 * When using one M64 BAR to map one IOV BAR, we need to shift
1645 * the IOV BAR according to the PE# allocated to the VFs.
1646 * Otherwise, the PE# for the VF will conflict with others.
1647 */
1648 if (!pdn->m64_single_mode) {
1649 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1650 if (ret)
1651 goto m64_failed;
1652 }
1653 }
1654
1655 /* Setup VF PEs */
1656 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1657
1658 return 0;
1659
1660 m64_failed:
1661 if (pdn->m64_single_mode) {
1662 for (i = 0; i < num_vfs; i++) {
1663 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1664 continue;
1665
1666 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1667 pnv_ioda_free_pe(pe);
1668 }
1669 } else
1670 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1671
1672 /* Releasing pe_num_map */
1673 kfree(pdn->pe_num_map);
1674
1675 return ret;
1676 }
1677
1678 int pcibios_sriov_disable(struct pci_dev *pdev)
1679 {
1680 pnv_pci_sriov_disable(pdev);
1681
1682 /* Release PCI data */
1683 remove_dev_pci_data(pdev);
1684 return 0;
1685 }
1686
1687 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1688 {
1689 /* Allocate PCI data */
1690 add_dev_pci_data(pdev);
1691
1692 return pnv_pci_sriov_enable(pdev, num_vfs);
1693 }
1694 #endif /* CONFIG_PCI_IOV */
1695
1696 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1697 {
1698 struct pci_dn *pdn = pci_get_pdn(pdev);
1699 struct pnv_ioda_pe *pe;
1700
1701 /*
1702 * The function can be called while the PE#
1703 * hasn't been assigned. Do nothing for the
1704 * case.
1705 */
1706 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1707 return;
1708
1709 pe = &phb->ioda.pe_array[pdn->pe_number];
1710 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1711 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1712 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1713 /*
1714 * Note: iommu_add_device() will fail here as
1715 * for physical PE: the device is already added by now;
1716 * for virtual PE: sysfs entries are not ready yet and
1717 * tce_iommu_bus_notifier will add the device to a group later.
1718 */
1719 }
1720
1721 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe)
1722 {
1723 unsigned short vendor = 0;
1724 struct pci_dev *pdev;
1725
1726 if (pe->device_count == 1)
1727 return true;
1728
1729 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1730 if (!pe->pbus)
1731 return true;
1732
1733 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
1734 if (!vendor) {
1735 vendor = pdev->vendor;
1736 continue;
1737 }
1738
1739 if (pdev->vendor != vendor)
1740 return false;
1741 }
1742
1743 return true;
1744 }
1745
1746 /*
1747 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1748 *
1749 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1750 * Devices can only access more than that if bit 59 of the PCI address is set
1751 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1752 * Many PCI devices are not capable of addressing that many bits, and as a
1753 * result are limited to the 4GB of virtual memory made available to 32-bit
1754 * devices in TVE#0.
1755 *
1756 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1757 * devices by configuring the virtual memory past the first 4GB inaccessible
1758 * by 64-bit DMAs. This should only be used by devices that want more than
1759 * 4GB, and only on PEs that have no 32-bit devices.
1760 *
1761 * Currently this will only work on PHB3 (POWER8).
1762 */
1763 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1764 {
1765 u64 window_size, table_size, tce_count, addr;
1766 struct page *table_pages;
1767 u64 tce_order = 28; /* 256MB TCEs */
1768 __be64 *tces;
1769 s64 rc;
1770
1771 /*
1772 * Window size needs to be a power of two, but needs to account for
1773 * shifting memory by the 4GB offset required to skip 32bit space.
1774 */
1775 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1776 tce_count = window_size >> tce_order;
1777 table_size = tce_count << 3;
1778
1779 if (table_size < PAGE_SIZE)
1780 table_size = PAGE_SIZE;
1781
1782 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1783 get_order(table_size));
1784 if (!table_pages)
1785 goto err;
1786
1787 tces = page_address(table_pages);
1788 if (!tces)
1789 goto err;
1790
1791 memset(tces, 0, table_size);
1792
1793 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1794 tces[(addr + (1ULL << 32)) >> tce_order] =
1795 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1796 }
1797
1798 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1799 pe->pe_number,
1800 /* reconfigure window 0 */
1801 (pe->pe_number << 1) + 0,
1802 1,
1803 __pa(tces),
1804 table_size,
1805 1 << tce_order);
1806 if (rc == OPAL_SUCCESS) {
1807 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1808 return 0;
1809 }
1810 err:
1811 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1812 return -EIO;
1813 }
1814
1815 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1816 {
1817 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1818 struct pnv_phb *phb = hose->private_data;
1819 struct pci_dn *pdn = pci_get_pdn(pdev);
1820 struct pnv_ioda_pe *pe;
1821 uint64_t top;
1822 bool bypass = false;
1823 s64 rc;
1824
1825 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1826 return -ENODEV;;
1827
1828 pe = &phb->ioda.pe_array[pdn->pe_number];
1829 if (pe->tce_bypass_enabled) {
1830 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1831 bypass = (dma_mask >= top);
1832 }
1833
1834 if (bypass) {
1835 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1836 set_dma_ops(&pdev->dev, &dma_direct_ops);
1837 } else {
1838 /*
1839 * If the device can't set the TCE bypass bit but still wants
1840 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1841 * bypass the 32-bit region and be usable for 64-bit DMAs.
1842 * The device needs to be able to address all of this space.
1843 */
1844 if (dma_mask >> 32 &&
1845 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1846 pnv_pci_ioda_pe_single_vendor(pe) &&
1847 phb->model == PNV_PHB_MODEL_PHB3) {
1848 /* Configure the bypass mode */
1849 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1850 if (rc)
1851 return rc;
1852 /* 4GB offset bypasses 32-bit space */
1853 set_dma_offset(&pdev->dev, (1ULL << 32));
1854 set_dma_ops(&pdev->dev, &dma_direct_ops);
1855 } else {
1856 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1857 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1858 }
1859 }
1860 *pdev->dev.dma_mask = dma_mask;
1861
1862 /* Update peer npu devices */
1863 pnv_npu_try_dma_set_bypass(pdev, bypass);
1864
1865 return 0;
1866 }
1867
1868 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1869 {
1870 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1871 struct pnv_phb *phb = hose->private_data;
1872 struct pci_dn *pdn = pci_get_pdn(pdev);
1873 struct pnv_ioda_pe *pe;
1874 u64 end, mask;
1875
1876 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1877 return 0;
1878
1879 pe = &phb->ioda.pe_array[pdn->pe_number];
1880 if (!pe->tce_bypass_enabled)
1881 return __dma_get_required_mask(&pdev->dev);
1882
1883
1884 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1885 mask = 1ULL << (fls64(end) - 1);
1886 mask += mask - 1;
1887
1888 return mask;
1889 }
1890
1891 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1892 struct pci_bus *bus,
1893 bool add_to_group)
1894 {
1895 struct pci_dev *dev;
1896
1897 list_for_each_entry(dev, &bus->devices, bus_list) {
1898 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1899 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1900 if (add_to_group)
1901 iommu_add_device(&dev->dev);
1902
1903 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1904 pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1905 add_to_group);
1906 }
1907 }
1908
1909 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1910 bool real_mode)
1911 {
1912 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1913 (phb->regs + 0x210);
1914 }
1915
1916 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1917 unsigned long index, unsigned long npages, bool rm)
1918 {
1919 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1920 &tbl->it_group_list, struct iommu_table_group_link,
1921 next);
1922 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1923 struct pnv_ioda_pe, table_group);
1924 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1925 unsigned long start, end, inc;
1926
1927 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1928 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1929 npages - 1);
1930
1931 /* p7ioc-style invalidation, 2 TCEs per write */
1932 start |= (1ull << 63);
1933 end |= (1ull << 63);
1934 inc = 16;
1935 end |= inc - 1; /* round up end to be different than start */
1936
1937 mb(); /* Ensure above stores are visible */
1938 while (start <= end) {
1939 if (rm)
1940 __raw_rm_writeq(cpu_to_be64(start), invalidate);
1941 else
1942 __raw_writeq(cpu_to_be64(start), invalidate);
1943 start += inc;
1944 }
1945
1946 /*
1947 * The iommu layer will do another mb() for us on build()
1948 * and we don't care on free()
1949 */
1950 }
1951
1952 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1953 long npages, unsigned long uaddr,
1954 enum dma_data_direction direction,
1955 unsigned long attrs)
1956 {
1957 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1958 attrs);
1959
1960 if (!ret)
1961 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1962
1963 return ret;
1964 }
1965
1966 #ifdef CONFIG_IOMMU_API
1967 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1968 unsigned long *hpa, enum dma_data_direction *direction)
1969 {
1970 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1971
1972 if (!ret)
1973 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1974
1975 return ret;
1976 }
1977
1978 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
1979 unsigned long *hpa, enum dma_data_direction *direction)
1980 {
1981 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
1982
1983 if (!ret)
1984 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
1985
1986 return ret;
1987 }
1988 #endif
1989
1990 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1991 long npages)
1992 {
1993 pnv_tce_free(tbl, index, npages);
1994
1995 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1996 }
1997
1998 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1999 .set = pnv_ioda1_tce_build,
2000 #ifdef CONFIG_IOMMU_API
2001 .exchange = pnv_ioda1_tce_xchg,
2002 .exchange_rm = pnv_ioda1_tce_xchg_rm,
2003 #endif
2004 .clear = pnv_ioda1_tce_free,
2005 .get = pnv_tce_get,
2006 };
2007
2008 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
2009 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
2010 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
2011
2012 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2013 {
2014 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2015 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2016
2017 mb(); /* Ensure previous TCE table stores are visible */
2018 if (rm)
2019 __raw_rm_writeq(cpu_to_be64(val), invalidate);
2020 else
2021 __raw_writeq(cpu_to_be64(val), invalidate);
2022 }
2023
2024 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2025 {
2026 /* 01xb - invalidate TCEs that match the specified PE# */
2027 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2028 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2029
2030 mb(); /* Ensure above stores are visible */
2031 __raw_writeq(cpu_to_be64(val), invalidate);
2032 }
2033
2034 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2035 unsigned shift, unsigned long index,
2036 unsigned long npages)
2037 {
2038 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2039 unsigned long start, end, inc;
2040
2041 /* We'll invalidate DMA address in PE scope */
2042 start = PHB3_TCE_KILL_INVAL_ONE;
2043 start |= (pe->pe_number & 0xFF);
2044 end = start;
2045
2046 /* Figure out the start, end and step */
2047 start |= (index << shift);
2048 end |= ((index + npages - 1) << shift);
2049 inc = (0x1ull << shift);
2050 mb();
2051
2052 while (start <= end) {
2053 if (rm)
2054 __raw_rm_writeq(cpu_to_be64(start), invalidate);
2055 else
2056 __raw_writeq(cpu_to_be64(start), invalidate);
2057 start += inc;
2058 }
2059 }
2060
2061 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2062 {
2063 struct pnv_phb *phb = pe->phb;
2064
2065 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2066 pnv_pci_phb3_tce_invalidate_pe(pe);
2067 else
2068 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2069 pe->pe_number, 0, 0, 0);
2070 }
2071
2072 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2073 unsigned long index, unsigned long npages, bool rm)
2074 {
2075 struct iommu_table_group_link *tgl;
2076
2077 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2078 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2079 struct pnv_ioda_pe, table_group);
2080 struct pnv_phb *phb = pe->phb;
2081 unsigned int shift = tbl->it_page_shift;
2082
2083 /*
2084 * NVLink1 can use the TCE kill register directly as
2085 * it's the same as PHB3. NVLink2 is different and
2086 * should go via the OPAL call.
2087 */
2088 if (phb->model == PNV_PHB_MODEL_NPU) {
2089 /*
2090 * The NVLink hardware does not support TCE kill
2091 * per TCE entry so we have to invalidate
2092 * the entire cache for it.
2093 */
2094 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2095 continue;
2096 }
2097 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2098 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2099 index, npages);
2100 else
2101 opal_pci_tce_kill(phb->opal_id,
2102 OPAL_PCI_TCE_KILL_PAGES,
2103 pe->pe_number, 1u << shift,
2104 index << shift, npages);
2105 }
2106 }
2107
2108 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2109 {
2110 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2111 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2112 else
2113 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2114 }
2115
2116 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2117 long npages, unsigned long uaddr,
2118 enum dma_data_direction direction,
2119 unsigned long attrs)
2120 {
2121 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2122 attrs);
2123
2124 if (!ret)
2125 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2126
2127 return ret;
2128 }
2129
2130 #ifdef CONFIG_IOMMU_API
2131 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2132 unsigned long *hpa, enum dma_data_direction *direction)
2133 {
2134 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2135
2136 if (!ret)
2137 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2138
2139 return ret;
2140 }
2141
2142 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2143 unsigned long *hpa, enum dma_data_direction *direction)
2144 {
2145 long ret = pnv_tce_xchg(tbl, index, hpa, direction);
2146
2147 if (!ret)
2148 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2149
2150 return ret;
2151 }
2152 #endif
2153
2154 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2155 long npages)
2156 {
2157 pnv_tce_free(tbl, index, npages);
2158
2159 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2160 }
2161
2162 static void pnv_ioda2_table_free(struct iommu_table *tbl)
2163 {
2164 pnv_pci_ioda2_table_free_pages(tbl);
2165 }
2166
2167 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2168 .set = pnv_ioda2_tce_build,
2169 #ifdef CONFIG_IOMMU_API
2170 .exchange = pnv_ioda2_tce_xchg,
2171 .exchange_rm = pnv_ioda2_tce_xchg_rm,
2172 #endif
2173 .clear = pnv_ioda2_tce_free,
2174 .get = pnv_tce_get,
2175 .free = pnv_ioda2_table_free,
2176 };
2177
2178 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2179 {
2180 unsigned int *weight = (unsigned int *)data;
2181
2182 /* This is quite simplistic. The "base" weight of a device
2183 * is 10. 0 means no DMA is to be accounted for it.
2184 */
2185 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2186 return 0;
2187
2188 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2189 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2190 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2191 *weight += 3;
2192 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2193 *weight += 15;
2194 else
2195 *weight += 10;
2196
2197 return 0;
2198 }
2199
2200 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2201 {
2202 unsigned int weight = 0;
2203
2204 /* SRIOV VF has same DMA32 weight as its PF */
2205 #ifdef CONFIG_PCI_IOV
2206 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2207 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2208 return weight;
2209 }
2210 #endif
2211
2212 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2213 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2214 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2215 struct pci_dev *pdev;
2216
2217 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2218 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2219 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2220 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2221 }
2222
2223 return weight;
2224 }
2225
2226 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2227 struct pnv_ioda_pe *pe)
2228 {
2229
2230 struct page *tce_mem = NULL;
2231 struct iommu_table *tbl;
2232 unsigned int weight, total_weight = 0;
2233 unsigned int tce32_segsz, base, segs, avail, i;
2234 int64_t rc;
2235 void *addr;
2236
2237 /* XXX FIXME: Handle 64-bit only DMA devices */
2238 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2239 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2240 weight = pnv_pci_ioda_pe_dma_weight(pe);
2241 if (!weight)
2242 return;
2243
2244 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2245 &total_weight);
2246 segs = (weight * phb->ioda.dma32_count) / total_weight;
2247 if (!segs)
2248 segs = 1;
2249
2250 /*
2251 * Allocate contiguous DMA32 segments. We begin with the expected
2252 * number of segments. With one more attempt, the number of DMA32
2253 * segments to be allocated is decreased by one until one segment
2254 * is allocated successfully.
2255 */
2256 do {
2257 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2258 for (avail = 0, i = base; i < base + segs; i++) {
2259 if (phb->ioda.dma32_segmap[i] ==
2260 IODA_INVALID_PE)
2261 avail++;
2262 }
2263
2264 if (avail == segs)
2265 goto found;
2266 }
2267 } while (--segs);
2268
2269 if (!segs) {
2270 pe_warn(pe, "No available DMA32 segments\n");
2271 return;
2272 }
2273
2274 found:
2275 tbl = pnv_pci_table_alloc(phb->hose->node);
2276 if (WARN_ON(!tbl))
2277 return;
2278
2279 iommu_register_group(&pe->table_group, phb->hose->global_number,
2280 pe->pe_number);
2281 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2282
2283 /* Grab a 32-bit TCE table */
2284 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2285 weight, total_weight, base, segs);
2286 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2287 base * PNV_IODA1_DMA32_SEGSIZE,
2288 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2289
2290 /* XXX Currently, we allocate one big contiguous table for the
2291 * TCEs. We only really need one chunk per 256M of TCE space
2292 * (ie per segment) but that's an optimization for later, it
2293 * requires some added smarts with our get/put_tce implementation
2294 *
2295 * Each TCE page is 4KB in size and each TCE entry occupies 8
2296 * bytes
2297 */
2298 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2299 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2300 get_order(tce32_segsz * segs));
2301 if (!tce_mem) {
2302 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2303 goto fail;
2304 }
2305 addr = page_address(tce_mem);
2306 memset(addr, 0, tce32_segsz * segs);
2307
2308 /* Configure HW */
2309 for (i = 0; i < segs; i++) {
2310 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2311 pe->pe_number,
2312 base + i, 1,
2313 __pa(addr) + tce32_segsz * i,
2314 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2315 if (rc) {
2316 pe_err(pe, " Failed to configure 32-bit TCE table,"
2317 " err %ld\n", rc);
2318 goto fail;
2319 }
2320 }
2321
2322 /* Setup DMA32 segment mapping */
2323 for (i = base; i < base + segs; i++)
2324 phb->ioda.dma32_segmap[i] = pe->pe_number;
2325
2326 /* Setup linux iommu table */
2327 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2328 base * PNV_IODA1_DMA32_SEGSIZE,
2329 IOMMU_PAGE_SHIFT_4K);
2330
2331 tbl->it_ops = &pnv_ioda1_iommu_ops;
2332 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2333 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2334 iommu_init_table(tbl, phb->hose->node);
2335
2336 if (pe->flags & PNV_IODA_PE_DEV) {
2337 /*
2338 * Setting table base here only for carrying iommu_group
2339 * further down to let iommu_add_device() do the job.
2340 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2341 */
2342 set_iommu_table_base(&pe->pdev->dev, tbl);
2343 iommu_add_device(&pe->pdev->dev);
2344 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2345 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2346
2347 return;
2348 fail:
2349 /* XXX Failure: Try to fallback to 64-bit only ? */
2350 if (tce_mem)
2351 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2352 if (tbl) {
2353 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2354 iommu_tce_table_put(tbl);
2355 }
2356 }
2357
2358 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2359 int num, struct iommu_table *tbl)
2360 {
2361 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2362 table_group);
2363 struct pnv_phb *phb = pe->phb;
2364 int64_t rc;
2365 const unsigned long size = tbl->it_indirect_levels ?
2366 tbl->it_level_size : tbl->it_size;
2367 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2368 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2369
2370 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2371 start_addr, start_addr + win_size - 1,
2372 IOMMU_PAGE_SIZE(tbl));
2373
2374 /*
2375 * Map TCE table through TVT. The TVE index is the PE number
2376 * shifted by 1 bit for 32-bits DMA space.
2377 */
2378 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2379 pe->pe_number,
2380 (pe->pe_number << 1) + num,
2381 tbl->it_indirect_levels + 1,
2382 __pa(tbl->it_base),
2383 size << 3,
2384 IOMMU_PAGE_SIZE(tbl));
2385 if (rc) {
2386 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2387 return rc;
2388 }
2389
2390 pnv_pci_link_table_and_group(phb->hose->node, num,
2391 tbl, &pe->table_group);
2392 pnv_pci_ioda2_tce_invalidate_pe(pe);
2393
2394 return 0;
2395 }
2396
2397 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2398 {
2399 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2400 int64_t rc;
2401
2402 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2403 if (enable) {
2404 phys_addr_t top = memblock_end_of_DRAM();
2405
2406 top = roundup_pow_of_two(top);
2407 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2408 pe->pe_number,
2409 window_id,
2410 pe->tce_bypass_base,
2411 top);
2412 } else {
2413 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2414 pe->pe_number,
2415 window_id,
2416 pe->tce_bypass_base,
2417 0);
2418 }
2419 if (rc)
2420 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2421 else
2422 pe->tce_bypass_enabled = enable;
2423 }
2424
2425 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2426 __u32 page_shift, __u64 window_size, __u32 levels,
2427 struct iommu_table *tbl);
2428
2429 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2430 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2431 struct iommu_table **ptbl)
2432 {
2433 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2434 table_group);
2435 int nid = pe->phb->hose->node;
2436 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2437 long ret;
2438 struct iommu_table *tbl;
2439
2440 tbl = pnv_pci_table_alloc(nid);
2441 if (!tbl)
2442 return -ENOMEM;
2443
2444 tbl->it_ops = &pnv_ioda2_iommu_ops;
2445
2446 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2447 bus_offset, page_shift, window_size,
2448 levels, tbl);
2449 if (ret) {
2450 iommu_tce_table_put(tbl);
2451 return ret;
2452 }
2453
2454 *ptbl = tbl;
2455
2456 return 0;
2457 }
2458
2459 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2460 {
2461 struct iommu_table *tbl = NULL;
2462 long rc;
2463
2464 /*
2465 * crashkernel= specifies the kdump kernel's maximum memory at
2466 * some offset and there is no guaranteed the result is a power
2467 * of 2, which will cause errors later.
2468 */
2469 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2470
2471 /*
2472 * In memory constrained environments, e.g. kdump kernel, the
2473 * DMA window can be larger than available memory, which will
2474 * cause errors later.
2475 */
2476 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2477
2478 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2479 IOMMU_PAGE_SHIFT_4K,
2480 window_size,
2481 POWERNV_IOMMU_DEFAULT_LEVELS, &tbl);
2482 if (rc) {
2483 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2484 rc);
2485 return rc;
2486 }
2487
2488 iommu_init_table(tbl, pe->phb->hose->node);
2489
2490 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2491 if (rc) {
2492 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2493 rc);
2494 iommu_tce_table_put(tbl);
2495 return rc;
2496 }
2497
2498 if (!pnv_iommu_bypass_disabled)
2499 pnv_pci_ioda2_set_bypass(pe, true);
2500
2501 /*
2502 * Setting table base here only for carrying iommu_group
2503 * further down to let iommu_add_device() do the job.
2504 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2505 */
2506 if (pe->flags & PNV_IODA_PE_DEV)
2507 set_iommu_table_base(&pe->pdev->dev, tbl);
2508
2509 return 0;
2510 }
2511
2512 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2513 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2514 int num)
2515 {
2516 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2517 table_group);
2518 struct pnv_phb *phb = pe->phb;
2519 long ret;
2520
2521 pe_info(pe, "Removing DMA window #%d\n", num);
2522
2523 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2524 (pe->pe_number << 1) + num,
2525 0/* levels */, 0/* table address */,
2526 0/* table size */, 0/* page size */);
2527 if (ret)
2528 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2529 else
2530 pnv_pci_ioda2_tce_invalidate_pe(pe);
2531
2532 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2533
2534 return ret;
2535 }
2536 #endif
2537
2538 #ifdef CONFIG_IOMMU_API
2539 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2540 __u64 window_size, __u32 levels)
2541 {
2542 unsigned long bytes = 0;
2543 const unsigned window_shift = ilog2(window_size);
2544 unsigned entries_shift = window_shift - page_shift;
2545 unsigned table_shift = entries_shift + 3;
2546 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2547 unsigned long direct_table_size;
2548
2549 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2550 (window_size > memory_hotplug_max()) ||
2551 !is_power_of_2(window_size))
2552 return 0;
2553
2554 /* Calculate a direct table size from window_size and levels */
2555 entries_shift = (entries_shift + levels - 1) / levels;
2556 table_shift = entries_shift + 3;
2557 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2558 direct_table_size = 1UL << table_shift;
2559
2560 for ( ; levels; --levels) {
2561 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2562
2563 tce_table_size /= direct_table_size;
2564 tce_table_size <<= 3;
2565 tce_table_size = max_t(unsigned long,
2566 tce_table_size, direct_table_size);
2567 }
2568
2569 return bytes;
2570 }
2571
2572 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2573 {
2574 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2575 table_group);
2576 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2577 struct iommu_table *tbl = pe->table_group.tables[0];
2578
2579 pnv_pci_ioda2_set_bypass(pe, false);
2580 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2581 if (pe->pbus)
2582 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2583 iommu_tce_table_put(tbl);
2584 }
2585
2586 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2587 {
2588 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2589 table_group);
2590
2591 pnv_pci_ioda2_setup_default_config(pe);
2592 if (pe->pbus)
2593 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2594 }
2595
2596 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2597 .get_table_size = pnv_pci_ioda2_get_table_size,
2598 .create_table = pnv_pci_ioda2_create_table,
2599 .set_window = pnv_pci_ioda2_set_window,
2600 .unset_window = pnv_pci_ioda2_unset_window,
2601 .take_ownership = pnv_ioda2_take_ownership,
2602 .release_ownership = pnv_ioda2_release_ownership,
2603 };
2604
2605 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2606 {
2607 struct pci_controller *hose;
2608 struct pnv_phb *phb;
2609 struct pnv_ioda_pe **ptmppe = opaque;
2610 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2611 struct pci_dn *pdn = pci_get_pdn(pdev);
2612
2613 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2614 return 0;
2615
2616 hose = pci_bus_to_host(pdev->bus);
2617 phb = hose->private_data;
2618 if (phb->type != PNV_PHB_NPU)
2619 return 0;
2620
2621 *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2622
2623 return 1;
2624 }
2625
2626 /*
2627 * This returns PE of associated NPU.
2628 * This assumes that NPU is in the same IOMMU group with GPU and there is
2629 * no other PEs.
2630 */
2631 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2632 struct iommu_table_group *table_group)
2633 {
2634 struct pnv_ioda_pe *npe = NULL;
2635 int ret = iommu_group_for_each_dev(table_group->group, &npe,
2636 gpe_table_group_to_npe_cb);
2637
2638 BUG_ON(!ret || !npe);
2639
2640 return npe;
2641 }
2642
2643 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2644 int num, struct iommu_table *tbl)
2645 {
2646 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2647
2648 if (ret)
2649 return ret;
2650
2651 ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl);
2652 if (ret)
2653 pnv_pci_ioda2_unset_window(table_group, num);
2654
2655 return ret;
2656 }
2657
2658 static long pnv_pci_ioda2_npu_unset_window(
2659 struct iommu_table_group *table_group,
2660 int num)
2661 {
2662 long ret = pnv_pci_ioda2_unset_window(table_group, num);
2663
2664 if (ret)
2665 return ret;
2666
2667 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num);
2668 }
2669
2670 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2671 {
2672 /*
2673 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2674 * the iommu_table if 32bit DMA is enabled.
2675 */
2676 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2677 pnv_ioda2_take_ownership(table_group);
2678 }
2679
2680 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2681 .get_table_size = pnv_pci_ioda2_get_table_size,
2682 .create_table = pnv_pci_ioda2_create_table,
2683 .set_window = pnv_pci_ioda2_npu_set_window,
2684 .unset_window = pnv_pci_ioda2_npu_unset_window,
2685 .take_ownership = pnv_ioda2_npu_take_ownership,
2686 .release_ownership = pnv_ioda2_release_ownership,
2687 };
2688
2689 static void pnv_pci_ioda_setup_iommu_api(void)
2690 {
2691 struct pci_controller *hose, *tmp;
2692 struct pnv_phb *phb;
2693 struct pnv_ioda_pe *pe, *gpe;
2694
2695 /*
2696 * Now we have all PHBs discovered, time to add NPU devices to
2697 * the corresponding IOMMU groups.
2698 */
2699 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2700 phb = hose->private_data;
2701
2702 if (phb->type != PNV_PHB_NPU)
2703 continue;
2704
2705 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2706 gpe = pnv_pci_npu_setup_iommu(pe);
2707 if (gpe)
2708 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2709 }
2710 }
2711 }
2712 #else /* !CONFIG_IOMMU_API */
2713 static void pnv_pci_ioda_setup_iommu_api(void) { };
2714 #endif
2715
2716 static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift,
2717 unsigned levels, unsigned long limit,
2718 unsigned long *current_offset, unsigned long *total_allocated)
2719 {
2720 struct page *tce_mem = NULL;
2721 __be64 *addr, *tmp;
2722 unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
2723 unsigned long allocated = 1UL << (order + PAGE_SHIFT);
2724 unsigned entries = 1UL << (shift - 3);
2725 long i;
2726
2727 tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
2728 if (!tce_mem) {
2729 pr_err("Failed to allocate a TCE memory, order=%d\n", order);
2730 return NULL;
2731 }
2732 addr = page_address(tce_mem);
2733 memset(addr, 0, allocated);
2734 *total_allocated += allocated;
2735
2736 --levels;
2737 if (!levels) {
2738 *current_offset += allocated;
2739 return addr;
2740 }
2741
2742 for (i = 0; i < entries; ++i) {
2743 tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift,
2744 levels, limit, current_offset, total_allocated);
2745 if (!tmp)
2746 break;
2747
2748 addr[i] = cpu_to_be64(__pa(tmp) |
2749 TCE_PCI_READ | TCE_PCI_WRITE);
2750
2751 if (*current_offset >= limit)
2752 break;
2753 }
2754
2755 return addr;
2756 }
2757
2758 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2759 unsigned long size, unsigned level);
2760
2761 static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
2762 __u32 page_shift, __u64 window_size, __u32 levels,
2763 struct iommu_table *tbl)
2764 {
2765 void *addr;
2766 unsigned long offset = 0, level_shift, total_allocated = 0;
2767 const unsigned window_shift = ilog2(window_size);
2768 unsigned entries_shift = window_shift - page_shift;
2769 unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT);
2770 const unsigned long tce_table_size = 1UL << table_shift;
2771
2772 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
2773 return -EINVAL;
2774
2775 if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
2776 return -EINVAL;
2777
2778 /* Adjust direct table size from window_size and levels */
2779 entries_shift = (entries_shift + levels - 1) / levels;
2780 level_shift = entries_shift + 3;
2781 level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
2782
2783 if ((level_shift - 3) * levels + page_shift >= 60)
2784 return -EINVAL;
2785
2786 /* Allocate TCE table */
2787 addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift,
2788 levels, tce_table_size, &offset, &total_allocated);
2789
2790 /* addr==NULL means that the first level allocation failed */
2791 if (!addr)
2792 return -ENOMEM;
2793
2794 /*
2795 * First level was allocated but some lower level failed as
2796 * we did not allocate as much as we wanted,
2797 * release partially allocated table.
2798 */
2799 if (offset < tce_table_size) {
2800 pnv_pci_ioda2_table_do_free_pages(addr,
2801 1ULL << (level_shift - 3), levels - 1);
2802 return -ENOMEM;
2803 }
2804
2805 /* Setup linux iommu table */
2806 pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset,
2807 page_shift);
2808 tbl->it_level_size = 1ULL << (level_shift - 3);
2809 tbl->it_indirect_levels = levels - 1;
2810 tbl->it_allocated_size = total_allocated;
2811
2812 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2813 window_size, tce_table_size, bus_offset);
2814
2815 return 0;
2816 }
2817
2818 static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
2819 unsigned long size, unsigned level)
2820 {
2821 const unsigned long addr_ul = (unsigned long) addr &
2822 ~(TCE_PCI_READ | TCE_PCI_WRITE);
2823
2824 if (level) {
2825 long i;
2826 u64 *tmp = (u64 *) addr_ul;
2827
2828 for (i = 0; i < size; ++i) {
2829 unsigned long hpa = be64_to_cpu(tmp[i]);
2830
2831 if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
2832 continue;
2833
2834 pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
2835 level - 1);
2836 }
2837 }
2838
2839 free_pages(addr_ul, get_order(size << 3));
2840 }
2841
2842 static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
2843 {
2844 const unsigned long size = tbl->it_indirect_levels ?
2845 tbl->it_level_size : tbl->it_size;
2846
2847 if (!tbl->it_size)
2848 return;
2849
2850 pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
2851 tbl->it_indirect_levels);
2852 }
2853
2854 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2855 struct pnv_ioda_pe *pe)
2856 {
2857 int64_t rc;
2858
2859 if (!pnv_pci_ioda_pe_dma_weight(pe))
2860 return;
2861
2862 /* TVE #1 is selected by PCI address bit 59 */
2863 pe->tce_bypass_base = 1ull << 59;
2864
2865 iommu_register_group(&pe->table_group, phb->hose->global_number,
2866 pe->pe_number);
2867
2868 /* The PE will reserve all possible 32-bits space */
2869 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2870 phb->ioda.m32_pci_base);
2871
2872 /* Setup linux iommu table */
2873 pe->table_group.tce32_start = 0;
2874 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2875 pe->table_group.max_dynamic_windows_supported =
2876 IOMMU_TABLE_GROUP_MAX_TABLES;
2877 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2878 pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
2879 #ifdef CONFIG_IOMMU_API
2880 pe->table_group.ops = &pnv_pci_ioda2_ops;
2881 #endif
2882
2883 rc = pnv_pci_ioda2_setup_default_config(pe);
2884 if (rc)
2885 return;
2886
2887 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2888 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2889 }
2890
2891 #ifdef CONFIG_PCI_MSI
2892 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2893 {
2894 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2895 ioda.irq_chip);
2896
2897 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2898 }
2899
2900 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2901 {
2902 int64_t rc;
2903 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2904 struct irq_chip *chip = irq_data_get_irq_chip(d);
2905
2906 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2907 WARN_ON_ONCE(rc);
2908
2909 icp_native_eoi(d);
2910 }
2911
2912
2913 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2914 {
2915 struct irq_data *idata;
2916 struct irq_chip *ichip;
2917
2918 /* The MSI EOI OPAL call is only needed on PHB3 */
2919 if (phb->model != PNV_PHB_MODEL_PHB3)
2920 return;
2921
2922 if (!phb->ioda.irq_chip_init) {
2923 /*
2924 * First time we setup an MSI IRQ, we need to setup the
2925 * corresponding IRQ chip to route correctly.
2926 */
2927 idata = irq_get_irq_data(virq);
2928 ichip = irq_data_get_irq_chip(idata);
2929 phb->ioda.irq_chip_init = 1;
2930 phb->ioda.irq_chip = *ichip;
2931 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2932 }
2933 irq_set_chip(virq, &phb->ioda.irq_chip);
2934 }
2935
2936 /*
2937 * Returns true iff chip is something that we could call
2938 * pnv_opal_pci_msi_eoi for.
2939 */
2940 bool is_pnv_opal_msi(struct irq_chip *chip)
2941 {
2942 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2943 }
2944 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2945
2946 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2947 unsigned int hwirq, unsigned int virq,
2948 unsigned int is_64, struct msi_msg *msg)
2949 {
2950 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2951 unsigned int xive_num = hwirq - phb->msi_base;
2952 __be32 data;
2953 int rc;
2954
2955 /* No PE assigned ? bail out ... no MSI for you ! */
2956 if (pe == NULL)
2957 return -ENXIO;
2958
2959 /* Check if we have an MVE */
2960 if (pe->mve_number < 0)
2961 return -ENXIO;
2962
2963 /* Force 32-bit MSI on some broken devices */
2964 if (dev->no_64bit_msi)
2965 is_64 = 0;
2966
2967 /* Assign XIVE to PE */
2968 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2969 if (rc) {
2970 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2971 pci_name(dev), rc, xive_num);
2972 return -EIO;
2973 }
2974
2975 if (is_64) {
2976 __be64 addr64;
2977
2978 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2979 &addr64, &data);
2980 if (rc) {
2981 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2982 pci_name(dev), rc);
2983 return -EIO;
2984 }
2985 msg->address_hi = be64_to_cpu(addr64) >> 32;
2986 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2987 } else {
2988 __be32 addr32;
2989
2990 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2991 &addr32, &data);
2992 if (rc) {
2993 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2994 pci_name(dev), rc);
2995 return -EIO;
2996 }
2997 msg->address_hi = 0;
2998 msg->address_lo = be32_to_cpu(addr32);
2999 }
3000 msg->data = be32_to_cpu(data);
3001
3002 pnv_set_msi_irq_chip(phb, virq);
3003
3004 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
3005 " address=%x_%08x data=%x PE# %x\n",
3006 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
3007 msg->address_hi, msg->address_lo, data, pe->pe_number);
3008
3009 return 0;
3010 }
3011
3012 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
3013 {
3014 unsigned int count;
3015 const __be32 *prop = of_get_property(phb->hose->dn,
3016 "ibm,opal-msi-ranges", NULL);
3017 if (!prop) {
3018 /* BML Fallback */
3019 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
3020 }
3021 if (!prop)
3022 return;
3023
3024 phb->msi_base = be32_to_cpup(prop);
3025 count = be32_to_cpup(prop + 1);
3026 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
3027 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
3028 phb->hose->global_number);
3029 return;
3030 }
3031
3032 phb->msi_setup = pnv_pci_ioda_msi_setup;
3033 phb->msi32_support = 1;
3034 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
3035 count, phb->msi_base);
3036 }
3037 #else
3038 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
3039 #endif /* CONFIG_PCI_MSI */
3040
3041 #ifdef CONFIG_PCI_IOV
3042 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
3043 {
3044 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3045 struct pnv_phb *phb = hose->private_data;
3046 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
3047 struct resource *res;
3048 int i;
3049 resource_size_t size, total_vf_bar_sz;
3050 struct pci_dn *pdn;
3051 int mul, total_vfs;
3052
3053 if (!pdev->is_physfn || pdev->is_added)
3054 return;
3055
3056 pdn = pci_get_pdn(pdev);
3057 pdn->vfs_expanded = 0;
3058 pdn->m64_single_mode = false;
3059
3060 total_vfs = pci_sriov_get_totalvfs(pdev);
3061 mul = phb->ioda.total_pe_num;
3062 total_vf_bar_sz = 0;
3063
3064 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3065 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3066 if (!res->flags || res->parent)
3067 continue;
3068 if (!pnv_pci_is_m64_flags(res->flags)) {
3069 dev_warn(&pdev->dev, "Don't support SR-IOV with"
3070 " non M64 VF BAR%d: %pR. \n",
3071 i, res);
3072 goto truncate_iov;
3073 }
3074
3075 total_vf_bar_sz += pci_iov_resource_size(pdev,
3076 i + PCI_IOV_RESOURCES);
3077
3078 /*
3079 * If bigger than quarter of M64 segment size, just round up
3080 * power of two.
3081 *
3082 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
3083 * with other devices, IOV BAR size is expanded to be
3084 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
3085 * segment size , the expanded size would equal to half of the
3086 * whole M64 space size, which will exhaust the M64 Space and
3087 * limit the system flexibility. This is a design decision to
3088 * set the boundary to quarter of the M64 segment size.
3089 */
3090 if (total_vf_bar_sz > gate) {
3091 mul = roundup_pow_of_two(total_vfs);
3092 dev_info(&pdev->dev,
3093 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
3094 total_vf_bar_sz, gate, mul);
3095 pdn->m64_single_mode = true;
3096 break;
3097 }
3098 }
3099
3100 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3101 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3102 if (!res->flags || res->parent)
3103 continue;
3104
3105 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3106 /*
3107 * On PHB3, the minimum size alignment of M64 BAR in single
3108 * mode is 32MB.
3109 */
3110 if (pdn->m64_single_mode && (size < SZ_32M))
3111 goto truncate_iov;
3112 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3113 res->end = res->start + size * mul - 1;
3114 dev_dbg(&pdev->dev, " %pR\n", res);
3115 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3116 i, res, mul);
3117 }
3118 pdn->vfs_expanded = mul;
3119
3120 return;
3121
3122 truncate_iov:
3123 /* To save MMIO space, IOV BAR is truncated. */
3124 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3125 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3126 res->flags = 0;
3127 res->end = res->start - 1;
3128 }
3129 }
3130 #endif /* CONFIG_PCI_IOV */
3131
3132 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3133 struct resource *res)
3134 {
3135 struct pnv_phb *phb = pe->phb;
3136 struct pci_bus_region region;
3137 int index;
3138 int64_t rc;
3139
3140 if (!res || !res->flags || res->start > res->end)
3141 return;
3142
3143 if (res->flags & IORESOURCE_IO) {
3144 region.start = res->start - phb->ioda.io_pci_base;
3145 region.end = res->end - phb->ioda.io_pci_base;
3146 index = region.start / phb->ioda.io_segsize;
3147
3148 while (index < phb->ioda.total_pe_num &&
3149 region.start <= region.end) {
3150 phb->ioda.io_segmap[index] = pe->pe_number;
3151 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3152 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3153 if (rc != OPAL_SUCCESS) {
3154 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3155 __func__, rc, index, pe->pe_number);
3156 break;
3157 }
3158
3159 region.start += phb->ioda.io_segsize;
3160 index++;
3161 }
3162 } else if ((res->flags & IORESOURCE_MEM) &&
3163 !pnv_pci_is_m64(phb, res)) {
3164 region.start = res->start -
3165 phb->hose->mem_offset[0] -
3166 phb->ioda.m32_pci_base;
3167 region.end = res->end -
3168 phb->hose->mem_offset[0] -
3169 phb->ioda.m32_pci_base;
3170 index = region.start / phb->ioda.m32_segsize;
3171
3172 while (index < phb->ioda.total_pe_num &&
3173 region.start <= region.end) {
3174 phb->ioda.m32_segmap[index] = pe->pe_number;
3175 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3176 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3177 if (rc != OPAL_SUCCESS) {
3178 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3179 __func__, rc, index, pe->pe_number);
3180 break;
3181 }
3182
3183 region.start += phb->ioda.m32_segsize;
3184 index++;
3185 }
3186 }
3187 }
3188
3189 /*
3190 * This function is supposed to be called on basis of PE from top
3191 * to bottom style. So the the I/O or MMIO segment assigned to
3192 * parent PE could be overridden by its child PEs if necessary.
3193 */
3194 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3195 {
3196 struct pci_dev *pdev;
3197 int i;
3198
3199 /*
3200 * NOTE: We only care PCI bus based PE for now. For PCI
3201 * device based PE, for example SRIOV sensitive VF should
3202 * be figured out later.
3203 */
3204 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3205
3206 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3207 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3208 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3209
3210 /*
3211 * If the PE contains all subordinate PCI buses, the
3212 * windows of the child bridges should be mapped to
3213 * the PE as well.
3214 */
3215 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3216 continue;
3217 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3218 pnv_ioda_setup_pe_res(pe,
3219 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3220 }
3221 }
3222
3223 #ifdef CONFIG_DEBUG_FS
3224 static int pnv_pci_diag_data_set(void *data, u64 val)
3225 {
3226 struct pci_controller *hose;
3227 struct pnv_phb *phb;
3228 s64 ret;
3229
3230 if (val != 1ULL)
3231 return -EINVAL;
3232
3233 hose = (struct pci_controller *)data;
3234 if (!hose || !hose->private_data)
3235 return -ENODEV;
3236
3237 phb = hose->private_data;
3238
3239 /* Retrieve the diag data from firmware */
3240 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3241 phb->diag_data_size);
3242 if (ret != OPAL_SUCCESS)
3243 return -EIO;
3244
3245 /* Print the diag data to the kernel log */
3246 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3247 return 0;
3248 }
3249
3250 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3251 pnv_pci_diag_data_set, "%llu\n");
3252
3253 #endif /* CONFIG_DEBUG_FS */
3254
3255 static void pnv_pci_ioda_create_dbgfs(void)
3256 {
3257 #ifdef CONFIG_DEBUG_FS
3258 struct pci_controller *hose, *tmp;
3259 struct pnv_phb *phb;
3260 char name[16];
3261
3262 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3263 phb = hose->private_data;
3264
3265 /* Notify initialization of PHB done */
3266 phb->initialized = 1;
3267
3268 sprintf(name, "PCI%04x", hose->global_number);
3269 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3270 if (!phb->dbgfs) {
3271 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3272 __func__, hose->global_number);
3273 continue;
3274 }
3275
3276 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3277 &pnv_pci_diag_data_fops);
3278 }
3279 #endif /* CONFIG_DEBUG_FS */
3280 }
3281
3282 static void pnv_pci_ioda_fixup(void)
3283 {
3284 pnv_pci_ioda_setup_PEs();
3285 pnv_pci_ioda_setup_iommu_api();
3286 pnv_pci_ioda_create_dbgfs();
3287
3288 #ifdef CONFIG_EEH
3289 eeh_init();
3290 eeh_addr_cache_build();
3291 #endif
3292 }
3293
3294 /*
3295 * Returns the alignment for I/O or memory windows for P2P
3296 * bridges. That actually depends on how PEs are segmented.
3297 * For now, we return I/O or M32 segment size for PE sensitive
3298 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3299 * 1MiB for memory) will be returned.
3300 *
3301 * The current PCI bus might be put into one PE, which was
3302 * create against the parent PCI bridge. For that case, we
3303 * needn't enlarge the alignment so that we can save some
3304 * resources.
3305 */
3306 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3307 unsigned long type)
3308 {
3309 struct pci_dev *bridge;
3310 struct pci_controller *hose = pci_bus_to_host(bus);
3311 struct pnv_phb *phb = hose->private_data;
3312 int num_pci_bridges = 0;
3313
3314 bridge = bus->self;
3315 while (bridge) {
3316 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3317 num_pci_bridges++;
3318 if (num_pci_bridges >= 2)
3319 return 1;
3320 }
3321
3322 bridge = bridge->bus->self;
3323 }
3324
3325 /*
3326 * We fall back to M32 if M64 isn't supported. We enforce the M64
3327 * alignment for any 64-bit resource, PCIe doesn't care and
3328 * bridges only do 64-bit prefetchable anyway.
3329 */
3330 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3331 return phb->ioda.m64_segsize;
3332 if (type & IORESOURCE_MEM)
3333 return phb->ioda.m32_segsize;
3334
3335 return phb->ioda.io_segsize;
3336 }
3337
3338 /*
3339 * We are updating root port or the upstream port of the
3340 * bridge behind the root port with PHB's windows in order
3341 * to accommodate the changes on required resources during
3342 * PCI (slot) hotplug, which is connected to either root
3343 * port or the downstream ports of PCIe switch behind the
3344 * root port.
3345 */
3346 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3347 unsigned long type)
3348 {
3349 struct pci_controller *hose = pci_bus_to_host(bus);
3350 struct pnv_phb *phb = hose->private_data;
3351 struct pci_dev *bridge = bus->self;
3352 struct resource *r, *w;
3353 bool msi_region = false;
3354 int i;
3355
3356 /* Check if we need apply fixup to the bridge's windows */
3357 if (!pci_is_root_bus(bridge->bus) &&
3358 !pci_is_root_bus(bridge->bus->self->bus))
3359 return;
3360
3361 /* Fixup the resources */
3362 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3363 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3364 if (!r->flags || !r->parent)
3365 continue;
3366
3367 w = NULL;
3368 if (r->flags & type & IORESOURCE_IO)
3369 w = &hose->io_resource;
3370 else if (pnv_pci_is_m64(phb, r) &&
3371 (type & IORESOURCE_PREFETCH) &&
3372 phb->ioda.m64_segsize)
3373 w = &hose->mem_resources[1];
3374 else if (r->flags & type & IORESOURCE_MEM) {
3375 w = &hose->mem_resources[0];
3376 msi_region = true;
3377 }
3378
3379 r->start = w->start;
3380 r->end = w->end;
3381
3382 /* The 64KB 32-bits MSI region shouldn't be included in
3383 * the 32-bits bridge window. Otherwise, we can see strange
3384 * issues. One of them is EEH error observed on Garrison.
3385 *
3386 * Exclude top 1MB region which is the minimal alignment of
3387 * 32-bits bridge window.
3388 */
3389 if (msi_region) {
3390 r->end += 0x10000;
3391 r->end -= 0x100000;
3392 }
3393 }
3394 }
3395
3396 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3397 {
3398 struct pci_controller *hose = pci_bus_to_host(bus);
3399 struct pnv_phb *phb = hose->private_data;
3400 struct pci_dev *bridge = bus->self;
3401 struct pnv_ioda_pe *pe;
3402 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3403
3404 /* Extend bridge's windows if necessary */
3405 pnv_pci_fixup_bridge_resources(bus, type);
3406
3407 /* The PE for root bus should be realized before any one else */
3408 if (!phb->ioda.root_pe_populated) {
3409 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3410 if (pe) {
3411 phb->ioda.root_pe_idx = pe->pe_number;
3412 phb->ioda.root_pe_populated = true;
3413 }
3414 }
3415
3416 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3417 if (list_empty(&bus->devices))
3418 return;
3419
3420 /* Reserve PEs according to used M64 resources */
3421 if (phb->reserve_m64_pe)
3422 phb->reserve_m64_pe(bus, NULL, all);
3423
3424 /*
3425 * Assign PE. We might run here because of partial hotplug.
3426 * For the case, we just pick up the existing PE and should
3427 * not allocate resources again.
3428 */
3429 pe = pnv_ioda_setup_bus_PE(bus, all);
3430 if (!pe)
3431 return;
3432
3433 pnv_ioda_setup_pe_seg(pe);
3434 switch (phb->type) {
3435 case PNV_PHB_IODA1:
3436 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3437 break;
3438 case PNV_PHB_IODA2:
3439 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3440 break;
3441 default:
3442 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3443 __func__, phb->hose->global_number, phb->type);
3444 }
3445 }
3446
3447 static resource_size_t pnv_pci_default_alignment(void)
3448 {
3449 return PAGE_SIZE;
3450 }
3451
3452 #ifdef CONFIG_PCI_IOV
3453 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3454 int resno)
3455 {
3456 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3457 struct pnv_phb *phb = hose->private_data;
3458 struct pci_dn *pdn = pci_get_pdn(pdev);
3459 resource_size_t align;
3460
3461 /*
3462 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3463 * SR-IOV. While from hardware perspective, the range mapped by M64
3464 * BAR should be size aligned.
3465 *
3466 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3467 * powernv-specific hardware restriction is gone. But if just use the
3468 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3469 * in one segment of M64 #15, which introduces the PE conflict between
3470 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3471 * m64_segsize.
3472 *
3473 * This function returns the total IOV BAR size if M64 BAR is in
3474 * Shared PE mode or just VF BAR size if not.
3475 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3476 * M64 segment size if IOV BAR size is less.
3477 */
3478 align = pci_iov_resource_size(pdev, resno);
3479 if (!pdn->vfs_expanded)
3480 return align;
3481 if (pdn->m64_single_mode)
3482 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3483
3484 return pdn->vfs_expanded * align;
3485 }
3486 #endif /* CONFIG_PCI_IOV */
3487
3488 /* Prevent enabling devices for which we couldn't properly
3489 * assign a PE
3490 */
3491 bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3492 {
3493 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3494 struct pnv_phb *phb = hose->private_data;
3495 struct pci_dn *pdn;
3496
3497 /* The function is probably called while the PEs have
3498 * not be created yet. For example, resource reassignment
3499 * during PCI probe period. We just skip the check if
3500 * PEs isn't ready.
3501 */
3502 if (!phb->initialized)
3503 return true;
3504
3505 pdn = pci_get_pdn(dev);
3506 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3507 return false;
3508
3509 return true;
3510 }
3511
3512 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3513 int num)
3514 {
3515 struct pnv_ioda_pe *pe = container_of(table_group,
3516 struct pnv_ioda_pe, table_group);
3517 struct pnv_phb *phb = pe->phb;
3518 unsigned int idx;
3519 long rc;
3520
3521 pe_info(pe, "Removing DMA window #%d\n", num);
3522 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3523 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3524 continue;
3525
3526 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3527 idx, 0, 0ul, 0ul, 0ul);
3528 if (rc != OPAL_SUCCESS) {
3529 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3530 rc, idx);
3531 return rc;
3532 }
3533
3534 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3535 }
3536
3537 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3538 return OPAL_SUCCESS;
3539 }
3540
3541 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3542 {
3543 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3544 struct iommu_table *tbl = pe->table_group.tables[0];
3545 int64_t rc;
3546
3547 if (!weight)
3548 return;
3549
3550 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3551 if (rc != OPAL_SUCCESS)
3552 return;
3553
3554 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3555 if (pe->table_group.group) {
3556 iommu_group_put(pe->table_group.group);
3557 WARN_ON(pe->table_group.group);
3558 }
3559
3560 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3561 iommu_tce_table_put(tbl);
3562 }
3563
3564 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3565 {
3566 struct iommu_table *tbl = pe->table_group.tables[0];
3567 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3568 #ifdef CONFIG_IOMMU_API
3569 int64_t rc;
3570 #endif
3571
3572 if (!weight)
3573 return;
3574
3575 #ifdef CONFIG_IOMMU_API
3576 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3577 if (rc)
3578 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3579 #endif
3580
3581 pnv_pci_ioda2_set_bypass(pe, false);
3582 if (pe->table_group.group) {
3583 iommu_group_put(pe->table_group.group);
3584 WARN_ON(pe->table_group.group);
3585 }
3586
3587 pnv_pci_ioda2_table_free_pages(tbl);
3588 iommu_tce_table_put(tbl);
3589 }
3590
3591 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3592 unsigned short win,
3593 unsigned int *map)
3594 {
3595 struct pnv_phb *phb = pe->phb;
3596 int idx;
3597 int64_t rc;
3598
3599 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3600 if (map[idx] != pe->pe_number)
3601 continue;
3602
3603 if (win == OPAL_M64_WINDOW_TYPE)
3604 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3605 phb->ioda.reserved_pe_idx, win,
3606 idx / PNV_IODA1_M64_SEGS,
3607 idx % PNV_IODA1_M64_SEGS);
3608 else
3609 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3610 phb->ioda.reserved_pe_idx, win, 0, idx);
3611
3612 if (rc != OPAL_SUCCESS)
3613 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3614 rc, win, idx);
3615
3616 map[idx] = IODA_INVALID_PE;
3617 }
3618 }
3619
3620 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3621 {
3622 struct pnv_phb *phb = pe->phb;
3623
3624 if (phb->type == PNV_PHB_IODA1) {
3625 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3626 phb->ioda.io_segmap);
3627 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3628 phb->ioda.m32_segmap);
3629 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3630 phb->ioda.m64_segmap);
3631 } else if (phb->type == PNV_PHB_IODA2) {
3632 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3633 phb->ioda.m32_segmap);
3634 }
3635 }
3636
3637 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3638 {
3639 struct pnv_phb *phb = pe->phb;
3640 struct pnv_ioda_pe *slave, *tmp;
3641
3642 list_del(&pe->list);
3643 switch (phb->type) {
3644 case PNV_PHB_IODA1:
3645 pnv_pci_ioda1_release_pe_dma(pe);
3646 break;
3647 case PNV_PHB_IODA2:
3648 pnv_pci_ioda2_release_pe_dma(pe);
3649 break;
3650 default:
3651 WARN_ON(1);
3652 }
3653
3654 pnv_ioda_release_pe_seg(pe);
3655 pnv_ioda_deconfigure_pe(pe->phb, pe);
3656
3657 /* Release slave PEs in the compound PE */
3658 if (pe->flags & PNV_IODA_PE_MASTER) {
3659 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3660 list_del(&slave->list);
3661 pnv_ioda_free_pe(slave);
3662 }
3663 }
3664
3665 /*
3666 * The PE for root bus can be removed because of hotplug in EEH
3667 * recovery for fenced PHB error. We need to mark the PE dead so
3668 * that it can be populated again in PCI hot add path. The PE
3669 * shouldn't be destroyed as it's the global reserved resource.
3670 */
3671 if (phb->ioda.root_pe_populated &&
3672 phb->ioda.root_pe_idx == pe->pe_number)
3673 phb->ioda.root_pe_populated = false;
3674 else
3675 pnv_ioda_free_pe(pe);
3676 }
3677
3678 static void pnv_pci_release_device(struct pci_dev *pdev)
3679 {
3680 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3681 struct pnv_phb *phb = hose->private_data;
3682 struct pci_dn *pdn = pci_get_pdn(pdev);
3683 struct pnv_ioda_pe *pe;
3684
3685 if (pdev->is_virtfn)
3686 return;
3687
3688 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3689 return;
3690
3691 /*
3692 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3693 * isn't removed and added afterwards in this scenario. We should
3694 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3695 * device count is decreased on removing devices while failing to
3696 * be increased on adding devices. It leads to unbalanced PE's device
3697 * count and eventually make normal PCI hotplug path broken.
3698 */
3699 pe = &phb->ioda.pe_array[pdn->pe_number];
3700 pdn->pe_number = IODA_INVALID_PE;
3701
3702 WARN_ON(--pe->device_count < 0);
3703 if (pe->device_count == 0)
3704 pnv_ioda_release_pe(pe);
3705 }
3706
3707 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3708 {
3709 struct pnv_phb *phb = hose->private_data;
3710
3711 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3712 OPAL_ASSERT_RESET);
3713 }
3714
3715 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3716 .dma_dev_setup = pnv_pci_dma_dev_setup,
3717 .dma_bus_setup = pnv_pci_dma_bus_setup,
3718 #ifdef CONFIG_PCI_MSI
3719 .setup_msi_irqs = pnv_setup_msi_irqs,
3720 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3721 #endif
3722 .enable_device_hook = pnv_pci_enable_device_hook,
3723 .release_device = pnv_pci_release_device,
3724 .window_alignment = pnv_pci_window_alignment,
3725 .setup_bridge = pnv_pci_setup_bridge,
3726 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3727 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3728 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3729 .shutdown = pnv_pci_ioda_shutdown,
3730 };
3731
3732 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3733 {
3734 dev_err_once(&npdev->dev,
3735 "%s operation unsupported for NVLink devices\n",
3736 __func__);
3737 return -EPERM;
3738 }
3739
3740 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3741 .dma_dev_setup = pnv_pci_dma_dev_setup,
3742 #ifdef CONFIG_PCI_MSI
3743 .setup_msi_irqs = pnv_setup_msi_irqs,
3744 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3745 #endif
3746 .enable_device_hook = pnv_pci_enable_device_hook,
3747 .window_alignment = pnv_pci_window_alignment,
3748 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3749 .dma_set_mask = pnv_npu_dma_set_mask,
3750 .shutdown = pnv_pci_ioda_shutdown,
3751 };
3752
3753 #ifdef CONFIG_CXL_BASE
3754 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = {
3755 .dma_dev_setup = pnv_pci_dma_dev_setup,
3756 .dma_bus_setup = pnv_pci_dma_bus_setup,
3757 #ifdef CONFIG_PCI_MSI
3758 .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs,
3759 .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs,
3760 #endif
3761 .enable_device_hook = pnv_cxl_enable_device_hook,
3762 .disable_device = pnv_cxl_disable_device,
3763 .release_device = pnv_pci_release_device,
3764 .window_alignment = pnv_pci_window_alignment,
3765 .setup_bridge = pnv_pci_setup_bridge,
3766 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3767 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3768 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3769 .shutdown = pnv_pci_ioda_shutdown,
3770 };
3771 #endif
3772
3773 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3774 u64 hub_id, int ioda_type)
3775 {
3776 struct pci_controller *hose;
3777 struct pnv_phb *phb;
3778 unsigned long size, m64map_off, m32map_off, pemap_off;
3779 unsigned long iomap_off = 0, dma32map_off = 0;
3780 struct resource r;
3781 const __be64 *prop64;
3782 const __be32 *prop32;
3783 int len;
3784 unsigned int segno;
3785 u64 phb_id;
3786 void *aux;
3787 long rc;
3788
3789 if (!of_device_is_available(np))
3790 return;
3791
3792 pr_info("Initializing %s PHB (%s)\n",
3793 pnv_phb_names[ioda_type], of_node_full_name(np));
3794
3795 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3796 if (!prop64) {
3797 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3798 return;
3799 }
3800 phb_id = be64_to_cpup(prop64);
3801 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3802
3803 phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0);
3804
3805 /* Allocate PCI controller */
3806 phb->hose = hose = pcibios_alloc_controller(np);
3807 if (!phb->hose) {
3808 pr_err(" Can't allocate PCI controller for %s\n",
3809 np->full_name);
3810 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3811 return;
3812 }
3813
3814 spin_lock_init(&phb->lock);
3815 prop32 = of_get_property(np, "bus-range", &len);
3816 if (prop32 && len == 8) {
3817 hose->first_busno = be32_to_cpu(prop32[0]);
3818 hose->last_busno = be32_to_cpu(prop32[1]);
3819 } else {
3820 pr_warn(" Broken <bus-range> on %s\n", np->full_name);
3821 hose->first_busno = 0;
3822 hose->last_busno = 0xff;
3823 }
3824 hose->private_data = phb;
3825 phb->hub_id = hub_id;
3826 phb->opal_id = phb_id;
3827 phb->type = ioda_type;
3828 mutex_init(&phb->ioda.pe_alloc_mutex);
3829
3830 /* Detect specific models for error handling */
3831 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3832 phb->model = PNV_PHB_MODEL_P7IOC;
3833 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3834 phb->model = PNV_PHB_MODEL_PHB3;
3835 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3836 phb->model = PNV_PHB_MODEL_NPU;
3837 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3838 phb->model = PNV_PHB_MODEL_NPU2;
3839 else
3840 phb->model = PNV_PHB_MODEL_UNKNOWN;
3841
3842 /* Initialize diagnostic data buffer */
3843 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3844 if (prop32)
3845 phb->diag_data_size = be32_to_cpup(prop32);
3846 else
3847 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3848
3849 phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0);
3850
3851 /* Parse 32-bit and IO ranges (if any) */
3852 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3853
3854 /* Get registers */
3855 if (!of_address_to_resource(np, 0, &r)) {
3856 phb->regs_phys = r.start;
3857 phb->regs = ioremap(r.start, resource_size(&r));
3858 if (phb->regs == NULL)
3859 pr_err(" Failed to map registers !\n");
3860 }
3861
3862 /* Initialize more IODA stuff */
3863 phb->ioda.total_pe_num = 1;
3864 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3865 if (prop32)
3866 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3867 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3868 if (prop32)
3869 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3870
3871 /* Invalidate RID to PE# mapping */
3872 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3873 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3874
3875 /* Parse 64-bit MMIO range */
3876 pnv_ioda_parse_m64_window(phb);
3877
3878 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3879 /* FW Has already off top 64k of M32 space (MSI space) */
3880 phb->ioda.m32_size += 0x10000;
3881
3882 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3883 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3884 phb->ioda.io_size = hose->pci_io_size;
3885 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3886 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3887
3888 /* Calculate how many 32-bit TCE segments we have */
3889 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3890 PNV_IODA1_DMA32_SEGSIZE;
3891
3892 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3893 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3894 sizeof(unsigned long));
3895 m64map_off = size;
3896 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3897 m32map_off = size;
3898 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3899 if (phb->type == PNV_PHB_IODA1) {
3900 iomap_off = size;
3901 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3902 dma32map_off = size;
3903 size += phb->ioda.dma32_count *
3904 sizeof(phb->ioda.dma32_segmap[0]);
3905 }
3906 pemap_off = size;
3907 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3908 aux = memblock_virt_alloc(size, 0);
3909 phb->ioda.pe_alloc = aux;
3910 phb->ioda.m64_segmap = aux + m64map_off;
3911 phb->ioda.m32_segmap = aux + m32map_off;
3912 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3913 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3914 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3915 }
3916 if (phb->type == PNV_PHB_IODA1) {
3917 phb->ioda.io_segmap = aux + iomap_off;
3918 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3919 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3920
3921 phb->ioda.dma32_segmap = aux + dma32map_off;
3922 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3923 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3924 }
3925 phb->ioda.pe_array = aux + pemap_off;
3926
3927 /*
3928 * Choose PE number for root bus, which shouldn't have
3929 * M64 resources consumed by its child devices. To pick
3930 * the PE number adjacent to the reserved one if possible.
3931 */
3932 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3933 if (phb->ioda.reserved_pe_idx == 0) {
3934 phb->ioda.root_pe_idx = 1;
3935 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3936 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3937 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3938 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3939 } else {
3940 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3941 }
3942
3943 INIT_LIST_HEAD(&phb->ioda.pe_list);
3944 mutex_init(&phb->ioda.pe_list_mutex);
3945
3946 /* Calculate how many 32-bit TCE segments we have */
3947 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3948 PNV_IODA1_DMA32_SEGSIZE;
3949
3950 #if 0 /* We should really do that ... */
3951 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3952 window_type,
3953 window_num,
3954 starting_real_address,
3955 starting_pci_address,
3956 segment_size);
3957 #endif
3958
3959 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3960 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3961 phb->ioda.m32_size, phb->ioda.m32_segsize);
3962 if (phb->ioda.m64_size)
3963 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3964 phb->ioda.m64_size, phb->ioda.m64_segsize);
3965 if (phb->ioda.io_size)
3966 pr_info(" IO: 0x%x [segment=0x%x]\n",
3967 phb->ioda.io_size, phb->ioda.io_segsize);
3968
3969
3970 phb->hose->ops = &pnv_pci_ops;
3971 phb->get_pe_state = pnv_ioda_get_pe_state;
3972 phb->freeze_pe = pnv_ioda_freeze_pe;
3973 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3974
3975 /* Setup MSI support */
3976 pnv_pci_init_ioda_msis(phb);
3977
3978 /*
3979 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3980 * to let the PCI core do resource assignment. It's supposed
3981 * that the PCI core will do correct I/O and MMIO alignment
3982 * for the P2P bridge bars so that each PCI bus (excluding
3983 * the child P2P bridges) can form individual PE.
3984 */
3985 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3986
3987 if (phb->type == PNV_PHB_NPU) {
3988 hose->controller_ops = pnv_npu_ioda_controller_ops;
3989 } else {
3990 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3991 hose->controller_ops = pnv_pci_ioda_controller_ops;
3992 }
3993
3994 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3995
3996 #ifdef CONFIG_PCI_IOV
3997 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3998 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3999 #endif
4000
4001 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
4002
4003 /* Reset IODA tables to a clean state */
4004 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
4005 if (rc)
4006 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc);
4007
4008 /*
4009 * If we're running in kdump kernel, the previous kernel never
4010 * shutdown PCI devices correctly. We already got IODA table
4011 * cleaned out. So we have to issue PHB reset to stop all PCI
4012 * transactions from previous kernel.
4013 */
4014 if (is_kdump_kernel()) {
4015 pr_info(" Issue PHB reset ...\n");
4016 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
4017 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
4018 }
4019
4020 /* Remove M64 resource if we can't configure it successfully */
4021 if (!phb->init_m64 || phb->init_m64(phb))
4022 hose->mem_resources[1].flags = 0;
4023 }
4024
4025 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
4026 {
4027 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
4028 }
4029
4030 void __init pnv_pci_init_npu_phb(struct device_node *np)
4031 {
4032 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU);
4033 }
4034
4035 void __init pnv_pci_init_ioda_hub(struct device_node *np)
4036 {
4037 struct device_node *phbn;
4038 const __be64 *prop64;
4039 u64 hub_id;
4040
4041 pr_info("Probing IODA IO-Hub %s\n", np->full_name);
4042
4043 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
4044 if (!prop64) {
4045 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
4046 return;
4047 }
4048 hub_id = be64_to_cpup(prop64);
4049 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
4050
4051 /* Count child PHBs */
4052 for_each_child_of_node(np, phbn) {
4053 /* Look for IODA1 PHBs */
4054 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
4055 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
4056 }
4057 }
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