2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/memblock.h>
21 #include <linux/irq.h>
23 #include <linux/msi.h>
24 #include <linux/iommu.h>
25 #include <linux/rculist.h>
26 #include <linux/sizes.h>
28 #include <asm/sections.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/machdep.h>
33 #include <asm/msi_bitmap.h>
34 #include <asm/ppc-pci.h>
36 #include <asm/iommu.h>
39 #include <asm/debugfs.h>
40 #include <asm/firmware.h>
41 #include <asm/pnv-pci.h>
42 #include <asm/mmzone.h>
44 #include <misc/cxl-base.h>
48 #include "../../../../drivers/pci/pci.h"
50 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
51 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
54 static const char * const pnv_phb_names
[] = { "IODA1", "IODA2", "NPU_NVLINK",
57 void pe_level_printk(const struct pnv_ioda_pe
*pe
, const char *level
,
69 if (pe
->flags
& PNV_IODA_PE_DEV
)
70 strlcpy(pfix
, dev_name(&pe
->pdev
->dev
), sizeof(pfix
));
71 else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
72 sprintf(pfix
, "%04x:%02x ",
73 pci_domain_nr(pe
->pbus
), pe
->pbus
->number
);
75 else if (pe
->flags
& PNV_IODA_PE_VF
)
76 sprintf(pfix
, "%04x:%02x:%2x.%d",
77 pci_domain_nr(pe
->parent_dev
->bus
),
78 (pe
->rid
& 0xff00) >> 8,
79 PCI_SLOT(pe
->rid
), PCI_FUNC(pe
->rid
));
80 #endif /* CONFIG_PCI_IOV*/
82 printk("%spci %s: [PE# %.2x] %pV",
83 level
, pfix
, pe
->pe_number
, &vaf
);
88 static bool pnv_iommu_bypass_disabled __read_mostly
;
89 static bool pci_reset_phbs __read_mostly
;
91 static int __init
iommu_setup(char *str
)
97 if (!strncmp(str
, "nobypass", 8)) {
98 pnv_iommu_bypass_disabled
= true;
99 pr_info("PowerNV: IOMMU bypass window disabled.\n");
102 str
+= strcspn(str
, ",");
109 early_param("iommu", iommu_setup
);
111 static int __init
pci_reset_phbs_setup(char *str
)
113 pci_reset_phbs
= true;
117 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup
);
119 static inline bool pnv_pci_is_m64(struct pnv_phb
*phb
, struct resource
*r
)
122 * WARNING: We cannot rely on the resource flags. The Linux PCI
123 * allocation code sometimes decides to put a 64-bit prefetchable
124 * BAR in the 32-bit window, so we have to compare the addresses.
126 * For simplicity we only test resource start.
128 return (r
->start
>= phb
->ioda
.m64_base
&&
129 r
->start
< (phb
->ioda
.m64_base
+ phb
->ioda
.m64_size
));
132 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags
)
134 unsigned long flags
= (IORESOURCE_MEM_64
| IORESOURCE_PREFETCH
);
136 return (resource_flags
& flags
) == flags
;
139 static struct pnv_ioda_pe
*pnv_ioda_init_pe(struct pnv_phb
*phb
, int pe_no
)
143 phb
->ioda
.pe_array
[pe_no
].phb
= phb
;
144 phb
->ioda
.pe_array
[pe_no
].pe_number
= pe_no
;
147 * Clear the PE frozen state as it might be put into frozen state
148 * in the last PCI remove path. It's not harmful to do so when the
149 * PE is already in unfrozen state.
151 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
, pe_no
,
152 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
153 if (rc
!= OPAL_SUCCESS
&& rc
!= OPAL_UNSUPPORTED
)
154 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
155 __func__
, rc
, phb
->hose
->global_number
, pe_no
);
157 return &phb
->ioda
.pe_array
[pe_no
];
160 static void pnv_ioda_reserve_pe(struct pnv_phb
*phb
, int pe_no
)
162 if (!(pe_no
>= 0 && pe_no
< phb
->ioda
.total_pe_num
)) {
163 pr_warn("%s: Invalid PE %x on PHB#%x\n",
164 __func__
, pe_no
, phb
->hose
->global_number
);
168 if (test_and_set_bit(pe_no
, phb
->ioda
.pe_alloc
))
169 pr_debug("%s: PE %x was reserved on PHB#%x\n",
170 __func__
, pe_no
, phb
->hose
->global_number
);
172 pnv_ioda_init_pe(phb
, pe_no
);
175 static struct pnv_ioda_pe
*pnv_ioda_alloc_pe(struct pnv_phb
*phb
)
179 for (pe
= phb
->ioda
.total_pe_num
- 1; pe
>= 0; pe
--) {
180 if (!test_and_set_bit(pe
, phb
->ioda
.pe_alloc
))
181 return pnv_ioda_init_pe(phb
, pe
);
187 static void pnv_ioda_free_pe(struct pnv_ioda_pe
*pe
)
189 struct pnv_phb
*phb
= pe
->phb
;
190 unsigned int pe_num
= pe
->pe_number
;
193 WARN_ON(pe
->npucomp
); /* NPUs are not supposed to be freed */
195 memset(pe
, 0, sizeof(struct pnv_ioda_pe
));
196 clear_bit(pe_num
, phb
->ioda
.pe_alloc
);
199 /* The default M64 BAR is shared by all PEs */
200 static int pnv_ioda2_init_m64(struct pnv_phb
*phb
)
206 /* Configure the default M64 BAR */
207 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
208 OPAL_M64_WINDOW_TYPE
,
209 phb
->ioda
.m64_bar_idx
,
213 if (rc
!= OPAL_SUCCESS
) {
214 desc
= "configuring";
218 /* Enable the default M64 BAR */
219 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
220 OPAL_M64_WINDOW_TYPE
,
221 phb
->ioda
.m64_bar_idx
,
222 OPAL_ENABLE_M64_SPLIT
);
223 if (rc
!= OPAL_SUCCESS
) {
229 * Exclude the segments for reserved and root bus PE, which
230 * are first or last two PEs.
232 r
= &phb
->hose
->mem_resources
[1];
233 if (phb
->ioda
.reserved_pe_idx
== 0)
234 r
->start
+= (2 * phb
->ioda
.m64_segsize
);
235 else if (phb
->ioda
.reserved_pe_idx
== (phb
->ioda
.total_pe_num
- 1))
236 r
->end
-= (2 * phb
->ioda
.m64_segsize
);
238 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
239 phb
->ioda
.reserved_pe_idx
);
244 pr_warn(" Failure %lld %s M64 BAR#%d\n",
245 rc
, desc
, phb
->ioda
.m64_bar_idx
);
246 opal_pci_phb_mmio_enable(phb
->opal_id
,
247 OPAL_M64_WINDOW_TYPE
,
248 phb
->ioda
.m64_bar_idx
,
253 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev
*pdev
,
254 unsigned long *pe_bitmap
)
256 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
257 struct pnv_phb
*phb
= hose
->private_data
;
259 resource_size_t base
, sgsz
, start
, end
;
262 base
= phb
->ioda
.m64_base
;
263 sgsz
= phb
->ioda
.m64_segsize
;
264 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
265 r
= &pdev
->resource
[i
];
266 if (!r
->parent
|| !pnv_pci_is_m64(phb
, r
))
269 start
= _ALIGN_DOWN(r
->start
- base
, sgsz
);
270 end
= _ALIGN_UP(r
->end
- base
, sgsz
);
271 for (segno
= start
/ sgsz
; segno
< end
/ sgsz
; segno
++) {
273 set_bit(segno
, pe_bitmap
);
275 pnv_ioda_reserve_pe(phb
, segno
);
280 static int pnv_ioda1_init_m64(struct pnv_phb
*phb
)
286 * There are 16 M64 BARs, each of which has 8 segments. So
287 * there are as many M64 segments as the maximum number of
290 for (index
= 0; index
< PNV_IODA1_M64_NUM
; index
++) {
291 unsigned long base
, segsz
= phb
->ioda
.m64_segsize
;
294 base
= phb
->ioda
.m64_base
+
295 index
* PNV_IODA1_M64_SEGS
* segsz
;
296 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
297 OPAL_M64_WINDOW_TYPE
, index
, base
, 0,
298 PNV_IODA1_M64_SEGS
* segsz
);
299 if (rc
!= OPAL_SUCCESS
) {
300 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
301 rc
, phb
->hose
->global_number
, index
);
305 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
306 OPAL_M64_WINDOW_TYPE
, index
,
307 OPAL_ENABLE_M64_SPLIT
);
308 if (rc
!= OPAL_SUCCESS
) {
309 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
310 rc
, phb
->hose
->global_number
, index
);
316 * Exclude the segments for reserved and root bus PE, which
317 * are first or last two PEs.
319 r
= &phb
->hose
->mem_resources
[1];
320 if (phb
->ioda
.reserved_pe_idx
== 0)
321 r
->start
+= (2 * phb
->ioda
.m64_segsize
);
322 else if (phb
->ioda
.reserved_pe_idx
== (phb
->ioda
.total_pe_num
- 1))
323 r
->end
-= (2 * phb
->ioda
.m64_segsize
);
325 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
326 phb
->ioda
.reserved_pe_idx
, phb
->hose
->global_number
);
331 for ( ; index
>= 0; index
--)
332 opal_pci_phb_mmio_enable(phb
->opal_id
,
333 OPAL_M64_WINDOW_TYPE
, index
, OPAL_DISABLE_M64
);
338 static void pnv_ioda_reserve_m64_pe(struct pci_bus
*bus
,
339 unsigned long *pe_bitmap
,
342 struct pci_dev
*pdev
;
344 list_for_each_entry(pdev
, &bus
->devices
, bus_list
) {
345 pnv_ioda_reserve_dev_m64_pe(pdev
, pe_bitmap
);
347 if (all
&& pdev
->subordinate
)
348 pnv_ioda_reserve_m64_pe(pdev
->subordinate
,
353 static struct pnv_ioda_pe
*pnv_ioda_pick_m64_pe(struct pci_bus
*bus
, bool all
)
355 struct pci_controller
*hose
= pci_bus_to_host(bus
);
356 struct pnv_phb
*phb
= hose
->private_data
;
357 struct pnv_ioda_pe
*master_pe
, *pe
;
358 unsigned long size
, *pe_alloc
;
361 /* Root bus shouldn't use M64 */
362 if (pci_is_root_bus(bus
))
365 /* Allocate bitmap */
366 size
= _ALIGN_UP(phb
->ioda
.total_pe_num
/ 8, sizeof(unsigned long));
367 pe_alloc
= kzalloc(size
, GFP_KERNEL
);
369 pr_warn("%s: Out of memory !\n",
374 /* Figure out reserved PE numbers by the PE */
375 pnv_ioda_reserve_m64_pe(bus
, pe_alloc
, all
);
378 * the current bus might not own M64 window and that's all
379 * contributed by its child buses. For the case, we needn't
380 * pick M64 dependent PE#.
382 if (bitmap_empty(pe_alloc
, phb
->ioda
.total_pe_num
)) {
388 * Figure out the master PE and put all slave PEs to master
389 * PE's list to form compound PE.
393 while ((i
= find_next_bit(pe_alloc
, phb
->ioda
.total_pe_num
, i
+ 1)) <
394 phb
->ioda
.total_pe_num
) {
395 pe
= &phb
->ioda
.pe_array
[i
];
397 phb
->ioda
.m64_segmap
[pe
->pe_number
] = pe
->pe_number
;
399 pe
->flags
|= PNV_IODA_PE_MASTER
;
400 INIT_LIST_HEAD(&pe
->slaves
);
403 pe
->flags
|= PNV_IODA_PE_SLAVE
;
404 pe
->master
= master_pe
;
405 list_add_tail(&pe
->list
, &master_pe
->slaves
);
409 * P7IOC supports M64DT, which helps mapping M64 segment
410 * to one particular PE#. However, PHB3 has fixed mapping
411 * between M64 segment and PE#. In order to have same logic
412 * for P7IOC and PHB3, we enforce fixed mapping between M64
413 * segment and PE# on P7IOC.
415 if (phb
->type
== PNV_PHB_IODA1
) {
418 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
419 pe
->pe_number
, OPAL_M64_WINDOW_TYPE
,
420 pe
->pe_number
/ PNV_IODA1_M64_SEGS
,
421 pe
->pe_number
% PNV_IODA1_M64_SEGS
);
422 if (rc
!= OPAL_SUCCESS
)
423 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
424 __func__
, rc
, phb
->hose
->global_number
,
433 static void __init
pnv_ioda_parse_m64_window(struct pnv_phb
*phb
)
435 struct pci_controller
*hose
= phb
->hose
;
436 struct device_node
*dn
= hose
->dn
;
437 struct resource
*res
;
442 if (phb
->type
!= PNV_PHB_IODA1
&& phb
->type
!= PNV_PHB_IODA2
) {
443 pr_info(" Not support M64 window\n");
447 if (!firmware_has_feature(FW_FEATURE_OPAL
)) {
448 pr_info(" Firmware too old to support M64 window\n");
452 r
= of_get_property(dn
, "ibm,opal-m64-window", NULL
);
454 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
460 * Find the available M64 BAR range and pickup the last one for
461 * covering the whole 64-bits space. We support only one range.
463 if (of_property_read_u32_array(dn
, "ibm,opal-available-m64-ranges",
465 /* In absence of the property, assume 0..15 */
469 /* We only support 64 bits in our allocator */
470 if (m64_range
[1] > 63) {
471 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
472 __func__
, m64_range
[1], phb
->hose
->global_number
);
475 /* Empty range, no m64 */
476 if (m64_range
[1] <= m64_range
[0]) {
477 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
478 __func__
, phb
->hose
->global_number
);
482 /* Configure M64 informations */
483 res
= &hose
->mem_resources
[1];
484 res
->name
= dn
->full_name
;
485 res
->start
= of_translate_address(dn
, r
+ 2);
486 res
->end
= res
->start
+ of_read_number(r
+ 4, 2) - 1;
487 res
->flags
= (IORESOURCE_MEM
| IORESOURCE_MEM_64
| IORESOURCE_PREFETCH
);
488 pci_addr
= of_read_number(r
, 2);
489 hose
->mem_offset
[1] = res
->start
- pci_addr
;
491 phb
->ioda
.m64_size
= resource_size(res
);
492 phb
->ioda
.m64_segsize
= phb
->ioda
.m64_size
/ phb
->ioda
.total_pe_num
;
493 phb
->ioda
.m64_base
= pci_addr
;
495 /* This lines up nicely with the display from processing OF ranges */
496 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
497 res
->start
, res
->end
, pci_addr
, m64_range
[0],
498 m64_range
[0] + m64_range
[1] - 1);
500 /* Mark all M64 used up by default */
501 phb
->ioda
.m64_bar_alloc
= (unsigned long)-1;
503 /* Use last M64 BAR to cover M64 window */
505 phb
->ioda
.m64_bar_idx
= m64_range
[0] + m64_range
[1];
507 pr_info(" Using M64 #%d as default window\n", phb
->ioda
.m64_bar_idx
);
509 /* Mark remaining ones free */
510 for (i
= m64_range
[0]; i
< m64_range
[1]; i
++)
511 clear_bit(i
, &phb
->ioda
.m64_bar_alloc
);
514 * Setup init functions for M64 based on IODA version, IODA3 uses
517 if (phb
->type
== PNV_PHB_IODA1
)
518 phb
->init_m64
= pnv_ioda1_init_m64
;
520 phb
->init_m64
= pnv_ioda2_init_m64
;
523 static void pnv_ioda_freeze_pe(struct pnv_phb
*phb
, int pe_no
)
525 struct pnv_ioda_pe
*pe
= &phb
->ioda
.pe_array
[pe_no
];
526 struct pnv_ioda_pe
*slave
;
529 /* Fetch master PE */
530 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
532 if (WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
)))
535 pe_no
= pe
->pe_number
;
538 /* Freeze master PE */
539 rc
= opal_pci_eeh_freeze_set(phb
->opal_id
,
541 OPAL_EEH_ACTION_SET_FREEZE_ALL
);
542 if (rc
!= OPAL_SUCCESS
) {
543 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
544 __func__
, rc
, phb
->hose
->global_number
, pe_no
);
548 /* Freeze slave PEs */
549 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
552 list_for_each_entry(slave
, &pe
->slaves
, list
) {
553 rc
= opal_pci_eeh_freeze_set(phb
->opal_id
,
555 OPAL_EEH_ACTION_SET_FREEZE_ALL
);
556 if (rc
!= OPAL_SUCCESS
)
557 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
558 __func__
, rc
, phb
->hose
->global_number
,
563 static int pnv_ioda_unfreeze_pe(struct pnv_phb
*phb
, int pe_no
, int opt
)
565 struct pnv_ioda_pe
*pe
, *slave
;
569 pe
= &phb
->ioda
.pe_array
[pe_no
];
570 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
572 WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
));
573 pe_no
= pe
->pe_number
;
576 /* Clear frozen state for master PE */
577 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
, pe_no
, opt
);
578 if (rc
!= OPAL_SUCCESS
) {
579 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
580 __func__
, rc
, opt
, phb
->hose
->global_number
, pe_no
);
584 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
587 /* Clear frozen state for slave PEs */
588 list_for_each_entry(slave
, &pe
->slaves
, list
) {
589 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
,
592 if (rc
!= OPAL_SUCCESS
) {
593 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
594 __func__
, rc
, opt
, phb
->hose
->global_number
,
603 static int pnv_ioda_get_pe_state(struct pnv_phb
*phb
, int pe_no
)
605 struct pnv_ioda_pe
*slave
, *pe
;
606 u8 fstate
= 0, state
;
610 /* Sanity check on PE number */
611 if (pe_no
< 0 || pe_no
>= phb
->ioda
.total_pe_num
)
612 return OPAL_EEH_STOPPED_PERM_UNAVAIL
;
615 * Fetch the master PE and the PE instance might be
616 * not initialized yet.
618 pe
= &phb
->ioda
.pe_array
[pe_no
];
619 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
621 WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
));
622 pe_no
= pe
->pe_number
;
625 /* Check the master PE */
626 rc
= opal_pci_eeh_freeze_status(phb
->opal_id
, pe_no
,
627 &state
, &pcierr
, NULL
);
628 if (rc
!= OPAL_SUCCESS
) {
629 pr_warn("%s: Failure %lld getting "
630 "PHB#%x-PE#%x state\n",
632 phb
->hose
->global_number
, pe_no
);
633 return OPAL_EEH_STOPPED_TEMP_UNAVAIL
;
636 /* Check the slave PE */
637 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
640 list_for_each_entry(slave
, &pe
->slaves
, list
) {
641 rc
= opal_pci_eeh_freeze_status(phb
->opal_id
,
646 if (rc
!= OPAL_SUCCESS
) {
647 pr_warn("%s: Failure %lld getting "
648 "PHB#%x-PE#%x state\n",
650 phb
->hose
->global_number
, slave
->pe_number
);
651 return OPAL_EEH_STOPPED_TEMP_UNAVAIL
;
655 * Override the result based on the ascending
665 struct pnv_ioda_pe
*pnv_ioda_get_pe(struct pci_dev
*dev
)
667 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
668 struct pnv_phb
*phb
= hose
->private_data
;
669 struct pci_dn
*pdn
= pci_get_pdn(dev
);
673 if (pdn
->pe_number
== IODA_INVALID_PE
)
675 return &phb
->ioda
.pe_array
[pdn
->pe_number
];
678 static int pnv_ioda_set_one_peltv(struct pnv_phb
*phb
,
679 struct pnv_ioda_pe
*parent
,
680 struct pnv_ioda_pe
*child
,
683 const char *desc
= is_add
? "adding" : "removing";
684 uint8_t op
= is_add
? OPAL_ADD_PE_TO_DOMAIN
:
685 OPAL_REMOVE_PE_FROM_DOMAIN
;
686 struct pnv_ioda_pe
*slave
;
689 /* Parent PE affects child PE */
690 rc
= opal_pci_set_peltv(phb
->opal_id
, parent
->pe_number
,
691 child
->pe_number
, op
);
692 if (rc
!= OPAL_SUCCESS
) {
693 pe_warn(child
, "OPAL error %ld %s to parent PELTV\n",
698 if (!(child
->flags
& PNV_IODA_PE_MASTER
))
701 /* Compound case: parent PE affects slave PEs */
702 list_for_each_entry(slave
, &child
->slaves
, list
) {
703 rc
= opal_pci_set_peltv(phb
->opal_id
, parent
->pe_number
,
704 slave
->pe_number
, op
);
705 if (rc
!= OPAL_SUCCESS
) {
706 pe_warn(slave
, "OPAL error %ld %s to parent PELTV\n",
715 static int pnv_ioda_set_peltv(struct pnv_phb
*phb
,
716 struct pnv_ioda_pe
*pe
,
719 struct pnv_ioda_pe
*slave
;
720 struct pci_dev
*pdev
= NULL
;
724 * Clear PE frozen state. If it's master PE, we need
725 * clear slave PE frozen state as well.
728 opal_pci_eeh_freeze_clear(phb
->opal_id
, pe
->pe_number
,
729 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
730 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
731 list_for_each_entry(slave
, &pe
->slaves
, list
)
732 opal_pci_eeh_freeze_clear(phb
->opal_id
,
734 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
739 * Associate PE in PELT. We need add the PE into the
740 * corresponding PELT-V as well. Otherwise, the error
741 * originated from the PE might contribute to other
744 ret
= pnv_ioda_set_one_peltv(phb
, pe
, pe
, is_add
);
748 /* For compound PEs, any one affects all of them */
749 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
750 list_for_each_entry(slave
, &pe
->slaves
, list
) {
751 ret
= pnv_ioda_set_one_peltv(phb
, slave
, pe
, is_add
);
757 if (pe
->flags
& (PNV_IODA_PE_BUS_ALL
| PNV_IODA_PE_BUS
))
758 pdev
= pe
->pbus
->self
;
759 else if (pe
->flags
& PNV_IODA_PE_DEV
)
760 pdev
= pe
->pdev
->bus
->self
;
761 #ifdef CONFIG_PCI_IOV
762 else if (pe
->flags
& PNV_IODA_PE_VF
)
763 pdev
= pe
->parent_dev
;
764 #endif /* CONFIG_PCI_IOV */
766 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
767 struct pnv_ioda_pe
*parent
;
769 if (pdn
&& pdn
->pe_number
!= IODA_INVALID_PE
) {
770 parent
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
771 ret
= pnv_ioda_set_one_peltv(phb
, parent
, pe
, is_add
);
776 pdev
= pdev
->bus
->self
;
782 static int pnv_ioda_deconfigure_pe(struct pnv_phb
*phb
, struct pnv_ioda_pe
*pe
)
784 struct pci_dev
*parent
;
785 uint8_t bcomp
, dcomp
, fcomp
;
789 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
793 dcomp
= OPAL_IGNORE_RID_DEVICE_NUMBER
;
794 fcomp
= OPAL_IGNORE_RID_FUNCTION_NUMBER
;
795 parent
= pe
->pbus
->self
;
796 if (pe
->flags
& PNV_IODA_PE_BUS_ALL
)
797 count
= pe
->pbus
->busn_res
.end
- pe
->pbus
->busn_res
.start
+ 1;
802 case 1: bcomp
= OpalPciBusAll
; break;
803 case 2: bcomp
= OpalPciBus7Bits
; break;
804 case 4: bcomp
= OpalPciBus6Bits
; break;
805 case 8: bcomp
= OpalPciBus5Bits
; break;
806 case 16: bcomp
= OpalPciBus4Bits
; break;
807 case 32: bcomp
= OpalPciBus3Bits
; break;
809 dev_err(&pe
->pbus
->dev
, "Number of subordinate buses %d unsupported\n",
811 /* Do an exact match only */
812 bcomp
= OpalPciBusAll
;
814 rid_end
= pe
->rid
+ (count
<< 8);
816 #ifdef CONFIG_PCI_IOV
817 if (pe
->flags
& PNV_IODA_PE_VF
)
818 parent
= pe
->parent_dev
;
821 parent
= pe
->pdev
->bus
->self
;
822 bcomp
= OpalPciBusAll
;
823 dcomp
= OPAL_COMPARE_RID_DEVICE_NUMBER
;
824 fcomp
= OPAL_COMPARE_RID_FUNCTION_NUMBER
;
825 rid_end
= pe
->rid
+ 1;
828 /* Clear the reverse map */
829 for (rid
= pe
->rid
; rid
< rid_end
; rid
++)
830 phb
->ioda
.pe_rmap
[rid
] = IODA_INVALID_PE
;
832 /* Release from all parents PELT-V */
834 struct pci_dn
*pdn
= pci_get_pdn(parent
);
835 if (pdn
&& pdn
->pe_number
!= IODA_INVALID_PE
) {
836 rc
= opal_pci_set_peltv(phb
->opal_id
, pdn
->pe_number
,
837 pe
->pe_number
, OPAL_REMOVE_PE_FROM_DOMAIN
);
838 /* XXX What to do in case of error ? */
840 parent
= parent
->bus
->self
;
843 opal_pci_eeh_freeze_clear(phb
->opal_id
, pe
->pe_number
,
844 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
846 /* Disassociate PE in PELT */
847 rc
= opal_pci_set_peltv(phb
->opal_id
, pe
->pe_number
,
848 pe
->pe_number
, OPAL_REMOVE_PE_FROM_DOMAIN
);
850 pe_warn(pe
, "OPAL error %lld remove self from PELTV\n", rc
);
851 rc
= opal_pci_set_pe(phb
->opal_id
, pe
->pe_number
, pe
->rid
,
852 bcomp
, dcomp
, fcomp
, OPAL_UNMAP_PE
);
854 pe_err(pe
, "OPAL error %lld trying to setup PELT table\n", rc
);
858 #ifdef CONFIG_PCI_IOV
859 pe
->parent_dev
= NULL
;
865 static int pnv_ioda_configure_pe(struct pnv_phb
*phb
, struct pnv_ioda_pe
*pe
)
867 struct pci_dev
*parent
;
868 uint8_t bcomp
, dcomp
, fcomp
;
869 long rc
, rid_end
, rid
;
871 /* Bus validation ? */
875 dcomp
= OPAL_IGNORE_RID_DEVICE_NUMBER
;
876 fcomp
= OPAL_IGNORE_RID_FUNCTION_NUMBER
;
877 parent
= pe
->pbus
->self
;
878 if (pe
->flags
& PNV_IODA_PE_BUS_ALL
)
879 count
= pe
->pbus
->busn_res
.end
- pe
->pbus
->busn_res
.start
+ 1;
884 case 1: bcomp
= OpalPciBusAll
; break;
885 case 2: bcomp
= OpalPciBus7Bits
; break;
886 case 4: bcomp
= OpalPciBus6Bits
; break;
887 case 8: bcomp
= OpalPciBus5Bits
; break;
888 case 16: bcomp
= OpalPciBus4Bits
; break;
889 case 32: bcomp
= OpalPciBus3Bits
; break;
891 dev_err(&pe
->pbus
->dev
, "Number of subordinate buses %d unsupported\n",
893 /* Do an exact match only */
894 bcomp
= OpalPciBusAll
;
896 rid_end
= pe
->rid
+ (count
<< 8);
898 #ifdef CONFIG_PCI_IOV
899 if (pe
->flags
& PNV_IODA_PE_VF
)
900 parent
= pe
->parent_dev
;
902 #endif /* CONFIG_PCI_IOV */
903 parent
= pe
->pdev
->bus
->self
;
904 bcomp
= OpalPciBusAll
;
905 dcomp
= OPAL_COMPARE_RID_DEVICE_NUMBER
;
906 fcomp
= OPAL_COMPARE_RID_FUNCTION_NUMBER
;
907 rid_end
= pe
->rid
+ 1;
911 * Associate PE in PELT. We need add the PE into the
912 * corresponding PELT-V as well. Otherwise, the error
913 * originated from the PE might contribute to other
916 rc
= opal_pci_set_pe(phb
->opal_id
, pe
->pe_number
, pe
->rid
,
917 bcomp
, dcomp
, fcomp
, OPAL_MAP_PE
);
919 pe_err(pe
, "OPAL error %ld trying to setup PELT table\n", rc
);
924 * Configure PELTV. NPUs don't have a PELTV table so skip
925 * configuration on them.
927 if (phb
->type
!= PNV_PHB_NPU_NVLINK
&& phb
->type
!= PNV_PHB_NPU_OCAPI
)
928 pnv_ioda_set_peltv(phb
, pe
, true);
930 /* Setup reverse map */
931 for (rid
= pe
->rid
; rid
< rid_end
; rid
++)
932 phb
->ioda
.pe_rmap
[rid
] = pe
->pe_number
;
934 /* Setup one MVTs on IODA1 */
935 if (phb
->type
!= PNV_PHB_IODA1
) {
940 pe
->mve_number
= pe
->pe_number
;
941 rc
= opal_pci_set_mve(phb
->opal_id
, pe
->mve_number
, pe
->pe_number
);
942 if (rc
!= OPAL_SUCCESS
) {
943 pe_err(pe
, "OPAL error %ld setting up MVE %x\n",
947 rc
= opal_pci_set_mve_enable(phb
->opal_id
,
948 pe
->mve_number
, OPAL_ENABLE_MVE
);
950 pe_err(pe
, "OPAL error %ld enabling MVE %x\n",
960 #ifdef CONFIG_PCI_IOV
961 static int pnv_pci_vf_resource_shift(struct pci_dev
*dev
, int offset
)
963 struct pci_dn
*pdn
= pci_get_pdn(dev
);
965 struct resource
*res
, res2
;
966 resource_size_t size
;
973 * "offset" is in VFs. The M64 windows are sized so that when they
974 * are segmented, each segment is the same size as the IOV BAR.
975 * Each segment is in a separate PE, and the high order bits of the
976 * address are the PE number. Therefore, each VF's BAR is in a
977 * separate PE, and changing the IOV BAR start address changes the
978 * range of PEs the VFs are in.
980 num_vfs
= pdn
->num_vfs
;
981 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
982 res
= &dev
->resource
[i
+ PCI_IOV_RESOURCES
];
983 if (!res
->flags
|| !res
->parent
)
987 * The actual IOV BAR range is determined by the start address
988 * and the actual size for num_vfs VFs BAR. This check is to
989 * make sure that after shifting, the range will not overlap
990 * with another device.
992 size
= pci_iov_resource_size(dev
, i
+ PCI_IOV_RESOURCES
);
993 res2
.flags
= res
->flags
;
994 res2
.start
= res
->start
+ (size
* offset
);
995 res2
.end
= res2
.start
+ (size
* num_vfs
) - 1;
997 if (res2
.end
> res
->end
) {
998 dev_err(&dev
->dev
, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
999 i
, &res2
, res
, num_vfs
, offset
);
1005 * Since M64 BAR shares segments among all possible 256 PEs,
1006 * we have to shift the beginning of PF IOV BAR to make it start from
1007 * the segment which belongs to the PE number assigned to the first VF.
1008 * This creates a "hole" in the /proc/iomem which could be used for
1009 * allocating other resources so we reserve this area below and
1010 * release when IOV is released.
1012 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
1013 res
= &dev
->resource
[i
+ PCI_IOV_RESOURCES
];
1014 if (!res
->flags
|| !res
->parent
)
1017 size
= pci_iov_resource_size(dev
, i
+ PCI_IOV_RESOURCES
);
1019 res
->start
+= size
* offset
;
1021 dev_info(&dev
->dev
, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1022 i
, &res2
, res
, (offset
> 0) ? "En" : "Dis",
1026 devm_release_resource(&dev
->dev
, &pdn
->holes
[i
]);
1027 memset(&pdn
->holes
[i
], 0, sizeof(pdn
->holes
[i
]));
1030 pci_update_resource(dev
, i
+ PCI_IOV_RESOURCES
);
1033 pdn
->holes
[i
].start
= res2
.start
;
1034 pdn
->holes
[i
].end
= res2
.start
+ size
* offset
- 1;
1035 pdn
->holes
[i
].flags
= IORESOURCE_BUS
;
1036 pdn
->holes
[i
].name
= "pnv_iov_reserved";
1037 devm_request_resource(&dev
->dev
, res
->parent
,
1043 #endif /* CONFIG_PCI_IOV */
1045 static struct pnv_ioda_pe
*pnv_ioda_setup_dev_PE(struct pci_dev
*dev
)
1047 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1048 struct pnv_phb
*phb
= hose
->private_data
;
1049 struct pci_dn
*pdn
= pci_get_pdn(dev
);
1050 struct pnv_ioda_pe
*pe
;
1053 pr_err("%s: Device tree node not associated properly\n",
1057 if (pdn
->pe_number
!= IODA_INVALID_PE
)
1060 pe
= pnv_ioda_alloc_pe(phb
);
1062 pr_warn("%s: Not enough PE# available, disabling device\n",
1067 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1068 * pointer in the PE data structure, both should be destroyed at the
1069 * same time. However, this needs to be looked at more closely again
1070 * once we actually start removing things (Hotplug, SR-IOV, ...)
1072 * At some point we want to remove the PDN completely anyways
1075 pdn
->pe_number
= pe
->pe_number
;
1076 pe
->flags
= PNV_IODA_PE_DEV
;
1079 pe
->mve_number
= -1;
1080 pe
->rid
= dev
->bus
->number
<< 8 | pdn
->devfn
;
1082 pe_info(pe
, "Associated device to PE\n");
1084 if (pnv_ioda_configure_pe(phb
, pe
)) {
1085 /* XXX What do we do here ? */
1086 pnv_ioda_free_pe(pe
);
1087 pdn
->pe_number
= IODA_INVALID_PE
;
1093 /* Put PE to the list */
1094 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1099 static void pnv_ioda_setup_same_PE(struct pci_bus
*bus
, struct pnv_ioda_pe
*pe
)
1101 struct pci_dev
*dev
;
1103 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1104 struct pci_dn
*pdn
= pci_get_pdn(dev
);
1107 pr_warn("%s: No device node associated with device !\n",
1113 * In partial hotplug case, the PCI device might be still
1114 * associated with the PE and needn't attach it to the PE
1117 if (pdn
->pe_number
!= IODA_INVALID_PE
)
1121 pdn
->pe_number
= pe
->pe_number
;
1122 if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && dev
->subordinate
)
1123 pnv_ioda_setup_same_PE(dev
->subordinate
, pe
);
1128 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1129 * single PCI bus. Another one that contains the primary PCI bus and its
1130 * subordinate PCI devices and buses. The second type of PE is normally
1131 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1133 static struct pnv_ioda_pe
*pnv_ioda_setup_bus_PE(struct pci_bus
*bus
, bool all
)
1135 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1136 struct pnv_phb
*phb
= hose
->private_data
;
1137 struct pnv_ioda_pe
*pe
= NULL
;
1138 unsigned int pe_num
;
1141 * In partial hotplug case, the PE instance might be still alive.
1142 * We should reuse it instead of allocating a new one.
1144 pe_num
= phb
->ioda
.pe_rmap
[bus
->number
<< 8];
1145 if (pe_num
!= IODA_INVALID_PE
) {
1146 pe
= &phb
->ioda
.pe_array
[pe_num
];
1147 pnv_ioda_setup_same_PE(bus
, pe
);
1151 /* PE number for root bus should have been reserved */
1152 if (pci_is_root_bus(bus
) &&
1153 phb
->ioda
.root_pe_idx
!= IODA_INVALID_PE
)
1154 pe
= &phb
->ioda
.pe_array
[phb
->ioda
.root_pe_idx
];
1156 /* Check if PE is determined by M64 */
1158 pe
= pnv_ioda_pick_m64_pe(bus
, all
);
1160 /* The PE number isn't pinned by M64 */
1162 pe
= pnv_ioda_alloc_pe(phb
);
1165 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1166 __func__
, pci_domain_nr(bus
), bus
->number
);
1170 pe
->flags
|= (all
? PNV_IODA_PE_BUS_ALL
: PNV_IODA_PE_BUS
);
1173 pe
->mve_number
= -1;
1174 pe
->rid
= bus
->busn_res
.start
<< 8;
1177 pe_info(pe
, "Secondary bus %pad..%pad associated with PE#%x\n",
1178 &bus
->busn_res
.start
, &bus
->busn_res
.end
,
1181 pe_info(pe
, "Secondary bus %pad associated with PE#%x\n",
1182 &bus
->busn_res
.start
, pe
->pe_number
);
1184 if (pnv_ioda_configure_pe(phb
, pe
)) {
1185 /* XXX What do we do here ? */
1186 pnv_ioda_free_pe(pe
);
1191 /* Associate it with all child devices */
1192 pnv_ioda_setup_same_PE(bus
, pe
);
1194 /* Put PE to the list */
1195 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1200 static struct pnv_ioda_pe
*pnv_ioda_setup_npu_PE(struct pci_dev
*npu_pdev
)
1202 int pe_num
, found_pe
= false, rc
;
1204 struct pnv_ioda_pe
*pe
;
1205 struct pci_dev
*gpu_pdev
;
1206 struct pci_dn
*npu_pdn
;
1207 struct pci_controller
*hose
= pci_bus_to_host(npu_pdev
->bus
);
1208 struct pnv_phb
*phb
= hose
->private_data
;
1211 * Due to a hardware errata PE#0 on the NPU is reserved for
1212 * error handling. This means we only have three PEs remaining
1213 * which need to be assigned to four links, implying some
1214 * links must share PEs.
1216 * To achieve this we assign PEs such that NPUs linking the
1217 * same GPU get assigned the same PE.
1219 gpu_pdev
= pnv_pci_get_gpu_dev(npu_pdev
);
1220 for (pe_num
= 0; pe_num
< phb
->ioda
.total_pe_num
; pe_num
++) {
1221 pe
= &phb
->ioda
.pe_array
[pe_num
];
1225 if (pnv_pci_get_gpu_dev(pe
->pdev
) == gpu_pdev
) {
1227 * This device has the same peer GPU so should
1228 * be assigned the same PE as the existing
1231 dev_info(&npu_pdev
->dev
,
1232 "Associating to existing PE %x\n", pe_num
);
1233 pci_dev_get(npu_pdev
);
1234 npu_pdn
= pci_get_pdn(npu_pdev
);
1235 rid
= npu_pdev
->bus
->number
<< 8 | npu_pdn
->devfn
;
1236 npu_pdn
->pe_number
= pe_num
;
1237 phb
->ioda
.pe_rmap
[rid
] = pe
->pe_number
;
1239 /* Map the PE to this link */
1240 rc
= opal_pci_set_pe(phb
->opal_id
, pe_num
, rid
,
1242 OPAL_COMPARE_RID_DEVICE_NUMBER
,
1243 OPAL_COMPARE_RID_FUNCTION_NUMBER
,
1245 WARN_ON(rc
!= OPAL_SUCCESS
);
1253 * Could not find an existing PE so allocate a new
1256 return pnv_ioda_setup_dev_PE(npu_pdev
);
1261 static void pnv_ioda_setup_npu_PEs(struct pci_bus
*bus
)
1263 struct pci_dev
*pdev
;
1265 list_for_each_entry(pdev
, &bus
->devices
, bus_list
)
1266 pnv_ioda_setup_npu_PE(pdev
);
1269 static void pnv_pci_ioda_setup_PEs(void)
1271 struct pci_controller
*hose
;
1272 struct pnv_phb
*phb
;
1273 struct pci_bus
*bus
;
1274 struct pci_dev
*pdev
;
1275 struct pnv_ioda_pe
*pe
;
1277 list_for_each_entry(hose
, &hose_list
, list_node
) {
1278 phb
= hose
->private_data
;
1279 if (phb
->type
== PNV_PHB_NPU_NVLINK
) {
1280 /* PE#0 is needed for error reporting */
1281 pnv_ioda_reserve_pe(phb
, 0);
1282 pnv_ioda_setup_npu_PEs(hose
->bus
);
1283 if (phb
->model
== PNV_PHB_MODEL_NPU2
)
1284 WARN_ON_ONCE(pnv_npu2_init(hose
));
1286 if (phb
->type
== PNV_PHB_NPU_OCAPI
) {
1288 list_for_each_entry(pdev
, &bus
->devices
, bus_list
)
1289 pnv_ioda_setup_dev_PE(pdev
);
1292 list_for_each_entry(hose
, &hose_list
, list_node
) {
1293 phb
= hose
->private_data
;
1294 if (phb
->type
!= PNV_PHB_IODA2
)
1297 list_for_each_entry(pe
, &phb
->ioda
.pe_list
, list
)
1298 pnv_npu2_map_lpar(pe
, MSR_DR
| MSR_PR
| MSR_HV
);
1302 #ifdef CONFIG_PCI_IOV
1303 static int pnv_pci_vf_release_m64(struct pci_dev
*pdev
, u16 num_vfs
)
1305 struct pci_bus
*bus
;
1306 struct pci_controller
*hose
;
1307 struct pnv_phb
*phb
;
1313 hose
= pci_bus_to_host(bus
);
1314 phb
= hose
->private_data
;
1315 pdn
= pci_get_pdn(pdev
);
1317 if (pdn
->m64_single_mode
)
1322 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++)
1323 for (j
= 0; j
< m64_bars
; j
++) {
1324 if (pdn
->m64_map
[j
][i
] == IODA_INVALID_M64
)
1326 opal_pci_phb_mmio_enable(phb
->opal_id
,
1327 OPAL_M64_WINDOW_TYPE
, pdn
->m64_map
[j
][i
], 0);
1328 clear_bit(pdn
->m64_map
[j
][i
], &phb
->ioda
.m64_bar_alloc
);
1329 pdn
->m64_map
[j
][i
] = IODA_INVALID_M64
;
1332 kfree(pdn
->m64_map
);
1336 static int pnv_pci_vf_assign_m64(struct pci_dev
*pdev
, u16 num_vfs
)
1338 struct pci_bus
*bus
;
1339 struct pci_controller
*hose
;
1340 struct pnv_phb
*phb
;
1343 struct resource
*res
;
1347 resource_size_t size
, start
;
1352 hose
= pci_bus_to_host(bus
);
1353 phb
= hose
->private_data
;
1354 pdn
= pci_get_pdn(pdev
);
1355 total_vfs
= pci_sriov_get_totalvfs(pdev
);
1357 if (pdn
->m64_single_mode
)
1362 pdn
->m64_map
= kmalloc_array(m64_bars
,
1363 sizeof(*pdn
->m64_map
),
1367 /* Initialize the m64_map to IODA_INVALID_M64 */
1368 for (i
= 0; i
< m64_bars
; i
++)
1369 for (j
= 0; j
< PCI_SRIOV_NUM_BARS
; j
++)
1370 pdn
->m64_map
[i
][j
] = IODA_INVALID_M64
;
1373 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
1374 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
1375 if (!res
->flags
|| !res
->parent
)
1378 for (j
= 0; j
< m64_bars
; j
++) {
1380 win
= find_next_zero_bit(&phb
->ioda
.m64_bar_alloc
,
1381 phb
->ioda
.m64_bar_idx
+ 1, 0);
1383 if (win
>= phb
->ioda
.m64_bar_idx
+ 1)
1385 } while (test_and_set_bit(win
, &phb
->ioda
.m64_bar_alloc
));
1387 pdn
->m64_map
[j
][i
] = win
;
1389 if (pdn
->m64_single_mode
) {
1390 size
= pci_iov_resource_size(pdev
,
1391 PCI_IOV_RESOURCES
+ i
);
1392 start
= res
->start
+ size
* j
;
1394 size
= resource_size(res
);
1398 /* Map the M64 here */
1399 if (pdn
->m64_single_mode
) {
1400 pe_num
= pdn
->pe_num_map
[j
];
1401 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
1402 pe_num
, OPAL_M64_WINDOW_TYPE
,
1403 pdn
->m64_map
[j
][i
], 0);
1406 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
1407 OPAL_M64_WINDOW_TYPE
,
1414 if (rc
!= OPAL_SUCCESS
) {
1415 dev_err(&pdev
->dev
, "Failed to map M64 window #%d: %lld\n",
1420 if (pdn
->m64_single_mode
)
1421 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
1422 OPAL_M64_WINDOW_TYPE
, pdn
->m64_map
[j
][i
], 2);
1424 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
1425 OPAL_M64_WINDOW_TYPE
, pdn
->m64_map
[j
][i
], 1);
1427 if (rc
!= OPAL_SUCCESS
) {
1428 dev_err(&pdev
->dev
, "Failed to enable M64 window #%d: %llx\n",
1437 pnv_pci_vf_release_m64(pdev
, num_vfs
);
1441 static long pnv_pci_ioda2_unset_window(struct iommu_table_group
*table_group
,
1444 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev
*dev
, struct pnv_ioda_pe
*pe
)
1446 struct iommu_table
*tbl
;
1449 tbl
= pe
->table_group
.tables
[0];
1450 rc
= pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
1452 pe_warn(pe
, "OPAL error %lld release DMA window\n", rc
);
1454 pnv_pci_ioda2_set_bypass(pe
, false);
1455 if (pe
->table_group
.group
) {
1456 iommu_group_put(pe
->table_group
.group
);
1457 BUG_ON(pe
->table_group
.group
);
1459 iommu_tce_table_put(tbl
);
1462 static void pnv_ioda_release_vf_PE(struct pci_dev
*pdev
)
1464 struct pci_bus
*bus
;
1465 struct pci_controller
*hose
;
1466 struct pnv_phb
*phb
;
1467 struct pnv_ioda_pe
*pe
, *pe_n
;
1471 hose
= pci_bus_to_host(bus
);
1472 phb
= hose
->private_data
;
1473 pdn
= pci_get_pdn(pdev
);
1475 if (!pdev
->is_physfn
)
1478 list_for_each_entry_safe(pe
, pe_n
, &phb
->ioda
.pe_list
, list
) {
1479 if (pe
->parent_dev
!= pdev
)
1482 pnv_pci_ioda2_release_dma_pe(pdev
, pe
);
1484 /* Remove from list */
1485 mutex_lock(&phb
->ioda
.pe_list_mutex
);
1486 list_del(&pe
->list
);
1487 mutex_unlock(&phb
->ioda
.pe_list_mutex
);
1489 pnv_ioda_deconfigure_pe(phb
, pe
);
1491 pnv_ioda_free_pe(pe
);
1495 void pnv_pci_sriov_disable(struct pci_dev
*pdev
)
1497 struct pci_bus
*bus
;
1498 struct pci_controller
*hose
;
1499 struct pnv_phb
*phb
;
1500 struct pnv_ioda_pe
*pe
;
1505 hose
= pci_bus_to_host(bus
);
1506 phb
= hose
->private_data
;
1507 pdn
= pci_get_pdn(pdev
);
1508 num_vfs
= pdn
->num_vfs
;
1510 /* Release VF PEs */
1511 pnv_ioda_release_vf_PE(pdev
);
1513 if (phb
->type
== PNV_PHB_IODA2
) {
1514 if (!pdn
->m64_single_mode
)
1515 pnv_pci_vf_resource_shift(pdev
, -*pdn
->pe_num_map
);
1517 /* Release M64 windows */
1518 pnv_pci_vf_release_m64(pdev
, num_vfs
);
1520 /* Release PE numbers */
1521 if (pdn
->m64_single_mode
) {
1522 for (i
= 0; i
< num_vfs
; i
++) {
1523 if (pdn
->pe_num_map
[i
] == IODA_INVALID_PE
)
1526 pe
= &phb
->ioda
.pe_array
[pdn
->pe_num_map
[i
]];
1527 pnv_ioda_free_pe(pe
);
1530 bitmap_clear(phb
->ioda
.pe_alloc
, *pdn
->pe_num_map
, num_vfs
);
1531 /* Releasing pe_num_map */
1532 kfree(pdn
->pe_num_map
);
1536 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb
*phb
,
1537 struct pnv_ioda_pe
*pe
);
1538 #ifdef CONFIG_IOMMU_API
1539 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe
*pe
,
1540 struct iommu_table_group
*table_group
, struct pci_bus
*bus
);
1543 static void pnv_ioda_setup_vf_PE(struct pci_dev
*pdev
, u16 num_vfs
)
1545 struct pci_bus
*bus
;
1546 struct pci_controller
*hose
;
1547 struct pnv_phb
*phb
;
1548 struct pnv_ioda_pe
*pe
;
1554 hose
= pci_bus_to_host(bus
);
1555 phb
= hose
->private_data
;
1556 pdn
= pci_get_pdn(pdev
);
1558 if (!pdev
->is_physfn
)
1561 /* Reserve PE for each VF */
1562 for (vf_index
= 0; vf_index
< num_vfs
; vf_index
++) {
1563 if (pdn
->m64_single_mode
)
1564 pe_num
= pdn
->pe_num_map
[vf_index
];
1566 pe_num
= *pdn
->pe_num_map
+ vf_index
;
1568 pe
= &phb
->ioda
.pe_array
[pe_num
];
1569 pe
->pe_number
= pe_num
;
1571 pe
->flags
= PNV_IODA_PE_VF
;
1573 pe
->parent_dev
= pdev
;
1574 pe
->mve_number
= -1;
1575 pe
->rid
= (pci_iov_virtfn_bus(pdev
, vf_index
) << 8) |
1576 pci_iov_virtfn_devfn(pdev
, vf_index
);
1578 pe_info(pe
, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1579 hose
->global_number
, pdev
->bus
->number
,
1580 PCI_SLOT(pci_iov_virtfn_devfn(pdev
, vf_index
)),
1581 PCI_FUNC(pci_iov_virtfn_devfn(pdev
, vf_index
)), pe_num
);
1583 if (pnv_ioda_configure_pe(phb
, pe
)) {
1584 /* XXX What do we do here ? */
1585 pnv_ioda_free_pe(pe
);
1590 /* Put PE to the list */
1591 mutex_lock(&phb
->ioda
.pe_list_mutex
);
1592 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1593 mutex_unlock(&phb
->ioda
.pe_list_mutex
);
1595 pnv_pci_ioda2_setup_dma_pe(phb
, pe
);
1596 #ifdef CONFIG_IOMMU_API
1597 iommu_register_group(&pe
->table_group
,
1598 pe
->phb
->hose
->global_number
, pe
->pe_number
);
1599 pnv_ioda_setup_bus_iommu_group(pe
, &pe
->table_group
, NULL
);
1604 int pnv_pci_sriov_enable(struct pci_dev
*pdev
, u16 num_vfs
)
1606 struct pci_bus
*bus
;
1607 struct pci_controller
*hose
;
1608 struct pnv_phb
*phb
;
1609 struct pnv_ioda_pe
*pe
;
1615 hose
= pci_bus_to_host(bus
);
1616 phb
= hose
->private_data
;
1617 pdn
= pci_get_pdn(pdev
);
1619 if (phb
->type
== PNV_PHB_IODA2
) {
1620 if (!pdn
->vfs_expanded
) {
1621 dev_info(&pdev
->dev
, "don't support this SRIOV device"
1622 " with non 64bit-prefetchable IOV BAR\n");
1627 * When M64 BARs functions in Single PE mode, the number of VFs
1628 * could be enabled must be less than the number of M64 BARs.
1630 if (pdn
->m64_single_mode
&& num_vfs
> phb
->ioda
.m64_bar_idx
) {
1631 dev_info(&pdev
->dev
, "Not enough M64 BAR for VFs\n");
1635 /* Allocating pe_num_map */
1636 if (pdn
->m64_single_mode
)
1637 pdn
->pe_num_map
= kmalloc_array(num_vfs
,
1638 sizeof(*pdn
->pe_num_map
),
1641 pdn
->pe_num_map
= kmalloc(sizeof(*pdn
->pe_num_map
), GFP_KERNEL
);
1643 if (!pdn
->pe_num_map
)
1646 if (pdn
->m64_single_mode
)
1647 for (i
= 0; i
< num_vfs
; i
++)
1648 pdn
->pe_num_map
[i
] = IODA_INVALID_PE
;
1650 /* Calculate available PE for required VFs */
1651 if (pdn
->m64_single_mode
) {
1652 for (i
= 0; i
< num_vfs
; i
++) {
1653 pe
= pnv_ioda_alloc_pe(phb
);
1659 pdn
->pe_num_map
[i
] = pe
->pe_number
;
1662 mutex_lock(&phb
->ioda
.pe_alloc_mutex
);
1663 *pdn
->pe_num_map
= bitmap_find_next_zero_area(
1664 phb
->ioda
.pe_alloc
, phb
->ioda
.total_pe_num
,
1666 if (*pdn
->pe_num_map
>= phb
->ioda
.total_pe_num
) {
1667 mutex_unlock(&phb
->ioda
.pe_alloc_mutex
);
1668 dev_info(&pdev
->dev
, "Failed to enable VF%d\n", num_vfs
);
1669 kfree(pdn
->pe_num_map
);
1672 bitmap_set(phb
->ioda
.pe_alloc
, *pdn
->pe_num_map
, num_vfs
);
1673 mutex_unlock(&phb
->ioda
.pe_alloc_mutex
);
1675 pdn
->num_vfs
= num_vfs
;
1677 /* Assign M64 window accordingly */
1678 ret
= pnv_pci_vf_assign_m64(pdev
, num_vfs
);
1680 dev_info(&pdev
->dev
, "Not enough M64 window resources\n");
1685 * When using one M64 BAR to map one IOV BAR, we need to shift
1686 * the IOV BAR according to the PE# allocated to the VFs.
1687 * Otherwise, the PE# for the VF will conflict with others.
1689 if (!pdn
->m64_single_mode
) {
1690 ret
= pnv_pci_vf_resource_shift(pdev
, *pdn
->pe_num_map
);
1697 pnv_ioda_setup_vf_PE(pdev
, num_vfs
);
1702 if (pdn
->m64_single_mode
) {
1703 for (i
= 0; i
< num_vfs
; i
++) {
1704 if (pdn
->pe_num_map
[i
] == IODA_INVALID_PE
)
1707 pe
= &phb
->ioda
.pe_array
[pdn
->pe_num_map
[i
]];
1708 pnv_ioda_free_pe(pe
);
1711 bitmap_clear(phb
->ioda
.pe_alloc
, *pdn
->pe_num_map
, num_vfs
);
1713 /* Releasing pe_num_map */
1714 kfree(pdn
->pe_num_map
);
1719 int pnv_pcibios_sriov_disable(struct pci_dev
*pdev
)
1721 pnv_pci_sriov_disable(pdev
);
1723 /* Release PCI data */
1724 remove_dev_pci_data(pdev
);
1728 int pnv_pcibios_sriov_enable(struct pci_dev
*pdev
, u16 num_vfs
)
1730 /* Allocate PCI data */
1731 add_dev_pci_data(pdev
);
1733 return pnv_pci_sriov_enable(pdev
, num_vfs
);
1735 #endif /* CONFIG_PCI_IOV */
1737 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb
*phb
, struct pci_dev
*pdev
)
1739 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1740 struct pnv_ioda_pe
*pe
;
1743 * The function can be called while the PE#
1744 * hasn't been assigned. Do nothing for the
1747 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
1750 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1751 WARN_ON(get_dma_ops(&pdev
->dev
) != &dma_iommu_ops
);
1752 pdev
->dev
.archdata
.dma_offset
= pe
->tce_bypass_base
;
1753 set_iommu_table_base(&pdev
->dev
, pe
->table_group
.tables
[0]);
1755 * Note: iommu_add_device() will fail here as
1756 * for physical PE: the device is already added by now;
1757 * for virtual PE: sysfs entries are not ready yet and
1758 * tce_iommu_bus_notifier will add the device to a group later.
1763 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1765 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1766 * Devices can only access more than that if bit 59 of the PCI address is set
1767 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1768 * Many PCI devices are not capable of addressing that many bits, and as a
1769 * result are limited to the 4GB of virtual memory made available to 32-bit
1772 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1773 * devices by configuring the virtual memory past the first 4GB inaccessible
1774 * by 64-bit DMAs. This should only be used by devices that want more than
1775 * 4GB, and only on PEs that have no 32-bit devices.
1777 * Currently this will only work on PHB3 (POWER8).
1779 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe
*pe
)
1781 u64 window_size
, table_size
, tce_count
, addr
;
1782 struct page
*table_pages
;
1783 u64 tce_order
= 28; /* 256MB TCEs */
1788 * Window size needs to be a power of two, but needs to account for
1789 * shifting memory by the 4GB offset required to skip 32bit space.
1791 window_size
= roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1792 tce_count
= window_size
>> tce_order
;
1793 table_size
= tce_count
<< 3;
1795 if (table_size
< PAGE_SIZE
)
1796 table_size
= PAGE_SIZE
;
1798 table_pages
= alloc_pages_node(pe
->phb
->hose
->node
, GFP_KERNEL
,
1799 get_order(table_size
));
1803 tces
= page_address(table_pages
);
1807 memset(tces
, 0, table_size
);
1809 for (addr
= 0; addr
< memory_hotplug_max(); addr
+= (1 << tce_order
)) {
1810 tces
[(addr
+ (1ULL << 32)) >> tce_order
] =
1811 cpu_to_be64(addr
| TCE_PCI_READ
| TCE_PCI_WRITE
);
1814 rc
= opal_pci_map_pe_dma_window(pe
->phb
->opal_id
,
1816 /* reconfigure window 0 */
1817 (pe
->pe_number
<< 1) + 0,
1822 if (rc
== OPAL_SUCCESS
) {
1823 pe_info(pe
, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1827 pe_err(pe
, "Error configuring 64-bit DMA bypass\n");
1831 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev
*pdev
,
1834 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
1835 struct pnv_phb
*phb
= hose
->private_data
;
1836 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1837 struct pnv_ioda_pe
*pe
;
1839 if (WARN_ON(!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
))
1842 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1843 if (pe
->tce_bypass_enabled
) {
1844 u64 top
= pe
->tce_bypass_base
+ memblock_end_of_DRAM() - 1;
1845 if (dma_mask
>= top
)
1850 * If the device can't set the TCE bypass bit but still wants
1851 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1852 * bypass the 32-bit region and be usable for 64-bit DMAs.
1853 * The device needs to be able to address all of this space.
1855 if (dma_mask
>> 32 &&
1856 dma_mask
> (memory_hotplug_max() + (1ULL << 32)) &&
1857 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1858 (pe
->device_count
== 1 || !pe
->pbus
) &&
1859 phb
->model
== PNV_PHB_MODEL_PHB3
) {
1860 /* Configure the bypass mode */
1861 s64 rc
= pnv_pci_ioda_dma_64bit_bypass(pe
);
1864 /* 4GB offset bypasses 32-bit space */
1865 pdev
->dev
.archdata
.dma_offset
= (1ULL << 32);
1872 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe
*pe
, struct pci_bus
*bus
)
1874 struct pci_dev
*dev
;
1876 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1877 set_iommu_table_base(&dev
->dev
, pe
->table_group
.tables
[0]);
1878 dev
->dev
.archdata
.dma_offset
= pe
->tce_bypass_base
;
1880 if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && dev
->subordinate
)
1881 pnv_ioda_setup_bus_dma(pe
, dev
->subordinate
);
1885 static inline __be64 __iomem
*pnv_ioda_get_inval_reg(struct pnv_phb
*phb
,
1888 return real_mode
? (__be64 __iomem
*)(phb
->regs_phys
+ 0x210) :
1889 (phb
->regs
+ 0x210);
1892 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table
*tbl
,
1893 unsigned long index
, unsigned long npages
, bool rm
)
1895 struct iommu_table_group_link
*tgl
= list_first_entry_or_null(
1896 &tbl
->it_group_list
, struct iommu_table_group_link
,
1898 struct pnv_ioda_pe
*pe
= container_of(tgl
->table_group
,
1899 struct pnv_ioda_pe
, table_group
);
1900 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(pe
->phb
, rm
);
1901 unsigned long start
, end
, inc
;
1903 start
= __pa(((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
);
1904 end
= __pa(((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
+
1907 /* p7ioc-style invalidation, 2 TCEs per write */
1908 start
|= (1ull << 63);
1909 end
|= (1ull << 63);
1911 end
|= inc
- 1; /* round up end to be different than start */
1913 mb(); /* Ensure above stores are visible */
1914 while (start
<= end
) {
1916 __raw_rm_writeq_be(start
, invalidate
);
1918 __raw_writeq_be(start
, invalidate
);
1924 * The iommu layer will do another mb() for us on build()
1925 * and we don't care on free()
1929 static int pnv_ioda1_tce_build(struct iommu_table
*tbl
, long index
,
1930 long npages
, unsigned long uaddr
,
1931 enum dma_data_direction direction
,
1932 unsigned long attrs
)
1934 int ret
= pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
,
1938 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, npages
, false);
1943 #ifdef CONFIG_IOMMU_API
1944 static int pnv_ioda1_tce_xchg(struct iommu_table
*tbl
, long index
,
1945 unsigned long *hpa
, enum dma_data_direction
*direction
)
1947 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
, true);
1950 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, 1, false);
1955 static int pnv_ioda1_tce_xchg_rm(struct iommu_table
*tbl
, long index
,
1956 unsigned long *hpa
, enum dma_data_direction
*direction
)
1958 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
, false);
1961 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, 1, true);
1967 static void pnv_ioda1_tce_free(struct iommu_table
*tbl
, long index
,
1970 pnv_tce_free(tbl
, index
, npages
);
1972 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, npages
, false);
1975 static struct iommu_table_ops pnv_ioda1_iommu_ops
= {
1976 .set
= pnv_ioda1_tce_build
,
1977 #ifdef CONFIG_IOMMU_API
1978 .exchange
= pnv_ioda1_tce_xchg
,
1979 .exchange_rm
= pnv_ioda1_tce_xchg_rm
,
1980 .useraddrptr
= pnv_tce_useraddrptr
,
1982 .clear
= pnv_ioda1_tce_free
,
1986 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1987 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1988 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1990 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb
*phb
, bool rm
)
1992 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(phb
, rm
);
1993 const unsigned long val
= PHB3_TCE_KILL_INVAL_ALL
;
1995 mb(); /* Ensure previous TCE table stores are visible */
1997 __raw_rm_writeq_be(val
, invalidate
);
1999 __raw_writeq_be(val
, invalidate
);
2002 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe
*pe
)
2004 /* 01xb - invalidate TCEs that match the specified PE# */
2005 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(pe
->phb
, false);
2006 unsigned long val
= PHB3_TCE_KILL_INVAL_PE
| (pe
->pe_number
& 0xFF);
2008 mb(); /* Ensure above stores are visible */
2009 __raw_writeq_be(val
, invalidate
);
2012 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe
*pe
, bool rm
,
2013 unsigned shift
, unsigned long index
,
2014 unsigned long npages
)
2016 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(pe
->phb
, rm
);
2017 unsigned long start
, end
, inc
;
2019 /* We'll invalidate DMA address in PE scope */
2020 start
= PHB3_TCE_KILL_INVAL_ONE
;
2021 start
|= (pe
->pe_number
& 0xFF);
2024 /* Figure out the start, end and step */
2025 start
|= (index
<< shift
);
2026 end
|= ((index
+ npages
- 1) << shift
);
2027 inc
= (0x1ull
<< shift
);
2030 while (start
<= end
) {
2032 __raw_rm_writeq_be(start
, invalidate
);
2034 __raw_writeq_be(start
, invalidate
);
2039 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe
*pe
)
2041 struct pnv_phb
*phb
= pe
->phb
;
2043 if (phb
->model
== PNV_PHB_MODEL_PHB3
&& phb
->regs
)
2044 pnv_pci_phb3_tce_invalidate_pe(pe
);
2046 opal_pci_tce_kill(phb
->opal_id
, OPAL_PCI_TCE_KILL_PE
,
2047 pe
->pe_number
, 0, 0, 0);
2050 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table
*tbl
,
2051 unsigned long index
, unsigned long npages
, bool rm
)
2053 struct iommu_table_group_link
*tgl
;
2055 list_for_each_entry_lockless(tgl
, &tbl
->it_group_list
, next
) {
2056 struct pnv_ioda_pe
*pe
= container_of(tgl
->table_group
,
2057 struct pnv_ioda_pe
, table_group
);
2058 struct pnv_phb
*phb
= pe
->phb
;
2059 unsigned int shift
= tbl
->it_page_shift
;
2062 * NVLink1 can use the TCE kill register directly as
2063 * it's the same as PHB3. NVLink2 is different and
2064 * should go via the OPAL call.
2066 if (phb
->model
== PNV_PHB_MODEL_NPU
) {
2068 * The NVLink hardware does not support TCE kill
2069 * per TCE entry so we have to invalidate
2070 * the entire cache for it.
2072 pnv_pci_phb3_tce_invalidate_entire(phb
, rm
);
2075 if (phb
->model
== PNV_PHB_MODEL_PHB3
&& phb
->regs
)
2076 pnv_pci_phb3_tce_invalidate(pe
, rm
, shift
,
2079 opal_pci_tce_kill(phb
->opal_id
,
2080 OPAL_PCI_TCE_KILL_PAGES
,
2081 pe
->pe_number
, 1u << shift
,
2082 index
<< shift
, npages
);
2086 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb
*phb
, bool rm
)
2088 if (phb
->model
== PNV_PHB_MODEL_NPU
|| phb
->model
== PNV_PHB_MODEL_PHB3
)
2089 pnv_pci_phb3_tce_invalidate_entire(phb
, rm
);
2091 opal_pci_tce_kill(phb
->opal_id
, OPAL_PCI_TCE_KILL
, 0, 0, 0, 0);
2094 static int pnv_ioda2_tce_build(struct iommu_table
*tbl
, long index
,
2095 long npages
, unsigned long uaddr
,
2096 enum dma_data_direction direction
,
2097 unsigned long attrs
)
2099 int ret
= pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
,
2103 pnv_pci_ioda2_tce_invalidate(tbl
, index
, npages
, false);
2108 #ifdef CONFIG_IOMMU_API
2109 static int pnv_ioda2_tce_xchg(struct iommu_table
*tbl
, long index
,
2110 unsigned long *hpa
, enum dma_data_direction
*direction
)
2112 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
, true);
2115 pnv_pci_ioda2_tce_invalidate(tbl
, index
, 1, false);
2120 static int pnv_ioda2_tce_xchg_rm(struct iommu_table
*tbl
, long index
,
2121 unsigned long *hpa
, enum dma_data_direction
*direction
)
2123 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
, false);
2126 pnv_pci_ioda2_tce_invalidate(tbl
, index
, 1, true);
2132 static void pnv_ioda2_tce_free(struct iommu_table
*tbl
, long index
,
2135 pnv_tce_free(tbl
, index
, npages
);
2137 pnv_pci_ioda2_tce_invalidate(tbl
, index
, npages
, false);
2140 static struct iommu_table_ops pnv_ioda2_iommu_ops
= {
2141 .set
= pnv_ioda2_tce_build
,
2142 #ifdef CONFIG_IOMMU_API
2143 .exchange
= pnv_ioda2_tce_xchg
,
2144 .exchange_rm
= pnv_ioda2_tce_xchg_rm
,
2145 .useraddrptr
= pnv_tce_useraddrptr
,
2147 .clear
= pnv_ioda2_tce_free
,
2149 .free
= pnv_pci_ioda2_table_free_pages
,
2152 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev
*dev
, void *data
)
2154 unsigned int *weight
= (unsigned int *)data
;
2156 /* This is quite simplistic. The "base" weight of a device
2157 * is 10. 0 means no DMA is to be accounted for it.
2159 if (dev
->hdr_type
!= PCI_HEADER_TYPE_NORMAL
)
2162 if (dev
->class == PCI_CLASS_SERIAL_USB_UHCI
||
2163 dev
->class == PCI_CLASS_SERIAL_USB_OHCI
||
2164 dev
->class == PCI_CLASS_SERIAL_USB_EHCI
)
2166 else if ((dev
->class >> 8) == PCI_CLASS_STORAGE_RAID
)
2174 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe
*pe
)
2176 unsigned int weight
= 0;
2178 /* SRIOV VF has same DMA32 weight as its PF */
2179 #ifdef CONFIG_PCI_IOV
2180 if ((pe
->flags
& PNV_IODA_PE_VF
) && pe
->parent_dev
) {
2181 pnv_pci_ioda_dev_dma_weight(pe
->parent_dev
, &weight
);
2186 if ((pe
->flags
& PNV_IODA_PE_DEV
) && pe
->pdev
) {
2187 pnv_pci_ioda_dev_dma_weight(pe
->pdev
, &weight
);
2188 } else if ((pe
->flags
& PNV_IODA_PE_BUS
) && pe
->pbus
) {
2189 struct pci_dev
*pdev
;
2191 list_for_each_entry(pdev
, &pe
->pbus
->devices
, bus_list
)
2192 pnv_pci_ioda_dev_dma_weight(pdev
, &weight
);
2193 } else if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && pe
->pbus
) {
2194 pci_walk_bus(pe
->pbus
, pnv_pci_ioda_dev_dma_weight
, &weight
);
2200 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb
*phb
,
2201 struct pnv_ioda_pe
*pe
)
2204 struct page
*tce_mem
= NULL
;
2205 struct iommu_table
*tbl
;
2206 unsigned int weight
, total_weight
= 0;
2207 unsigned int tce32_segsz
, base
, segs
, avail
, i
;
2211 /* XXX FIXME: Handle 64-bit only DMA devices */
2212 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2213 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2214 weight
= pnv_pci_ioda_pe_dma_weight(pe
);
2218 pci_walk_bus(phb
->hose
->bus
, pnv_pci_ioda_dev_dma_weight
,
2220 segs
= (weight
* phb
->ioda
.dma32_count
) / total_weight
;
2225 * Allocate contiguous DMA32 segments. We begin with the expected
2226 * number of segments. With one more attempt, the number of DMA32
2227 * segments to be allocated is decreased by one until one segment
2228 * is allocated successfully.
2231 for (base
= 0; base
<= phb
->ioda
.dma32_count
- segs
; base
++) {
2232 for (avail
= 0, i
= base
; i
< base
+ segs
; i
++) {
2233 if (phb
->ioda
.dma32_segmap
[i
] ==
2244 pe_warn(pe
, "No available DMA32 segments\n");
2249 tbl
= pnv_pci_table_alloc(phb
->hose
->node
);
2253 iommu_register_group(&pe
->table_group
, phb
->hose
->global_number
,
2255 pnv_pci_link_table_and_group(phb
->hose
->node
, 0, tbl
, &pe
->table_group
);
2257 /* Grab a 32-bit TCE table */
2258 pe_info(pe
, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2259 weight
, total_weight
, base
, segs
);
2260 pe_info(pe
, " Setting up 32-bit TCE table at %08x..%08x\n",
2261 base
* PNV_IODA1_DMA32_SEGSIZE
,
2262 (base
+ segs
) * PNV_IODA1_DMA32_SEGSIZE
- 1);
2264 /* XXX Currently, we allocate one big contiguous table for the
2265 * TCEs. We only really need one chunk per 256M of TCE space
2266 * (ie per segment) but that's an optimization for later, it
2267 * requires some added smarts with our get/put_tce implementation
2269 * Each TCE page is 4KB in size and each TCE entry occupies 8
2272 tce32_segsz
= PNV_IODA1_DMA32_SEGSIZE
>> (IOMMU_PAGE_SHIFT_4K
- 3);
2273 tce_mem
= alloc_pages_node(phb
->hose
->node
, GFP_KERNEL
,
2274 get_order(tce32_segsz
* segs
));
2276 pe_err(pe
, " Failed to allocate a 32-bit TCE memory\n");
2279 addr
= page_address(tce_mem
);
2280 memset(addr
, 0, tce32_segsz
* segs
);
2283 for (i
= 0; i
< segs
; i
++) {
2284 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
,
2287 __pa(addr
) + tce32_segsz
* i
,
2288 tce32_segsz
, IOMMU_PAGE_SIZE_4K
);
2290 pe_err(pe
, " Failed to configure 32-bit TCE table, err %lld\n",
2296 /* Setup DMA32 segment mapping */
2297 for (i
= base
; i
< base
+ segs
; i
++)
2298 phb
->ioda
.dma32_segmap
[i
] = pe
->pe_number
;
2300 /* Setup linux iommu table */
2301 pnv_pci_setup_iommu_table(tbl
, addr
, tce32_segsz
* segs
,
2302 base
* PNV_IODA1_DMA32_SEGSIZE
,
2303 IOMMU_PAGE_SHIFT_4K
);
2305 tbl
->it_ops
= &pnv_ioda1_iommu_ops
;
2306 pe
->table_group
.tce32_start
= tbl
->it_offset
<< tbl
->it_page_shift
;
2307 pe
->table_group
.tce32_size
= tbl
->it_size
<< tbl
->it_page_shift
;
2308 iommu_init_table(tbl
, phb
->hose
->node
);
2310 if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
2311 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
2315 /* XXX Failure: Try to fallback to 64-bit only ? */
2317 __free_pages(tce_mem
, get_order(tce32_segsz
* segs
));
2319 pnv_pci_unlink_table_and_group(tbl
, &pe
->table_group
);
2320 iommu_tce_table_put(tbl
);
2324 static long pnv_pci_ioda2_set_window(struct iommu_table_group
*table_group
,
2325 int num
, struct iommu_table
*tbl
)
2327 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2329 struct pnv_phb
*phb
= pe
->phb
;
2331 const unsigned long size
= tbl
->it_indirect_levels
?
2332 tbl
->it_level_size
: tbl
->it_size
;
2333 const __u64 start_addr
= tbl
->it_offset
<< tbl
->it_page_shift
;
2334 const __u64 win_size
= tbl
->it_size
<< tbl
->it_page_shift
;
2336 pe_info(pe
, "Setting up window#%d %llx..%llx pg=%lx\n",
2337 num
, start_addr
, start_addr
+ win_size
- 1,
2338 IOMMU_PAGE_SIZE(tbl
));
2341 * Map TCE table through TVT. The TVE index is the PE number
2342 * shifted by 1 bit for 32-bits DMA space.
2344 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
,
2346 (pe
->pe_number
<< 1) + num
,
2347 tbl
->it_indirect_levels
+ 1,
2350 IOMMU_PAGE_SIZE(tbl
));
2352 pe_err(pe
, "Failed to configure TCE table, err %lld\n", rc
);
2356 pnv_pci_link_table_and_group(phb
->hose
->node
, num
,
2357 tbl
, &pe
->table_group
);
2358 pnv_pci_ioda2_tce_invalidate_pe(pe
);
2363 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe
*pe
, bool enable
)
2365 uint16_t window_id
= (pe
->pe_number
<< 1 ) + 1;
2368 pe_info(pe
, "%sabling 64-bit DMA bypass\n", enable
? "En" : "Dis");
2370 phys_addr_t top
= memblock_end_of_DRAM();
2372 top
= roundup_pow_of_two(top
);
2373 rc
= opal_pci_map_pe_dma_window_real(pe
->phb
->opal_id
,
2376 pe
->tce_bypass_base
,
2379 rc
= opal_pci_map_pe_dma_window_real(pe
->phb
->opal_id
,
2382 pe
->tce_bypass_base
,
2386 pe_err(pe
, "OPAL error %lld configuring bypass window\n", rc
);
2388 pe
->tce_bypass_enabled
= enable
;
2391 static long pnv_pci_ioda2_create_table(struct iommu_table_group
*table_group
,
2392 int num
, __u32 page_shift
, __u64 window_size
, __u32 levels
,
2393 bool alloc_userspace_copy
, struct iommu_table
**ptbl
)
2395 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2397 int nid
= pe
->phb
->hose
->node
;
2398 __u64 bus_offset
= num
? pe
->tce_bypass_base
: table_group
->tce32_start
;
2400 struct iommu_table
*tbl
;
2402 tbl
= pnv_pci_table_alloc(nid
);
2406 tbl
->it_ops
= &pnv_ioda2_iommu_ops
;
2408 ret
= pnv_pci_ioda2_table_alloc_pages(nid
,
2409 bus_offset
, page_shift
, window_size
,
2410 levels
, alloc_userspace_copy
, tbl
);
2412 iommu_tce_table_put(tbl
);
2421 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe
*pe
)
2423 struct iommu_table
*tbl
= NULL
;
2427 * crashkernel= specifies the kdump kernel's maximum memory at
2428 * some offset and there is no guaranteed the result is a power
2429 * of 2, which will cause errors later.
2431 const u64 max_memory
= __rounddown_pow_of_two(memory_hotplug_max());
2434 * In memory constrained environments, e.g. kdump kernel, the
2435 * DMA window can be larger than available memory, which will
2436 * cause errors later.
2438 const u64 window_size
= min((u64
)pe
->table_group
.tce32_size
, max_memory
);
2440 rc
= pnv_pci_ioda2_create_table(&pe
->table_group
, 0,
2441 IOMMU_PAGE_SHIFT_4K
,
2443 POWERNV_IOMMU_DEFAULT_LEVELS
, false, &tbl
);
2445 pe_err(pe
, "Failed to create 32-bit TCE table, err %ld",
2450 iommu_init_table(tbl
, pe
->phb
->hose
->node
);
2452 rc
= pnv_pci_ioda2_set_window(&pe
->table_group
, 0, tbl
);
2454 pe_err(pe
, "Failed to configure 32-bit TCE table, err %ld\n",
2456 iommu_tce_table_put(tbl
);
2460 if (!pnv_iommu_bypass_disabled
)
2461 pnv_pci_ioda2_set_bypass(pe
, true);
2466 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2467 static long pnv_pci_ioda2_unset_window(struct iommu_table_group
*table_group
,
2470 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2472 struct pnv_phb
*phb
= pe
->phb
;
2475 pe_info(pe
, "Removing DMA window #%d\n", num
);
2477 ret
= opal_pci_map_pe_dma_window(phb
->opal_id
, pe
->pe_number
,
2478 (pe
->pe_number
<< 1) + num
,
2479 0/* levels */, 0/* table address */,
2480 0/* table size */, 0/* page size */);
2482 pe_warn(pe
, "Unmapping failed, ret = %ld\n", ret
);
2484 pnv_pci_ioda2_tce_invalidate_pe(pe
);
2486 pnv_pci_unlink_table_and_group(table_group
->tables
[num
], table_group
);
2492 #ifdef CONFIG_IOMMU_API
2493 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift
,
2494 __u64 window_size
, __u32 levels
)
2496 unsigned long bytes
= 0;
2497 const unsigned window_shift
= ilog2(window_size
);
2498 unsigned entries_shift
= window_shift
- page_shift
;
2499 unsigned table_shift
= entries_shift
+ 3;
2500 unsigned long tce_table_size
= max(0x1000UL
, 1UL << table_shift
);
2501 unsigned long direct_table_size
;
2503 if (!levels
|| (levels
> POWERNV_IOMMU_MAX_LEVELS
) ||
2504 !is_power_of_2(window_size
))
2507 /* Calculate a direct table size from window_size and levels */
2508 entries_shift
= (entries_shift
+ levels
- 1) / levels
;
2509 table_shift
= entries_shift
+ 3;
2510 table_shift
= max_t(unsigned, table_shift
, PAGE_SHIFT
);
2511 direct_table_size
= 1UL << table_shift
;
2513 for ( ; levels
; --levels
) {
2514 bytes
+= _ALIGN_UP(tce_table_size
, direct_table_size
);
2516 tce_table_size
/= direct_table_size
;
2517 tce_table_size
<<= 3;
2518 tce_table_size
= max_t(unsigned long,
2519 tce_table_size
, direct_table_size
);
2522 return bytes
+ bytes
; /* one for HW table, one for userspace copy */
2525 static long pnv_pci_ioda2_create_table_userspace(
2526 struct iommu_table_group
*table_group
,
2527 int num
, __u32 page_shift
, __u64 window_size
, __u32 levels
,
2528 struct iommu_table
**ptbl
)
2530 long ret
= pnv_pci_ioda2_create_table(table_group
,
2531 num
, page_shift
, window_size
, levels
, true, ptbl
);
2534 (*ptbl
)->it_allocated_size
= pnv_pci_ioda2_get_table_size(
2535 page_shift
, window_size
, levels
);
2539 static void pnv_ioda2_take_ownership(struct iommu_table_group
*table_group
)
2541 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2543 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2544 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
2546 pnv_pci_ioda2_set_bypass(pe
, false);
2547 pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
2549 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
2550 iommu_tce_table_put(tbl
);
2553 static void pnv_ioda2_release_ownership(struct iommu_table_group
*table_group
)
2555 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2558 pnv_pci_ioda2_setup_default_config(pe
);
2560 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
2563 static struct iommu_table_group_ops pnv_pci_ioda2_ops
= {
2564 .get_table_size
= pnv_pci_ioda2_get_table_size
,
2565 .create_table
= pnv_pci_ioda2_create_table_userspace
,
2566 .set_window
= pnv_pci_ioda2_set_window
,
2567 .unset_window
= pnv_pci_ioda2_unset_window
,
2568 .take_ownership
= pnv_ioda2_take_ownership
,
2569 .release_ownership
= pnv_ioda2_release_ownership
,
2572 static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe
*pe
,
2573 struct iommu_table_group
*table_group
,
2574 struct pci_bus
*bus
)
2576 struct pci_dev
*dev
;
2578 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
2579 iommu_add_device(table_group
, &dev
->dev
);
2581 if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && dev
->subordinate
)
2582 pnv_ioda_setup_bus_iommu_group_add_devices(pe
,
2583 table_group
, dev
->subordinate
);
2587 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe
*pe
,
2588 struct iommu_table_group
*table_group
, struct pci_bus
*bus
)
2591 if (pe
->flags
& PNV_IODA_PE_DEV
)
2592 iommu_add_device(table_group
, &pe
->pdev
->dev
);
2594 if ((pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
)) || bus
)
2595 pnv_ioda_setup_bus_iommu_group_add_devices(pe
, table_group
,
2599 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb
*phb
);
2601 static void pnv_pci_ioda_setup_iommu_api(void)
2603 struct pci_controller
*hose
;
2604 struct pnv_phb
*phb
;
2605 struct pnv_ioda_pe
*pe
;
2608 * There are 4 types of PEs:
2609 * - PNV_IODA_PE_BUS: a downstream port with an adapter,
2610 * created from pnv_pci_setup_bridge();
2611 * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
2612 * created from pnv_pci_setup_bridge();
2613 * - PNV_IODA_PE_VF: a SRIOV virtual function,
2614 * created from pnv_pcibios_sriov_enable();
2615 * - PNV_IODA_PE_DEV: an NPU or OCAPI device,
2616 * created from pnv_pci_ioda_fixup().
2618 * Normally a PE is represented by an IOMMU group, however for
2619 * devices with side channels the groups need to be more strict.
2621 list_for_each_entry(hose
, &hose_list
, list_node
) {
2622 phb
= hose
->private_data
;
2624 if (phb
->type
== PNV_PHB_NPU_NVLINK
||
2625 phb
->type
== PNV_PHB_NPU_OCAPI
)
2628 list_for_each_entry(pe
, &phb
->ioda
.pe_list
, list
) {
2629 struct iommu_table_group
*table_group
;
2631 table_group
= pnv_try_setup_npu_table_group(pe
);
2633 if (!pnv_pci_ioda_pe_dma_weight(pe
))
2636 table_group
= &pe
->table_group
;
2637 iommu_register_group(&pe
->table_group
,
2638 pe
->phb
->hose
->global_number
,
2641 pnv_ioda_setup_bus_iommu_group(pe
, table_group
,
2647 * Now we have all PHBs discovered, time to add NPU devices to
2648 * the corresponding IOMMU groups.
2650 list_for_each_entry(hose
, &hose_list
, list_node
) {
2651 unsigned long pgsizes
;
2653 phb
= hose
->private_data
;
2655 if (phb
->type
!= PNV_PHB_NPU_NVLINK
)
2658 pgsizes
= pnv_ioda_parse_tce_sizes(phb
);
2659 list_for_each_entry(pe
, &phb
->ioda
.pe_list
, list
) {
2661 * IODA2 bridges get this set up from
2662 * pci_controller_ops::setup_bridge but NPU bridges
2663 * do not have this hook defined so we do it here.
2665 pe
->table_group
.pgsizes
= pgsizes
;
2666 pnv_npu_compound_attach(pe
);
2670 #else /* !CONFIG_IOMMU_API */
2671 static void pnv_pci_ioda_setup_iommu_api(void) { };
2674 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb
*phb
)
2676 struct pci_controller
*hose
= phb
->hose
;
2677 struct device_node
*dn
= hose
->dn
;
2678 unsigned long mask
= 0;
2682 count
= of_property_count_u32_elems(dn
, "ibm,supported-tce-sizes");
2684 mask
= SZ_4K
| SZ_64K
;
2685 /* Add 16M for POWER8 by default */
2686 if (cpu_has_feature(CPU_FTR_ARCH_207S
) &&
2687 !cpu_has_feature(CPU_FTR_ARCH_300
))
2688 mask
|= SZ_16M
| SZ_256M
;
2692 for (i
= 0; i
< count
; i
++) {
2693 rc
= of_property_read_u32_index(dn
, "ibm,supported-tce-sizes",
2696 mask
|= 1ULL << val
;
2702 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb
*phb
,
2703 struct pnv_ioda_pe
*pe
)
2707 if (!pnv_pci_ioda_pe_dma_weight(pe
))
2710 /* TVE #1 is selected by PCI address bit 59 */
2711 pe
->tce_bypass_base
= 1ull << 59;
2713 /* The PE will reserve all possible 32-bits space */
2714 pe_info(pe
, "Setting up 32-bit TCE table at 0..%08x\n",
2715 phb
->ioda
.m32_pci_base
);
2717 /* Setup linux iommu table */
2718 pe
->table_group
.tce32_start
= 0;
2719 pe
->table_group
.tce32_size
= phb
->ioda
.m32_pci_base
;
2720 pe
->table_group
.max_dynamic_windows_supported
=
2721 IOMMU_TABLE_GROUP_MAX_TABLES
;
2722 pe
->table_group
.max_levels
= POWERNV_IOMMU_MAX_LEVELS
;
2723 pe
->table_group
.pgsizes
= pnv_ioda_parse_tce_sizes(phb
);
2724 #ifdef CONFIG_IOMMU_API
2725 pe
->table_group
.ops
= &pnv_pci_ioda2_ops
;
2728 rc
= pnv_pci_ioda2_setup_default_config(pe
);
2732 if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
2733 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
2736 int64_t pnv_opal_pci_msi_eoi(struct irq_chip
*chip
, unsigned int hw_irq
)
2738 struct pnv_phb
*phb
= container_of(chip
, struct pnv_phb
,
2741 return opal_pci_msi_eoi(phb
->opal_id
, hw_irq
);
2744 static void pnv_ioda2_msi_eoi(struct irq_data
*d
)
2747 unsigned int hw_irq
= (unsigned int)irqd_to_hwirq(d
);
2748 struct irq_chip
*chip
= irq_data_get_irq_chip(d
);
2750 rc
= pnv_opal_pci_msi_eoi(chip
, hw_irq
);
2757 void pnv_set_msi_irq_chip(struct pnv_phb
*phb
, unsigned int virq
)
2759 struct irq_data
*idata
;
2760 struct irq_chip
*ichip
;
2762 /* The MSI EOI OPAL call is only needed on PHB3 */
2763 if (phb
->model
!= PNV_PHB_MODEL_PHB3
)
2766 if (!phb
->ioda
.irq_chip_init
) {
2768 * First time we setup an MSI IRQ, we need to setup the
2769 * corresponding IRQ chip to route correctly.
2771 idata
= irq_get_irq_data(virq
);
2772 ichip
= irq_data_get_irq_chip(idata
);
2773 phb
->ioda
.irq_chip_init
= 1;
2774 phb
->ioda
.irq_chip
= *ichip
;
2775 phb
->ioda
.irq_chip
.irq_eoi
= pnv_ioda2_msi_eoi
;
2777 irq_set_chip(virq
, &phb
->ioda
.irq_chip
);
2781 * Returns true iff chip is something that we could call
2782 * pnv_opal_pci_msi_eoi for.
2784 bool is_pnv_opal_msi(struct irq_chip
*chip
)
2786 return chip
->irq_eoi
== pnv_ioda2_msi_eoi
;
2788 EXPORT_SYMBOL_GPL(is_pnv_opal_msi
);
2790 static int pnv_pci_ioda_msi_setup(struct pnv_phb
*phb
, struct pci_dev
*dev
,
2791 unsigned int hwirq
, unsigned int virq
,
2792 unsigned int is_64
, struct msi_msg
*msg
)
2794 struct pnv_ioda_pe
*pe
= pnv_ioda_get_pe(dev
);
2795 unsigned int xive_num
= hwirq
- phb
->msi_base
;
2799 /* No PE assigned ? bail out ... no MSI for you ! */
2803 /* Check if we have an MVE */
2804 if (pe
->mve_number
< 0)
2807 /* Force 32-bit MSI on some broken devices */
2808 if (dev
->no_64bit_msi
)
2811 /* Assign XIVE to PE */
2812 rc
= opal_pci_set_xive_pe(phb
->opal_id
, pe
->pe_number
, xive_num
);
2814 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2815 pci_name(dev
), rc
, xive_num
);
2822 rc
= opal_get_msi_64(phb
->opal_id
, pe
->mve_number
, xive_num
, 1,
2825 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2829 msg
->address_hi
= be64_to_cpu(addr64
) >> 32;
2830 msg
->address_lo
= be64_to_cpu(addr64
) & 0xfffffffful
;
2834 rc
= opal_get_msi_32(phb
->opal_id
, pe
->mve_number
, xive_num
, 1,
2837 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2841 msg
->address_hi
= 0;
2842 msg
->address_lo
= be32_to_cpu(addr32
);
2844 msg
->data
= be32_to_cpu(data
);
2846 pnv_set_msi_irq_chip(phb
, virq
);
2848 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2849 " address=%x_%08x data=%x PE# %x\n",
2850 pci_name(dev
), is_64
? "64" : "32", hwirq
, xive_num
,
2851 msg
->address_hi
, msg
->address_lo
, data
, pe
->pe_number
);
2856 static void pnv_pci_init_ioda_msis(struct pnv_phb
*phb
)
2859 const __be32
*prop
= of_get_property(phb
->hose
->dn
,
2860 "ibm,opal-msi-ranges", NULL
);
2863 prop
= of_get_property(phb
->hose
->dn
, "msi-ranges", NULL
);
2868 phb
->msi_base
= be32_to_cpup(prop
);
2869 count
= be32_to_cpup(prop
+ 1);
2870 if (msi_bitmap_alloc(&phb
->msi_bmp
, count
, phb
->hose
->dn
)) {
2871 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2872 phb
->hose
->global_number
);
2876 phb
->msi_setup
= pnv_pci_ioda_msi_setup
;
2877 phb
->msi32_support
= 1;
2878 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2879 count
, phb
->msi_base
);
2882 #ifdef CONFIG_PCI_IOV
2883 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev
*pdev
)
2885 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
2886 struct pnv_phb
*phb
= hose
->private_data
;
2887 const resource_size_t gate
= phb
->ioda
.m64_segsize
>> 2;
2888 struct resource
*res
;
2890 resource_size_t size
, total_vf_bar_sz
;
2894 if (!pdev
->is_physfn
|| pci_dev_is_added(pdev
))
2897 pdn
= pci_get_pdn(pdev
);
2898 pdn
->vfs_expanded
= 0;
2899 pdn
->m64_single_mode
= false;
2901 total_vfs
= pci_sriov_get_totalvfs(pdev
);
2902 mul
= phb
->ioda
.total_pe_num
;
2903 total_vf_bar_sz
= 0;
2905 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2906 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2907 if (!res
->flags
|| res
->parent
)
2909 if (!pnv_pci_is_m64_flags(res
->flags
)) {
2910 dev_warn(&pdev
->dev
, "Don't support SR-IOV with"
2911 " non M64 VF BAR%d: %pR. \n",
2916 total_vf_bar_sz
+= pci_iov_resource_size(pdev
,
2917 i
+ PCI_IOV_RESOURCES
);
2920 * If bigger than quarter of M64 segment size, just round up
2923 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2924 * with other devices, IOV BAR size is expanded to be
2925 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2926 * segment size , the expanded size would equal to half of the
2927 * whole M64 space size, which will exhaust the M64 Space and
2928 * limit the system flexibility. This is a design decision to
2929 * set the boundary to quarter of the M64 segment size.
2931 if (total_vf_bar_sz
> gate
) {
2932 mul
= roundup_pow_of_two(total_vfs
);
2933 dev_info(&pdev
->dev
,
2934 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2935 total_vf_bar_sz
, gate
, mul
);
2936 pdn
->m64_single_mode
= true;
2941 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2942 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2943 if (!res
->flags
|| res
->parent
)
2946 size
= pci_iov_resource_size(pdev
, i
+ PCI_IOV_RESOURCES
);
2948 * On PHB3, the minimum size alignment of M64 BAR in single
2951 if (pdn
->m64_single_mode
&& (size
< SZ_32M
))
2953 dev_dbg(&pdev
->dev
, " Fixing VF BAR%d: %pR to\n", i
, res
);
2954 res
->end
= res
->start
+ size
* mul
- 1;
2955 dev_dbg(&pdev
->dev
, " %pR\n", res
);
2956 dev_info(&pdev
->dev
, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2959 pdn
->vfs_expanded
= mul
;
2964 /* To save MMIO space, IOV BAR is truncated. */
2965 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2966 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2968 res
->end
= res
->start
- 1;
2971 #endif /* CONFIG_PCI_IOV */
2973 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe
*pe
,
2974 struct resource
*res
)
2976 struct pnv_phb
*phb
= pe
->phb
;
2977 struct pci_bus_region region
;
2981 if (!res
|| !res
->flags
|| res
->start
> res
->end
)
2984 if (res
->flags
& IORESOURCE_IO
) {
2985 region
.start
= res
->start
- phb
->ioda
.io_pci_base
;
2986 region
.end
= res
->end
- phb
->ioda
.io_pci_base
;
2987 index
= region
.start
/ phb
->ioda
.io_segsize
;
2989 while (index
< phb
->ioda
.total_pe_num
&&
2990 region
.start
<= region
.end
) {
2991 phb
->ioda
.io_segmap
[index
] = pe
->pe_number
;
2992 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
2993 pe
->pe_number
, OPAL_IO_WINDOW_TYPE
, 0, index
);
2994 if (rc
!= OPAL_SUCCESS
) {
2995 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
2996 __func__
, rc
, index
, pe
->pe_number
);
3000 region
.start
+= phb
->ioda
.io_segsize
;
3003 } else if ((res
->flags
& IORESOURCE_MEM
) &&
3004 !pnv_pci_is_m64(phb
, res
)) {
3005 region
.start
= res
->start
-
3006 phb
->hose
->mem_offset
[0] -
3007 phb
->ioda
.m32_pci_base
;
3008 region
.end
= res
->end
-
3009 phb
->hose
->mem_offset
[0] -
3010 phb
->ioda
.m32_pci_base
;
3011 index
= region
.start
/ phb
->ioda
.m32_segsize
;
3013 while (index
< phb
->ioda
.total_pe_num
&&
3014 region
.start
<= region
.end
) {
3015 phb
->ioda
.m32_segmap
[index
] = pe
->pe_number
;
3016 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
3017 pe
->pe_number
, OPAL_M32_WINDOW_TYPE
, 0, index
);
3018 if (rc
!= OPAL_SUCCESS
) {
3019 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3020 __func__
, rc
, index
, pe
->pe_number
);
3024 region
.start
+= phb
->ioda
.m32_segsize
;
3031 * This function is supposed to be called on basis of PE from top
3032 * to bottom style. So the the I/O or MMIO segment assigned to
3033 * parent PE could be overridden by its child PEs if necessary.
3035 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe
*pe
)
3037 struct pci_dev
*pdev
;
3041 * NOTE: We only care PCI bus based PE for now. For PCI
3042 * device based PE, for example SRIOV sensitive VF should
3043 * be figured out later.
3045 BUG_ON(!(pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
)));
3047 list_for_each_entry(pdev
, &pe
->pbus
->devices
, bus_list
) {
3048 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
3049 pnv_ioda_setup_pe_res(pe
, &pdev
->resource
[i
]);
3052 * If the PE contains all subordinate PCI buses, the
3053 * windows of the child bridges should be mapped to
3056 if (!(pe
->flags
& PNV_IODA_PE_BUS_ALL
) || !pci_is_bridge(pdev
))
3058 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
3059 pnv_ioda_setup_pe_res(pe
,
3060 &pdev
->resource
[PCI_BRIDGE_RESOURCES
+ i
]);
3064 #ifdef CONFIG_DEBUG_FS
3065 static int pnv_pci_diag_data_set(void *data
, u64 val
)
3067 struct pci_controller
*hose
;
3068 struct pnv_phb
*phb
;
3074 hose
= (struct pci_controller
*)data
;
3075 if (!hose
|| !hose
->private_data
)
3078 phb
= hose
->private_data
;
3080 /* Retrieve the diag data from firmware */
3081 ret
= opal_pci_get_phb_diag_data2(phb
->opal_id
, phb
->diag_data
,
3082 phb
->diag_data_size
);
3083 if (ret
!= OPAL_SUCCESS
)
3086 /* Print the diag data to the kernel log */
3087 pnv_pci_dump_phb_diag_data(phb
->hose
, phb
->diag_data
);
3091 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops
, NULL
,
3092 pnv_pci_diag_data_set
, "%llu\n");
3094 #endif /* CONFIG_DEBUG_FS */
3096 static void pnv_pci_ioda_create_dbgfs(void)
3098 #ifdef CONFIG_DEBUG_FS
3099 struct pci_controller
*hose
, *tmp
;
3100 struct pnv_phb
*phb
;
3103 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
3104 phb
= hose
->private_data
;
3106 /* Notify initialization of PHB done */
3107 phb
->initialized
= 1;
3109 sprintf(name
, "PCI%04x", hose
->global_number
);
3110 phb
->dbgfs
= debugfs_create_dir(name
, powerpc_debugfs_root
);
3112 pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3113 __func__
, hose
->global_number
);
3117 debugfs_create_file("dump_diag_regs", 0200, phb
->dbgfs
, hose
,
3118 &pnv_pci_diag_data_fops
);
3120 #endif /* CONFIG_DEBUG_FS */
3123 static void pnv_pci_enable_bridge(struct pci_bus
*bus
)
3125 struct pci_dev
*dev
= bus
->self
;
3126 struct pci_bus
*child
;
3128 /* Empty bus ? bail */
3129 if (list_empty(&bus
->devices
))
3133 * If there's a bridge associated with that bus enable it. This works
3134 * around races in the generic code if the enabling is done during
3135 * parallel probing. This can be removed once those races have been
3139 int rc
= pci_enable_device(dev
);
3141 pci_err(dev
, "Error enabling bridge (%d)\n", rc
);
3142 pci_set_master(dev
);
3145 /* Perform the same to child busses */
3146 list_for_each_entry(child
, &bus
->children
, node
)
3147 pnv_pci_enable_bridge(child
);
3150 static void pnv_pci_enable_bridges(void)
3152 struct pci_controller
*hose
;
3154 list_for_each_entry(hose
, &hose_list
, list_node
)
3155 pnv_pci_enable_bridge(hose
->bus
);
3158 static void pnv_pci_ioda_fixup(void)
3160 pnv_pci_ioda_setup_PEs();
3161 pnv_pci_ioda_setup_iommu_api();
3162 pnv_pci_ioda_create_dbgfs();
3164 pnv_pci_enable_bridges();
3167 pnv_eeh_post_init();
3172 * Returns the alignment for I/O or memory windows for P2P
3173 * bridges. That actually depends on how PEs are segmented.
3174 * For now, we return I/O or M32 segment size for PE sensitive
3175 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3176 * 1MiB for memory) will be returned.
3178 * The current PCI bus might be put into one PE, which was
3179 * create against the parent PCI bridge. For that case, we
3180 * needn't enlarge the alignment so that we can save some
3183 static resource_size_t
pnv_pci_window_alignment(struct pci_bus
*bus
,
3186 struct pci_dev
*bridge
;
3187 struct pci_controller
*hose
= pci_bus_to_host(bus
);
3188 struct pnv_phb
*phb
= hose
->private_data
;
3189 int num_pci_bridges
= 0;
3193 if (pci_pcie_type(bridge
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
3195 if (num_pci_bridges
>= 2)
3199 bridge
= bridge
->bus
->self
;
3203 * We fall back to M32 if M64 isn't supported. We enforce the M64
3204 * alignment for any 64-bit resource, PCIe doesn't care and
3205 * bridges only do 64-bit prefetchable anyway.
3207 if (phb
->ioda
.m64_segsize
&& pnv_pci_is_m64_flags(type
))
3208 return phb
->ioda
.m64_segsize
;
3209 if (type
& IORESOURCE_MEM
)
3210 return phb
->ioda
.m32_segsize
;
3212 return phb
->ioda
.io_segsize
;
3216 * We are updating root port or the upstream port of the
3217 * bridge behind the root port with PHB's windows in order
3218 * to accommodate the changes on required resources during
3219 * PCI (slot) hotplug, which is connected to either root
3220 * port or the downstream ports of PCIe switch behind the
3223 static void pnv_pci_fixup_bridge_resources(struct pci_bus
*bus
,
3226 struct pci_controller
*hose
= pci_bus_to_host(bus
);
3227 struct pnv_phb
*phb
= hose
->private_data
;
3228 struct pci_dev
*bridge
= bus
->self
;
3229 struct resource
*r
, *w
;
3230 bool msi_region
= false;
3233 /* Check if we need apply fixup to the bridge's windows */
3234 if (!pci_is_root_bus(bridge
->bus
) &&
3235 !pci_is_root_bus(bridge
->bus
->self
->bus
))
3238 /* Fixup the resources */
3239 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
3240 r
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
+ i
];
3241 if (!r
->flags
|| !r
->parent
)
3245 if (r
->flags
& type
& IORESOURCE_IO
)
3246 w
= &hose
->io_resource
;
3247 else if (pnv_pci_is_m64(phb
, r
) &&
3248 (type
& IORESOURCE_PREFETCH
) &&
3249 phb
->ioda
.m64_segsize
)
3250 w
= &hose
->mem_resources
[1];
3251 else if (r
->flags
& type
& IORESOURCE_MEM
) {
3252 w
= &hose
->mem_resources
[0];
3256 r
->start
= w
->start
;
3259 /* The 64KB 32-bits MSI region shouldn't be included in
3260 * the 32-bits bridge window. Otherwise, we can see strange
3261 * issues. One of them is EEH error observed on Garrison.
3263 * Exclude top 1MB region which is the minimal alignment of
3264 * 32-bits bridge window.
3273 static void pnv_pci_setup_bridge(struct pci_bus
*bus
, unsigned long type
)
3275 struct pci_controller
*hose
= pci_bus_to_host(bus
);
3276 struct pnv_phb
*phb
= hose
->private_data
;
3277 struct pci_dev
*bridge
= bus
->self
;
3278 struct pnv_ioda_pe
*pe
;
3279 bool all
= (pci_pcie_type(bridge
) == PCI_EXP_TYPE_PCI_BRIDGE
);
3281 /* Extend bridge's windows if necessary */
3282 pnv_pci_fixup_bridge_resources(bus
, type
);
3284 /* The PE for root bus should be realized before any one else */
3285 if (!phb
->ioda
.root_pe_populated
) {
3286 pe
= pnv_ioda_setup_bus_PE(phb
->hose
->bus
, false);
3288 phb
->ioda
.root_pe_idx
= pe
->pe_number
;
3289 phb
->ioda
.root_pe_populated
= true;
3293 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3294 if (list_empty(&bus
->devices
))
3297 /* Reserve PEs according to used M64 resources */
3298 pnv_ioda_reserve_m64_pe(bus
, NULL
, all
);
3301 * Assign PE. We might run here because of partial hotplug.
3302 * For the case, we just pick up the existing PE and should
3303 * not allocate resources again.
3305 pe
= pnv_ioda_setup_bus_PE(bus
, all
);
3309 pnv_ioda_setup_pe_seg(pe
);
3310 switch (phb
->type
) {
3312 pnv_pci_ioda1_setup_dma_pe(phb
, pe
);
3315 pnv_pci_ioda2_setup_dma_pe(phb
, pe
);
3318 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3319 __func__
, phb
->hose
->global_number
, phb
->type
);
3323 static resource_size_t
pnv_pci_default_alignment(void)
3328 #ifdef CONFIG_PCI_IOV
3329 static resource_size_t
pnv_pci_iov_resource_alignment(struct pci_dev
*pdev
,
3332 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
3333 struct pnv_phb
*phb
= hose
->private_data
;
3334 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
3335 resource_size_t align
;
3338 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3339 * SR-IOV. While from hardware perspective, the range mapped by M64
3340 * BAR should be size aligned.
3342 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3343 * powernv-specific hardware restriction is gone. But if just use the
3344 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3345 * in one segment of M64 #15, which introduces the PE conflict between
3346 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3349 * This function returns the total IOV BAR size if M64 BAR is in
3350 * Shared PE mode or just VF BAR size if not.
3351 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3352 * M64 segment size if IOV BAR size is less.
3354 align
= pci_iov_resource_size(pdev
, resno
);
3355 if (!pdn
->vfs_expanded
)
3357 if (pdn
->m64_single_mode
)
3358 return max(align
, (resource_size_t
)phb
->ioda
.m64_segsize
);
3360 return pdn
->vfs_expanded
* align
;
3362 #endif /* CONFIG_PCI_IOV */
3364 /* Prevent enabling devices for which we couldn't properly
3367 static bool pnv_pci_enable_device_hook(struct pci_dev
*dev
)
3369 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
3370 struct pnv_phb
*phb
= hose
->private_data
;
3373 /* The function is probably called while the PEs have
3374 * not be created yet. For example, resource reassignment
3375 * during PCI probe period. We just skip the check if
3378 if (!phb
->initialized
)
3381 pdn
= pci_get_pdn(dev
);
3382 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
3388 static long pnv_pci_ioda1_unset_window(struct iommu_table_group
*table_group
,
3391 struct pnv_ioda_pe
*pe
= container_of(table_group
,
3392 struct pnv_ioda_pe
, table_group
);
3393 struct pnv_phb
*phb
= pe
->phb
;
3397 pe_info(pe
, "Removing DMA window #%d\n", num
);
3398 for (idx
= 0; idx
< phb
->ioda
.dma32_count
; idx
++) {
3399 if (phb
->ioda
.dma32_segmap
[idx
] != pe
->pe_number
)
3402 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
, pe
->pe_number
,
3403 idx
, 0, 0ul, 0ul, 0ul);
3404 if (rc
!= OPAL_SUCCESS
) {
3405 pe_warn(pe
, "Failure %ld unmapping DMA32 segment#%d\n",
3410 phb
->ioda
.dma32_segmap
[idx
] = IODA_INVALID_PE
;
3413 pnv_pci_unlink_table_and_group(table_group
->tables
[num
], table_group
);
3414 return OPAL_SUCCESS
;
3417 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe
*pe
)
3419 unsigned int weight
= pnv_pci_ioda_pe_dma_weight(pe
);
3420 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
3426 rc
= pnv_pci_ioda1_unset_window(&pe
->table_group
, 0);
3427 if (rc
!= OPAL_SUCCESS
)
3430 pnv_pci_p7ioc_tce_invalidate(tbl
, tbl
->it_offset
, tbl
->it_size
, false);
3431 if (pe
->table_group
.group
) {
3432 iommu_group_put(pe
->table_group
.group
);
3433 WARN_ON(pe
->table_group
.group
);
3436 free_pages(tbl
->it_base
, get_order(tbl
->it_size
<< 3));
3437 iommu_tce_table_put(tbl
);
3440 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe
*pe
)
3442 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
3443 unsigned int weight
= pnv_pci_ioda_pe_dma_weight(pe
);
3444 #ifdef CONFIG_IOMMU_API
3451 #ifdef CONFIG_IOMMU_API
3452 rc
= pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
3454 pe_warn(pe
, "OPAL error %lld release DMA window\n", rc
);
3457 pnv_pci_ioda2_set_bypass(pe
, false);
3458 if (pe
->table_group
.group
) {
3459 iommu_group_put(pe
->table_group
.group
);
3460 WARN_ON(pe
->table_group
.group
);
3463 iommu_tce_table_put(tbl
);
3466 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe
*pe
,
3470 struct pnv_phb
*phb
= pe
->phb
;
3474 for (idx
= 0; idx
< phb
->ioda
.total_pe_num
; idx
++) {
3475 if (map
[idx
] != pe
->pe_number
)
3478 if (win
== OPAL_M64_WINDOW_TYPE
)
3479 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
3480 phb
->ioda
.reserved_pe_idx
, win
,
3481 idx
/ PNV_IODA1_M64_SEGS
,
3482 idx
% PNV_IODA1_M64_SEGS
);
3484 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
3485 phb
->ioda
.reserved_pe_idx
, win
, 0, idx
);
3487 if (rc
!= OPAL_SUCCESS
)
3488 pe_warn(pe
, "Error %lld unmapping (%d) segment#%d\n",
3491 map
[idx
] = IODA_INVALID_PE
;
3495 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe
*pe
)
3497 struct pnv_phb
*phb
= pe
->phb
;
3499 if (phb
->type
== PNV_PHB_IODA1
) {
3500 pnv_ioda_free_pe_seg(pe
, OPAL_IO_WINDOW_TYPE
,
3501 phb
->ioda
.io_segmap
);
3502 pnv_ioda_free_pe_seg(pe
, OPAL_M32_WINDOW_TYPE
,
3503 phb
->ioda
.m32_segmap
);
3504 pnv_ioda_free_pe_seg(pe
, OPAL_M64_WINDOW_TYPE
,
3505 phb
->ioda
.m64_segmap
);
3506 } else if (phb
->type
== PNV_PHB_IODA2
) {
3507 pnv_ioda_free_pe_seg(pe
, OPAL_M32_WINDOW_TYPE
,
3508 phb
->ioda
.m32_segmap
);
3512 static void pnv_ioda_release_pe(struct pnv_ioda_pe
*pe
)
3514 struct pnv_phb
*phb
= pe
->phb
;
3515 struct pnv_ioda_pe
*slave
, *tmp
;
3517 list_del(&pe
->list
);
3518 switch (phb
->type
) {
3520 pnv_pci_ioda1_release_pe_dma(pe
);
3523 pnv_pci_ioda2_release_pe_dma(pe
);
3529 pnv_ioda_release_pe_seg(pe
);
3530 pnv_ioda_deconfigure_pe(pe
->phb
, pe
);
3532 /* Release slave PEs in the compound PE */
3533 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
3534 list_for_each_entry_safe(slave
, tmp
, &pe
->slaves
, list
) {
3535 list_del(&slave
->list
);
3536 pnv_ioda_free_pe(slave
);
3541 * The PE for root bus can be removed because of hotplug in EEH
3542 * recovery for fenced PHB error. We need to mark the PE dead so
3543 * that it can be populated again in PCI hot add path. The PE
3544 * shouldn't be destroyed as it's the global reserved resource.
3546 if (phb
->ioda
.root_pe_populated
&&
3547 phb
->ioda
.root_pe_idx
== pe
->pe_number
)
3548 phb
->ioda
.root_pe_populated
= false;
3550 pnv_ioda_free_pe(pe
);
3553 static void pnv_pci_release_device(struct pci_dev
*pdev
)
3555 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
3556 struct pnv_phb
*phb
= hose
->private_data
;
3557 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
3558 struct pnv_ioda_pe
*pe
;
3560 if (pdev
->is_virtfn
)
3563 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
3567 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3568 * isn't removed and added afterwards in this scenario. We should
3569 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3570 * device count is decreased on removing devices while failing to
3571 * be increased on adding devices. It leads to unbalanced PE's device
3572 * count and eventually make normal PCI hotplug path broken.
3574 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
3575 pdn
->pe_number
= IODA_INVALID_PE
;
3577 WARN_ON(--pe
->device_count
< 0);
3578 if (pe
->device_count
== 0)
3579 pnv_ioda_release_pe(pe
);
3582 static void pnv_npu_disable_device(struct pci_dev
*pdev
)
3584 struct eeh_dev
*edev
= pci_dev_to_eeh_dev(pdev
);
3585 struct eeh_pe
*eehpe
= edev
? edev
->pe
: NULL
;
3587 if (eehpe
&& eeh_ops
&& eeh_ops
->reset
)
3588 eeh_ops
->reset(eehpe
, EEH_RESET_HOT
);
3591 static void pnv_pci_ioda_shutdown(struct pci_controller
*hose
)
3593 struct pnv_phb
*phb
= hose
->private_data
;
3595 opal_pci_reset(phb
->opal_id
, OPAL_RESET_PCI_IODA_TABLE
,
3599 static const struct pci_controller_ops pnv_pci_ioda_controller_ops
= {
3600 .dma_dev_setup
= pnv_pci_dma_dev_setup
,
3601 .dma_bus_setup
= pnv_pci_dma_bus_setup
,
3602 .iommu_bypass_supported
= pnv_pci_ioda_iommu_bypass_supported
,
3603 .setup_msi_irqs
= pnv_setup_msi_irqs
,
3604 .teardown_msi_irqs
= pnv_teardown_msi_irqs
,
3605 .enable_device_hook
= pnv_pci_enable_device_hook
,
3606 .release_device
= pnv_pci_release_device
,
3607 .window_alignment
= pnv_pci_window_alignment
,
3608 .setup_bridge
= pnv_pci_setup_bridge
,
3609 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3610 .shutdown
= pnv_pci_ioda_shutdown
,
3613 static const struct pci_controller_ops pnv_npu_ioda_controller_ops
= {
3614 .dma_dev_setup
= pnv_pci_dma_dev_setup
,
3615 .setup_msi_irqs
= pnv_setup_msi_irqs
,
3616 .teardown_msi_irqs
= pnv_teardown_msi_irqs
,
3617 .enable_device_hook
= pnv_pci_enable_device_hook
,
3618 .window_alignment
= pnv_pci_window_alignment
,
3619 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3620 .shutdown
= pnv_pci_ioda_shutdown
,
3621 .disable_device
= pnv_npu_disable_device
,
3624 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops
= {
3625 .enable_device_hook
= pnv_pci_enable_device_hook
,
3626 .window_alignment
= pnv_pci_window_alignment
,
3627 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3628 .shutdown
= pnv_pci_ioda_shutdown
,
3631 static void __init
pnv_pci_init_ioda_phb(struct device_node
*np
,
3632 u64 hub_id
, int ioda_type
)
3634 struct pci_controller
*hose
;
3635 struct pnv_phb
*phb
;
3636 unsigned long size
, m64map_off
, m32map_off
, pemap_off
;
3637 unsigned long iomap_off
= 0, dma32map_off
= 0;
3639 const __be64
*prop64
;
3640 const __be32
*prop32
;
3647 if (!of_device_is_available(np
))
3650 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names
[ioda_type
], np
);
3652 prop64
= of_get_property(np
, "ibm,opal-phbid", NULL
);
3654 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3657 phb_id
= be64_to_cpup(prop64
);
3658 pr_debug(" PHB-ID : 0x%016llx\n", phb_id
);
3660 phb
= memblock_alloc(sizeof(*phb
), SMP_CACHE_BYTES
);
3662 panic("%s: Failed to allocate %zu bytes\n", __func__
,
3665 /* Allocate PCI controller */
3666 phb
->hose
= hose
= pcibios_alloc_controller(np
);
3668 pr_err(" Can't allocate PCI controller for %pOF\n",
3670 memblock_free(__pa(phb
), sizeof(struct pnv_phb
));
3674 spin_lock_init(&phb
->lock
);
3675 prop32
= of_get_property(np
, "bus-range", &len
);
3676 if (prop32
&& len
== 8) {
3677 hose
->first_busno
= be32_to_cpu(prop32
[0]);
3678 hose
->last_busno
= be32_to_cpu(prop32
[1]);
3680 pr_warn(" Broken <bus-range> on %pOF\n", np
);
3681 hose
->first_busno
= 0;
3682 hose
->last_busno
= 0xff;
3684 hose
->private_data
= phb
;
3685 phb
->hub_id
= hub_id
;
3686 phb
->opal_id
= phb_id
;
3687 phb
->type
= ioda_type
;
3688 mutex_init(&phb
->ioda
.pe_alloc_mutex
);
3690 /* Detect specific models for error handling */
3691 if (of_device_is_compatible(np
, "ibm,p7ioc-pciex"))
3692 phb
->model
= PNV_PHB_MODEL_P7IOC
;
3693 else if (of_device_is_compatible(np
, "ibm,power8-pciex"))
3694 phb
->model
= PNV_PHB_MODEL_PHB3
;
3695 else if (of_device_is_compatible(np
, "ibm,power8-npu-pciex"))
3696 phb
->model
= PNV_PHB_MODEL_NPU
;
3697 else if (of_device_is_compatible(np
, "ibm,power9-npu-pciex"))
3698 phb
->model
= PNV_PHB_MODEL_NPU2
;
3700 phb
->model
= PNV_PHB_MODEL_UNKNOWN
;
3702 /* Initialize diagnostic data buffer */
3703 prop32
= of_get_property(np
, "ibm,phb-diag-data-size", NULL
);
3705 phb
->diag_data_size
= be32_to_cpup(prop32
);
3707 phb
->diag_data_size
= PNV_PCI_DIAG_BUF_SIZE
;
3709 phb
->diag_data
= memblock_alloc(phb
->diag_data_size
, SMP_CACHE_BYTES
);
3710 if (!phb
->diag_data
)
3711 panic("%s: Failed to allocate %u bytes\n", __func__
,
3712 phb
->diag_data_size
);
3714 /* Parse 32-bit and IO ranges (if any) */
3715 pci_process_bridge_OF_ranges(hose
, np
, !hose
->global_number
);
3718 if (!of_address_to_resource(np
, 0, &r
)) {
3719 phb
->regs_phys
= r
.start
;
3720 phb
->regs
= ioremap(r
.start
, resource_size(&r
));
3721 if (phb
->regs
== NULL
)
3722 pr_err(" Failed to map registers !\n");
3725 /* Initialize more IODA stuff */
3726 phb
->ioda
.total_pe_num
= 1;
3727 prop32
= of_get_property(np
, "ibm,opal-num-pes", NULL
);
3729 phb
->ioda
.total_pe_num
= be32_to_cpup(prop32
);
3730 prop32
= of_get_property(np
, "ibm,opal-reserved-pe", NULL
);
3732 phb
->ioda
.reserved_pe_idx
= be32_to_cpup(prop32
);
3734 /* Invalidate RID to PE# mapping */
3735 for (segno
= 0; segno
< ARRAY_SIZE(phb
->ioda
.pe_rmap
); segno
++)
3736 phb
->ioda
.pe_rmap
[segno
] = IODA_INVALID_PE
;
3738 /* Parse 64-bit MMIO range */
3739 pnv_ioda_parse_m64_window(phb
);
3741 phb
->ioda
.m32_size
= resource_size(&hose
->mem_resources
[0]);
3742 /* FW Has already off top 64k of M32 space (MSI space) */
3743 phb
->ioda
.m32_size
+= 0x10000;
3745 phb
->ioda
.m32_segsize
= phb
->ioda
.m32_size
/ phb
->ioda
.total_pe_num
;
3746 phb
->ioda
.m32_pci_base
= hose
->mem_resources
[0].start
- hose
->mem_offset
[0];
3747 phb
->ioda
.io_size
= hose
->pci_io_size
;
3748 phb
->ioda
.io_segsize
= phb
->ioda
.io_size
/ phb
->ioda
.total_pe_num
;
3749 phb
->ioda
.io_pci_base
= 0; /* XXX calculate this ? */
3751 /* Calculate how many 32-bit TCE segments we have */
3752 phb
->ioda
.dma32_count
= phb
->ioda
.m32_pci_base
/
3753 PNV_IODA1_DMA32_SEGSIZE
;
3755 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3756 size
= _ALIGN_UP(max_t(unsigned, phb
->ioda
.total_pe_num
, 8) / 8,
3757 sizeof(unsigned long));
3759 size
+= phb
->ioda
.total_pe_num
* sizeof(phb
->ioda
.m64_segmap
[0]);
3761 size
+= phb
->ioda
.total_pe_num
* sizeof(phb
->ioda
.m32_segmap
[0]);
3762 if (phb
->type
== PNV_PHB_IODA1
) {
3764 size
+= phb
->ioda
.total_pe_num
* sizeof(phb
->ioda
.io_segmap
[0]);
3765 dma32map_off
= size
;
3766 size
+= phb
->ioda
.dma32_count
*
3767 sizeof(phb
->ioda
.dma32_segmap
[0]);
3770 size
+= phb
->ioda
.total_pe_num
* sizeof(struct pnv_ioda_pe
);
3771 aux
= memblock_alloc(size
, SMP_CACHE_BYTES
);
3773 panic("%s: Failed to allocate %lu bytes\n", __func__
, size
);
3774 phb
->ioda
.pe_alloc
= aux
;
3775 phb
->ioda
.m64_segmap
= aux
+ m64map_off
;
3776 phb
->ioda
.m32_segmap
= aux
+ m32map_off
;
3777 for (segno
= 0; segno
< phb
->ioda
.total_pe_num
; segno
++) {
3778 phb
->ioda
.m64_segmap
[segno
] = IODA_INVALID_PE
;
3779 phb
->ioda
.m32_segmap
[segno
] = IODA_INVALID_PE
;
3781 if (phb
->type
== PNV_PHB_IODA1
) {
3782 phb
->ioda
.io_segmap
= aux
+ iomap_off
;
3783 for (segno
= 0; segno
< phb
->ioda
.total_pe_num
; segno
++)
3784 phb
->ioda
.io_segmap
[segno
] = IODA_INVALID_PE
;
3786 phb
->ioda
.dma32_segmap
= aux
+ dma32map_off
;
3787 for (segno
= 0; segno
< phb
->ioda
.dma32_count
; segno
++)
3788 phb
->ioda
.dma32_segmap
[segno
] = IODA_INVALID_PE
;
3790 phb
->ioda
.pe_array
= aux
+ pemap_off
;
3793 * Choose PE number for root bus, which shouldn't have
3794 * M64 resources consumed by its child devices. To pick
3795 * the PE number adjacent to the reserved one if possible.
3797 pnv_ioda_reserve_pe(phb
, phb
->ioda
.reserved_pe_idx
);
3798 if (phb
->ioda
.reserved_pe_idx
== 0) {
3799 phb
->ioda
.root_pe_idx
= 1;
3800 pnv_ioda_reserve_pe(phb
, phb
->ioda
.root_pe_idx
);
3801 } else if (phb
->ioda
.reserved_pe_idx
== (phb
->ioda
.total_pe_num
- 1)) {
3802 phb
->ioda
.root_pe_idx
= phb
->ioda
.reserved_pe_idx
- 1;
3803 pnv_ioda_reserve_pe(phb
, phb
->ioda
.root_pe_idx
);
3805 phb
->ioda
.root_pe_idx
= IODA_INVALID_PE
;
3808 INIT_LIST_HEAD(&phb
->ioda
.pe_list
);
3809 mutex_init(&phb
->ioda
.pe_list_mutex
);
3811 /* Calculate how many 32-bit TCE segments we have */
3812 phb
->ioda
.dma32_count
= phb
->ioda
.m32_pci_base
/
3813 PNV_IODA1_DMA32_SEGSIZE
;
3815 #if 0 /* We should really do that ... */
3816 rc
= opal_pci_set_phb_mem_window(opal
->phb_id
,
3819 starting_real_address
,
3820 starting_pci_address
,
3824 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3825 phb
->ioda
.total_pe_num
, phb
->ioda
.reserved_pe_idx
,
3826 phb
->ioda
.m32_size
, phb
->ioda
.m32_segsize
);
3827 if (phb
->ioda
.m64_size
)
3828 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3829 phb
->ioda
.m64_size
, phb
->ioda
.m64_segsize
);
3830 if (phb
->ioda
.io_size
)
3831 pr_info(" IO: 0x%x [segment=0x%x]\n",
3832 phb
->ioda
.io_size
, phb
->ioda
.io_segsize
);
3835 phb
->hose
->ops
= &pnv_pci_ops
;
3836 phb
->get_pe_state
= pnv_ioda_get_pe_state
;
3837 phb
->freeze_pe
= pnv_ioda_freeze_pe
;
3838 phb
->unfreeze_pe
= pnv_ioda_unfreeze_pe
;
3840 /* Setup MSI support */
3841 pnv_pci_init_ioda_msis(phb
);
3844 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3845 * to let the PCI core do resource assignment. It's supposed
3846 * that the PCI core will do correct I/O and MMIO alignment
3847 * for the P2P bridge bars so that each PCI bus (excluding
3848 * the child P2P bridges) can form individual PE.
3850 ppc_md
.pcibios_fixup
= pnv_pci_ioda_fixup
;
3852 switch (phb
->type
) {
3853 case PNV_PHB_NPU_NVLINK
:
3854 hose
->controller_ops
= pnv_npu_ioda_controller_ops
;
3856 case PNV_PHB_NPU_OCAPI
:
3857 hose
->controller_ops
= pnv_npu_ocapi_ioda_controller_ops
;
3860 phb
->dma_dev_setup
= pnv_pci_ioda_dma_dev_setup
;
3861 hose
->controller_ops
= pnv_pci_ioda_controller_ops
;
3864 ppc_md
.pcibios_default_alignment
= pnv_pci_default_alignment
;
3866 #ifdef CONFIG_PCI_IOV
3867 ppc_md
.pcibios_fixup_sriov
= pnv_pci_ioda_fixup_iov_resources
;
3868 ppc_md
.pcibios_iov_resource_alignment
= pnv_pci_iov_resource_alignment
;
3869 ppc_md
.pcibios_sriov_enable
= pnv_pcibios_sriov_enable
;
3870 ppc_md
.pcibios_sriov_disable
= pnv_pcibios_sriov_disable
;
3873 pci_add_flags(PCI_REASSIGN_ALL_RSRC
);
3875 /* Reset IODA tables to a clean state */
3876 rc
= opal_pci_reset(phb_id
, OPAL_RESET_PCI_IODA_TABLE
, OPAL_ASSERT_RESET
);
3878 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc
);
3881 * If we're running in kdump kernel, the previous kernel never
3882 * shutdown PCI devices correctly. We already got IODA table
3883 * cleaned out. So we have to issue PHB reset to stop all PCI
3884 * transactions from previous kernel. The ppc_pci_reset_phbs
3885 * kernel parameter will force this reset too. Additionally,
3886 * if the IODA reset above failed then use a bigger hammer.
3887 * This can happen if we get a PHB fatal error in very early
3890 if (is_kdump_kernel() || pci_reset_phbs
|| rc
) {
3891 pr_info(" Issue PHB reset ...\n");
3892 pnv_eeh_phb_reset(hose
, EEH_RESET_FUNDAMENTAL
);
3893 pnv_eeh_phb_reset(hose
, EEH_RESET_DEACTIVATE
);
3896 /* Remove M64 resource if we can't configure it successfully */
3897 if (!phb
->init_m64
|| phb
->init_m64(phb
))
3898 hose
->mem_resources
[1].flags
= 0;
3901 void __init
pnv_pci_init_ioda2_phb(struct device_node
*np
)
3903 pnv_pci_init_ioda_phb(np
, 0, PNV_PHB_IODA2
);
3906 void __init
pnv_pci_init_npu_phb(struct device_node
*np
)
3908 pnv_pci_init_ioda_phb(np
, 0, PNV_PHB_NPU_NVLINK
);
3911 void __init
pnv_pci_init_npu2_opencapi_phb(struct device_node
*np
)
3913 pnv_pci_init_ioda_phb(np
, 0, PNV_PHB_NPU_OCAPI
);
3916 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev
*dev
)
3918 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
3919 struct pnv_phb
*phb
= hose
->private_data
;
3921 if (!machine_is(powernv
))
3924 if (phb
->type
== PNV_PHB_NPU_OCAPI
)
3925 dev
->cfg_size
= PCI_CFG_SPACE_EXP_SIZE
;
3927 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID
, PCI_ANY_ID
, pnv_npu2_opencapi_cfg_size_fixup
);
3929 void __init
pnv_pci_init_ioda_hub(struct device_node
*np
)
3931 struct device_node
*phbn
;
3932 const __be64
*prop64
;
3935 pr_info("Probing IODA IO-Hub %pOF\n", np
);
3937 prop64
= of_get_property(np
, "ibm,opal-hubid", NULL
);
3939 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3942 hub_id
= be64_to_cpup(prop64
);
3943 pr_devel(" HUB-ID : 0x%016llx\n", hub_id
);
3945 /* Count child PHBs */
3946 for_each_child_of_node(np
, phbn
) {
3947 /* Look for IODA1 PHBs */
3948 if (of_device_is_compatible(phbn
, "ibm,ioda-phb"))
3949 pnv_pci_init_ioda_phb(phbn
, hub_id
, PNV_PHB_IODA1
);