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Merge branch 'turbostat' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux
[mirror_ubuntu-focal-kernel.git] / arch / powerpc / platforms / powernv / pci-ioda.c
1 /*
2 * Support PCI/PCIe on PowerNV platforms
3 *
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #undef DEBUG
13
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/memblock.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23 #include <linux/msi.h>
24 #include <linux/iommu.h>
25 #include <linux/rculist.h>
26 #include <linux/sizes.h>
27
28 #include <asm/sections.h>
29 #include <asm/io.h>
30 #include <asm/prom.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/machdep.h>
33 #include <asm/msi_bitmap.h>
34 #include <asm/ppc-pci.h>
35 #include <asm/opal.h>
36 #include <asm/iommu.h>
37 #include <asm/tce.h>
38 #include <asm/xics.h>
39 #include <asm/debugfs.h>
40 #include <asm/firmware.h>
41 #include <asm/pnv-pci.h>
42 #include <asm/mmzone.h>
43
44 #include <misc/cxl-base.h>
45
46 #include "powernv.h"
47 #include "pci.h"
48 #include "../../../../drivers/pci/pci.h"
49
50 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
51 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
53
54 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
55 "NPU_OCAPI" };
56
57 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
58 const char *fmt, ...)
59 {
60 struct va_format vaf;
61 va_list args;
62 char pfix[32];
63
64 va_start(args, fmt);
65
66 vaf.fmt = fmt;
67 vaf.va = &args;
68
69 if (pe->flags & PNV_IODA_PE_DEV)
70 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
71 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
72 sprintf(pfix, "%04x:%02x ",
73 pci_domain_nr(pe->pbus), pe->pbus->number);
74 #ifdef CONFIG_PCI_IOV
75 else if (pe->flags & PNV_IODA_PE_VF)
76 sprintf(pfix, "%04x:%02x:%2x.%d",
77 pci_domain_nr(pe->parent_dev->bus),
78 (pe->rid & 0xff00) >> 8,
79 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
80 #endif /* CONFIG_PCI_IOV*/
81
82 printk("%spci %s: [PE# %.2x] %pV",
83 level, pfix, pe->pe_number, &vaf);
84
85 va_end(args);
86 }
87
88 static bool pnv_iommu_bypass_disabled __read_mostly;
89 static bool pci_reset_phbs __read_mostly;
90
91 static int __init iommu_setup(char *str)
92 {
93 if (!str)
94 return -EINVAL;
95
96 while (*str) {
97 if (!strncmp(str, "nobypass", 8)) {
98 pnv_iommu_bypass_disabled = true;
99 pr_info("PowerNV: IOMMU bypass window disabled.\n");
100 break;
101 }
102 str += strcspn(str, ",");
103 if (*str == ',')
104 str++;
105 }
106
107 return 0;
108 }
109 early_param("iommu", iommu_setup);
110
111 static int __init pci_reset_phbs_setup(char *str)
112 {
113 pci_reset_phbs = true;
114 return 0;
115 }
116
117 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
118
119 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
120 {
121 /*
122 * WARNING: We cannot rely on the resource flags. The Linux PCI
123 * allocation code sometimes decides to put a 64-bit prefetchable
124 * BAR in the 32-bit window, so we have to compare the addresses.
125 *
126 * For simplicity we only test resource start.
127 */
128 return (r->start >= phb->ioda.m64_base &&
129 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
130 }
131
132 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
133 {
134 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
135
136 return (resource_flags & flags) == flags;
137 }
138
139 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
140 {
141 s64 rc;
142
143 phb->ioda.pe_array[pe_no].phb = phb;
144 phb->ioda.pe_array[pe_no].pe_number = pe_no;
145
146 /*
147 * Clear the PE frozen state as it might be put into frozen state
148 * in the last PCI remove path. It's not harmful to do so when the
149 * PE is already in unfrozen state.
150 */
151 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
152 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
153 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
154 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
155 __func__, rc, phb->hose->global_number, pe_no);
156
157 return &phb->ioda.pe_array[pe_no];
158 }
159
160 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
161 {
162 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
163 pr_warn("%s: Invalid PE %x on PHB#%x\n",
164 __func__, pe_no, phb->hose->global_number);
165 return;
166 }
167
168 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
169 pr_debug("%s: PE %x was reserved on PHB#%x\n",
170 __func__, pe_no, phb->hose->global_number);
171
172 pnv_ioda_init_pe(phb, pe_no);
173 }
174
175 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
176 {
177 long pe;
178
179 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
180 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
181 return pnv_ioda_init_pe(phb, pe);
182 }
183
184 return NULL;
185 }
186
187 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
188 {
189 struct pnv_phb *phb = pe->phb;
190 unsigned int pe_num = pe->pe_number;
191
192 WARN_ON(pe->pdev);
193 WARN_ON(pe->npucomp); /* NPUs are not supposed to be freed */
194 kfree(pe->npucomp);
195 memset(pe, 0, sizeof(struct pnv_ioda_pe));
196 clear_bit(pe_num, phb->ioda.pe_alloc);
197 }
198
199 /* The default M64 BAR is shared by all PEs */
200 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
201 {
202 const char *desc;
203 struct resource *r;
204 s64 rc;
205
206 /* Configure the default M64 BAR */
207 rc = opal_pci_set_phb_mem_window(phb->opal_id,
208 OPAL_M64_WINDOW_TYPE,
209 phb->ioda.m64_bar_idx,
210 phb->ioda.m64_base,
211 0, /* unused */
212 phb->ioda.m64_size);
213 if (rc != OPAL_SUCCESS) {
214 desc = "configuring";
215 goto fail;
216 }
217
218 /* Enable the default M64 BAR */
219 rc = opal_pci_phb_mmio_enable(phb->opal_id,
220 OPAL_M64_WINDOW_TYPE,
221 phb->ioda.m64_bar_idx,
222 OPAL_ENABLE_M64_SPLIT);
223 if (rc != OPAL_SUCCESS) {
224 desc = "enabling";
225 goto fail;
226 }
227
228 /*
229 * Exclude the segments for reserved and root bus PE, which
230 * are first or last two PEs.
231 */
232 r = &phb->hose->mem_resources[1];
233 if (phb->ioda.reserved_pe_idx == 0)
234 r->start += (2 * phb->ioda.m64_segsize);
235 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
236 r->end -= (2 * phb->ioda.m64_segsize);
237 else
238 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
239 phb->ioda.reserved_pe_idx);
240
241 return 0;
242
243 fail:
244 pr_warn(" Failure %lld %s M64 BAR#%d\n",
245 rc, desc, phb->ioda.m64_bar_idx);
246 opal_pci_phb_mmio_enable(phb->opal_id,
247 OPAL_M64_WINDOW_TYPE,
248 phb->ioda.m64_bar_idx,
249 OPAL_DISABLE_M64);
250 return -EIO;
251 }
252
253 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
254 unsigned long *pe_bitmap)
255 {
256 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
257 struct pnv_phb *phb = hose->private_data;
258 struct resource *r;
259 resource_size_t base, sgsz, start, end;
260 int segno, i;
261
262 base = phb->ioda.m64_base;
263 sgsz = phb->ioda.m64_segsize;
264 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
265 r = &pdev->resource[i];
266 if (!r->parent || !pnv_pci_is_m64(phb, r))
267 continue;
268
269 start = _ALIGN_DOWN(r->start - base, sgsz);
270 end = _ALIGN_UP(r->end - base, sgsz);
271 for (segno = start / sgsz; segno < end / sgsz; segno++) {
272 if (pe_bitmap)
273 set_bit(segno, pe_bitmap);
274 else
275 pnv_ioda_reserve_pe(phb, segno);
276 }
277 }
278 }
279
280 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
281 {
282 struct resource *r;
283 int index;
284
285 /*
286 * There are 16 M64 BARs, each of which has 8 segments. So
287 * there are as many M64 segments as the maximum number of
288 * PEs, which is 128.
289 */
290 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
291 unsigned long base, segsz = phb->ioda.m64_segsize;
292 int64_t rc;
293
294 base = phb->ioda.m64_base +
295 index * PNV_IODA1_M64_SEGS * segsz;
296 rc = opal_pci_set_phb_mem_window(phb->opal_id,
297 OPAL_M64_WINDOW_TYPE, index, base, 0,
298 PNV_IODA1_M64_SEGS * segsz);
299 if (rc != OPAL_SUCCESS) {
300 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
301 rc, phb->hose->global_number, index);
302 goto fail;
303 }
304
305 rc = opal_pci_phb_mmio_enable(phb->opal_id,
306 OPAL_M64_WINDOW_TYPE, index,
307 OPAL_ENABLE_M64_SPLIT);
308 if (rc != OPAL_SUCCESS) {
309 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
310 rc, phb->hose->global_number, index);
311 goto fail;
312 }
313 }
314
315 /*
316 * Exclude the segments for reserved and root bus PE, which
317 * are first or last two PEs.
318 */
319 r = &phb->hose->mem_resources[1];
320 if (phb->ioda.reserved_pe_idx == 0)
321 r->start += (2 * phb->ioda.m64_segsize);
322 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
323 r->end -= (2 * phb->ioda.m64_segsize);
324 else
325 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
326 phb->ioda.reserved_pe_idx, phb->hose->global_number);
327
328 return 0;
329
330 fail:
331 for ( ; index >= 0; index--)
332 opal_pci_phb_mmio_enable(phb->opal_id,
333 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
334
335 return -EIO;
336 }
337
338 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
339 unsigned long *pe_bitmap,
340 bool all)
341 {
342 struct pci_dev *pdev;
343
344 list_for_each_entry(pdev, &bus->devices, bus_list) {
345 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
346
347 if (all && pdev->subordinate)
348 pnv_ioda_reserve_m64_pe(pdev->subordinate,
349 pe_bitmap, all);
350 }
351 }
352
353 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
354 {
355 struct pci_controller *hose = pci_bus_to_host(bus);
356 struct pnv_phb *phb = hose->private_data;
357 struct pnv_ioda_pe *master_pe, *pe;
358 unsigned long size, *pe_alloc;
359 int i;
360
361 /* Root bus shouldn't use M64 */
362 if (pci_is_root_bus(bus))
363 return NULL;
364
365 /* Allocate bitmap */
366 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
367 pe_alloc = kzalloc(size, GFP_KERNEL);
368 if (!pe_alloc) {
369 pr_warn("%s: Out of memory !\n",
370 __func__);
371 return NULL;
372 }
373
374 /* Figure out reserved PE numbers by the PE */
375 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
376
377 /*
378 * the current bus might not own M64 window and that's all
379 * contributed by its child buses. For the case, we needn't
380 * pick M64 dependent PE#.
381 */
382 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
383 kfree(pe_alloc);
384 return NULL;
385 }
386
387 /*
388 * Figure out the master PE and put all slave PEs to master
389 * PE's list to form compound PE.
390 */
391 master_pe = NULL;
392 i = -1;
393 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
394 phb->ioda.total_pe_num) {
395 pe = &phb->ioda.pe_array[i];
396
397 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
398 if (!master_pe) {
399 pe->flags |= PNV_IODA_PE_MASTER;
400 INIT_LIST_HEAD(&pe->slaves);
401 master_pe = pe;
402 } else {
403 pe->flags |= PNV_IODA_PE_SLAVE;
404 pe->master = master_pe;
405 list_add_tail(&pe->list, &master_pe->slaves);
406 }
407
408 /*
409 * P7IOC supports M64DT, which helps mapping M64 segment
410 * to one particular PE#. However, PHB3 has fixed mapping
411 * between M64 segment and PE#. In order to have same logic
412 * for P7IOC and PHB3, we enforce fixed mapping between M64
413 * segment and PE# on P7IOC.
414 */
415 if (phb->type == PNV_PHB_IODA1) {
416 int64_t rc;
417
418 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
419 pe->pe_number, OPAL_M64_WINDOW_TYPE,
420 pe->pe_number / PNV_IODA1_M64_SEGS,
421 pe->pe_number % PNV_IODA1_M64_SEGS);
422 if (rc != OPAL_SUCCESS)
423 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
424 __func__, rc, phb->hose->global_number,
425 pe->pe_number);
426 }
427 }
428
429 kfree(pe_alloc);
430 return master_pe;
431 }
432
433 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
434 {
435 struct pci_controller *hose = phb->hose;
436 struct device_node *dn = hose->dn;
437 struct resource *res;
438 u32 m64_range[2], i;
439 const __be32 *r;
440 u64 pci_addr;
441
442 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
443 pr_info(" Not support M64 window\n");
444 return;
445 }
446
447 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
448 pr_info(" Firmware too old to support M64 window\n");
449 return;
450 }
451
452 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
453 if (!r) {
454 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
455 dn);
456 return;
457 }
458
459 /*
460 * Find the available M64 BAR range and pickup the last one for
461 * covering the whole 64-bits space. We support only one range.
462 */
463 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
464 m64_range, 2)) {
465 /* In absence of the property, assume 0..15 */
466 m64_range[0] = 0;
467 m64_range[1] = 16;
468 }
469 /* We only support 64 bits in our allocator */
470 if (m64_range[1] > 63) {
471 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
472 __func__, m64_range[1], phb->hose->global_number);
473 m64_range[1] = 63;
474 }
475 /* Empty range, no m64 */
476 if (m64_range[1] <= m64_range[0]) {
477 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
478 __func__, phb->hose->global_number);
479 return;
480 }
481
482 /* Configure M64 informations */
483 res = &hose->mem_resources[1];
484 res->name = dn->full_name;
485 res->start = of_translate_address(dn, r + 2);
486 res->end = res->start + of_read_number(r + 4, 2) - 1;
487 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
488 pci_addr = of_read_number(r, 2);
489 hose->mem_offset[1] = res->start - pci_addr;
490
491 phb->ioda.m64_size = resource_size(res);
492 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
493 phb->ioda.m64_base = pci_addr;
494
495 /* This lines up nicely with the display from processing OF ranges */
496 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
497 res->start, res->end, pci_addr, m64_range[0],
498 m64_range[0] + m64_range[1] - 1);
499
500 /* Mark all M64 used up by default */
501 phb->ioda.m64_bar_alloc = (unsigned long)-1;
502
503 /* Use last M64 BAR to cover M64 window */
504 m64_range[1]--;
505 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
506
507 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
508
509 /* Mark remaining ones free */
510 for (i = m64_range[0]; i < m64_range[1]; i++)
511 clear_bit(i, &phb->ioda.m64_bar_alloc);
512
513 /*
514 * Setup init functions for M64 based on IODA version, IODA3 uses
515 * the IODA2 code.
516 */
517 if (phb->type == PNV_PHB_IODA1)
518 phb->init_m64 = pnv_ioda1_init_m64;
519 else
520 phb->init_m64 = pnv_ioda2_init_m64;
521 }
522
523 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
524 {
525 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
526 struct pnv_ioda_pe *slave;
527 s64 rc;
528
529 /* Fetch master PE */
530 if (pe->flags & PNV_IODA_PE_SLAVE) {
531 pe = pe->master;
532 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
533 return;
534
535 pe_no = pe->pe_number;
536 }
537
538 /* Freeze master PE */
539 rc = opal_pci_eeh_freeze_set(phb->opal_id,
540 pe_no,
541 OPAL_EEH_ACTION_SET_FREEZE_ALL);
542 if (rc != OPAL_SUCCESS) {
543 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
544 __func__, rc, phb->hose->global_number, pe_no);
545 return;
546 }
547
548 /* Freeze slave PEs */
549 if (!(pe->flags & PNV_IODA_PE_MASTER))
550 return;
551
552 list_for_each_entry(slave, &pe->slaves, list) {
553 rc = opal_pci_eeh_freeze_set(phb->opal_id,
554 slave->pe_number,
555 OPAL_EEH_ACTION_SET_FREEZE_ALL);
556 if (rc != OPAL_SUCCESS)
557 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
558 __func__, rc, phb->hose->global_number,
559 slave->pe_number);
560 }
561 }
562
563 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
564 {
565 struct pnv_ioda_pe *pe, *slave;
566 s64 rc;
567
568 /* Find master PE */
569 pe = &phb->ioda.pe_array[pe_no];
570 if (pe->flags & PNV_IODA_PE_SLAVE) {
571 pe = pe->master;
572 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
573 pe_no = pe->pe_number;
574 }
575
576 /* Clear frozen state for master PE */
577 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
578 if (rc != OPAL_SUCCESS) {
579 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
580 __func__, rc, opt, phb->hose->global_number, pe_no);
581 return -EIO;
582 }
583
584 if (!(pe->flags & PNV_IODA_PE_MASTER))
585 return 0;
586
587 /* Clear frozen state for slave PEs */
588 list_for_each_entry(slave, &pe->slaves, list) {
589 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
590 slave->pe_number,
591 opt);
592 if (rc != OPAL_SUCCESS) {
593 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
594 __func__, rc, opt, phb->hose->global_number,
595 slave->pe_number);
596 return -EIO;
597 }
598 }
599
600 return 0;
601 }
602
603 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
604 {
605 struct pnv_ioda_pe *slave, *pe;
606 u8 fstate = 0, state;
607 __be16 pcierr = 0;
608 s64 rc;
609
610 /* Sanity check on PE number */
611 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
612 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
613
614 /*
615 * Fetch the master PE and the PE instance might be
616 * not initialized yet.
617 */
618 pe = &phb->ioda.pe_array[pe_no];
619 if (pe->flags & PNV_IODA_PE_SLAVE) {
620 pe = pe->master;
621 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
622 pe_no = pe->pe_number;
623 }
624
625 /* Check the master PE */
626 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
627 &state, &pcierr, NULL);
628 if (rc != OPAL_SUCCESS) {
629 pr_warn("%s: Failure %lld getting "
630 "PHB#%x-PE#%x state\n",
631 __func__, rc,
632 phb->hose->global_number, pe_no);
633 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
634 }
635
636 /* Check the slave PE */
637 if (!(pe->flags & PNV_IODA_PE_MASTER))
638 return state;
639
640 list_for_each_entry(slave, &pe->slaves, list) {
641 rc = opal_pci_eeh_freeze_status(phb->opal_id,
642 slave->pe_number,
643 &fstate,
644 &pcierr,
645 NULL);
646 if (rc != OPAL_SUCCESS) {
647 pr_warn("%s: Failure %lld getting "
648 "PHB#%x-PE#%x state\n",
649 __func__, rc,
650 phb->hose->global_number, slave->pe_number);
651 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
652 }
653
654 /*
655 * Override the result based on the ascending
656 * priority.
657 */
658 if (fstate > state)
659 state = fstate;
660 }
661
662 return state;
663 }
664
665 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
666 {
667 struct pci_controller *hose = pci_bus_to_host(dev->bus);
668 struct pnv_phb *phb = hose->private_data;
669 struct pci_dn *pdn = pci_get_pdn(dev);
670
671 if (!pdn)
672 return NULL;
673 if (pdn->pe_number == IODA_INVALID_PE)
674 return NULL;
675 return &phb->ioda.pe_array[pdn->pe_number];
676 }
677
678 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
679 struct pnv_ioda_pe *parent,
680 struct pnv_ioda_pe *child,
681 bool is_add)
682 {
683 const char *desc = is_add ? "adding" : "removing";
684 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
685 OPAL_REMOVE_PE_FROM_DOMAIN;
686 struct pnv_ioda_pe *slave;
687 long rc;
688
689 /* Parent PE affects child PE */
690 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
691 child->pe_number, op);
692 if (rc != OPAL_SUCCESS) {
693 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
694 rc, desc);
695 return -ENXIO;
696 }
697
698 if (!(child->flags & PNV_IODA_PE_MASTER))
699 return 0;
700
701 /* Compound case: parent PE affects slave PEs */
702 list_for_each_entry(slave, &child->slaves, list) {
703 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
704 slave->pe_number, op);
705 if (rc != OPAL_SUCCESS) {
706 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
707 rc, desc);
708 return -ENXIO;
709 }
710 }
711
712 return 0;
713 }
714
715 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
716 struct pnv_ioda_pe *pe,
717 bool is_add)
718 {
719 struct pnv_ioda_pe *slave;
720 struct pci_dev *pdev = NULL;
721 int ret;
722
723 /*
724 * Clear PE frozen state. If it's master PE, we need
725 * clear slave PE frozen state as well.
726 */
727 if (is_add) {
728 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
729 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
730 if (pe->flags & PNV_IODA_PE_MASTER) {
731 list_for_each_entry(slave, &pe->slaves, list)
732 opal_pci_eeh_freeze_clear(phb->opal_id,
733 slave->pe_number,
734 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
735 }
736 }
737
738 /*
739 * Associate PE in PELT. We need add the PE into the
740 * corresponding PELT-V as well. Otherwise, the error
741 * originated from the PE might contribute to other
742 * PEs.
743 */
744 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
745 if (ret)
746 return ret;
747
748 /* For compound PEs, any one affects all of them */
749 if (pe->flags & PNV_IODA_PE_MASTER) {
750 list_for_each_entry(slave, &pe->slaves, list) {
751 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
752 if (ret)
753 return ret;
754 }
755 }
756
757 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
758 pdev = pe->pbus->self;
759 else if (pe->flags & PNV_IODA_PE_DEV)
760 pdev = pe->pdev->bus->self;
761 #ifdef CONFIG_PCI_IOV
762 else if (pe->flags & PNV_IODA_PE_VF)
763 pdev = pe->parent_dev;
764 #endif /* CONFIG_PCI_IOV */
765 while (pdev) {
766 struct pci_dn *pdn = pci_get_pdn(pdev);
767 struct pnv_ioda_pe *parent;
768
769 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
770 parent = &phb->ioda.pe_array[pdn->pe_number];
771 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
772 if (ret)
773 return ret;
774 }
775
776 pdev = pdev->bus->self;
777 }
778
779 return 0;
780 }
781
782 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
783 {
784 struct pci_dev *parent;
785 uint8_t bcomp, dcomp, fcomp;
786 int64_t rc;
787 long rid_end, rid;
788
789 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
790 if (pe->pbus) {
791 int count;
792
793 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
794 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
795 parent = pe->pbus->self;
796 if (pe->flags & PNV_IODA_PE_BUS_ALL)
797 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
798 else
799 count = 1;
800
801 switch(count) {
802 case 1: bcomp = OpalPciBusAll; break;
803 case 2: bcomp = OpalPciBus7Bits; break;
804 case 4: bcomp = OpalPciBus6Bits; break;
805 case 8: bcomp = OpalPciBus5Bits; break;
806 case 16: bcomp = OpalPciBus4Bits; break;
807 case 32: bcomp = OpalPciBus3Bits; break;
808 default:
809 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
810 count);
811 /* Do an exact match only */
812 bcomp = OpalPciBusAll;
813 }
814 rid_end = pe->rid + (count << 8);
815 } else {
816 #ifdef CONFIG_PCI_IOV
817 if (pe->flags & PNV_IODA_PE_VF)
818 parent = pe->parent_dev;
819 else
820 #endif
821 parent = pe->pdev->bus->self;
822 bcomp = OpalPciBusAll;
823 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
824 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
825 rid_end = pe->rid + 1;
826 }
827
828 /* Clear the reverse map */
829 for (rid = pe->rid; rid < rid_end; rid++)
830 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
831
832 /* Release from all parents PELT-V */
833 while (parent) {
834 struct pci_dn *pdn = pci_get_pdn(parent);
835 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
836 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
837 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
838 /* XXX What to do in case of error ? */
839 }
840 parent = parent->bus->self;
841 }
842
843 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
844 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
845
846 /* Disassociate PE in PELT */
847 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
848 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
849 if (rc)
850 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
851 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
852 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
853 if (rc)
854 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
855
856 pe->pbus = NULL;
857 pe->pdev = NULL;
858 #ifdef CONFIG_PCI_IOV
859 pe->parent_dev = NULL;
860 #endif
861
862 return 0;
863 }
864
865 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
866 {
867 struct pci_dev *parent;
868 uint8_t bcomp, dcomp, fcomp;
869 long rc, rid_end, rid;
870
871 /* Bus validation ? */
872 if (pe->pbus) {
873 int count;
874
875 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
876 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
877 parent = pe->pbus->self;
878 if (pe->flags & PNV_IODA_PE_BUS_ALL)
879 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
880 else
881 count = 1;
882
883 switch(count) {
884 case 1: bcomp = OpalPciBusAll; break;
885 case 2: bcomp = OpalPciBus7Bits; break;
886 case 4: bcomp = OpalPciBus6Bits; break;
887 case 8: bcomp = OpalPciBus5Bits; break;
888 case 16: bcomp = OpalPciBus4Bits; break;
889 case 32: bcomp = OpalPciBus3Bits; break;
890 default:
891 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
892 count);
893 /* Do an exact match only */
894 bcomp = OpalPciBusAll;
895 }
896 rid_end = pe->rid + (count << 8);
897 } else {
898 #ifdef CONFIG_PCI_IOV
899 if (pe->flags & PNV_IODA_PE_VF)
900 parent = pe->parent_dev;
901 else
902 #endif /* CONFIG_PCI_IOV */
903 parent = pe->pdev->bus->self;
904 bcomp = OpalPciBusAll;
905 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
906 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
907 rid_end = pe->rid + 1;
908 }
909
910 /*
911 * Associate PE in PELT. We need add the PE into the
912 * corresponding PELT-V as well. Otherwise, the error
913 * originated from the PE might contribute to other
914 * PEs.
915 */
916 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
917 bcomp, dcomp, fcomp, OPAL_MAP_PE);
918 if (rc) {
919 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
920 return -ENXIO;
921 }
922
923 /*
924 * Configure PELTV. NPUs don't have a PELTV table so skip
925 * configuration on them.
926 */
927 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
928 pnv_ioda_set_peltv(phb, pe, true);
929
930 /* Setup reverse map */
931 for (rid = pe->rid; rid < rid_end; rid++)
932 phb->ioda.pe_rmap[rid] = pe->pe_number;
933
934 /* Setup one MVTs on IODA1 */
935 if (phb->type != PNV_PHB_IODA1) {
936 pe->mve_number = 0;
937 goto out;
938 }
939
940 pe->mve_number = pe->pe_number;
941 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
942 if (rc != OPAL_SUCCESS) {
943 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
944 rc, pe->mve_number);
945 pe->mve_number = -1;
946 } else {
947 rc = opal_pci_set_mve_enable(phb->opal_id,
948 pe->mve_number, OPAL_ENABLE_MVE);
949 if (rc) {
950 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
951 rc, pe->mve_number);
952 pe->mve_number = -1;
953 }
954 }
955
956 out:
957 return 0;
958 }
959
960 #ifdef CONFIG_PCI_IOV
961 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
962 {
963 struct pci_dn *pdn = pci_get_pdn(dev);
964 int i;
965 struct resource *res, res2;
966 resource_size_t size;
967 u16 num_vfs;
968
969 if (!dev->is_physfn)
970 return -EINVAL;
971
972 /*
973 * "offset" is in VFs. The M64 windows are sized so that when they
974 * are segmented, each segment is the same size as the IOV BAR.
975 * Each segment is in a separate PE, and the high order bits of the
976 * address are the PE number. Therefore, each VF's BAR is in a
977 * separate PE, and changing the IOV BAR start address changes the
978 * range of PEs the VFs are in.
979 */
980 num_vfs = pdn->num_vfs;
981 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
982 res = &dev->resource[i + PCI_IOV_RESOURCES];
983 if (!res->flags || !res->parent)
984 continue;
985
986 /*
987 * The actual IOV BAR range is determined by the start address
988 * and the actual size for num_vfs VFs BAR. This check is to
989 * make sure that after shifting, the range will not overlap
990 * with another device.
991 */
992 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
993 res2.flags = res->flags;
994 res2.start = res->start + (size * offset);
995 res2.end = res2.start + (size * num_vfs) - 1;
996
997 if (res2.end > res->end) {
998 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
999 i, &res2, res, num_vfs, offset);
1000 return -EBUSY;
1001 }
1002 }
1003
1004 /*
1005 * Since M64 BAR shares segments among all possible 256 PEs,
1006 * we have to shift the beginning of PF IOV BAR to make it start from
1007 * the segment which belongs to the PE number assigned to the first VF.
1008 * This creates a "hole" in the /proc/iomem which could be used for
1009 * allocating other resources so we reserve this area below and
1010 * release when IOV is released.
1011 */
1012 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1013 res = &dev->resource[i + PCI_IOV_RESOURCES];
1014 if (!res->flags || !res->parent)
1015 continue;
1016
1017 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1018 res2 = *res;
1019 res->start += size * offset;
1020
1021 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1022 i, &res2, res, (offset > 0) ? "En" : "Dis",
1023 num_vfs, offset);
1024
1025 if (offset < 0) {
1026 devm_release_resource(&dev->dev, &pdn->holes[i]);
1027 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1028 }
1029
1030 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1031
1032 if (offset > 0) {
1033 pdn->holes[i].start = res2.start;
1034 pdn->holes[i].end = res2.start + size * offset - 1;
1035 pdn->holes[i].flags = IORESOURCE_BUS;
1036 pdn->holes[i].name = "pnv_iov_reserved";
1037 devm_request_resource(&dev->dev, res->parent,
1038 &pdn->holes[i]);
1039 }
1040 }
1041 return 0;
1042 }
1043 #endif /* CONFIG_PCI_IOV */
1044
1045 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1046 {
1047 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1048 struct pnv_phb *phb = hose->private_data;
1049 struct pci_dn *pdn = pci_get_pdn(dev);
1050 struct pnv_ioda_pe *pe;
1051
1052 if (!pdn) {
1053 pr_err("%s: Device tree node not associated properly\n",
1054 pci_name(dev));
1055 return NULL;
1056 }
1057 if (pdn->pe_number != IODA_INVALID_PE)
1058 return NULL;
1059
1060 pe = pnv_ioda_alloc_pe(phb);
1061 if (!pe) {
1062 pr_warn("%s: Not enough PE# available, disabling device\n",
1063 pci_name(dev));
1064 return NULL;
1065 }
1066
1067 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1068 * pointer in the PE data structure, both should be destroyed at the
1069 * same time. However, this needs to be looked at more closely again
1070 * once we actually start removing things (Hotplug, SR-IOV, ...)
1071 *
1072 * At some point we want to remove the PDN completely anyways
1073 */
1074 pci_dev_get(dev);
1075 pdn->pe_number = pe->pe_number;
1076 pe->flags = PNV_IODA_PE_DEV;
1077 pe->pdev = dev;
1078 pe->pbus = NULL;
1079 pe->mve_number = -1;
1080 pe->rid = dev->bus->number << 8 | pdn->devfn;
1081
1082 pe_info(pe, "Associated device to PE\n");
1083
1084 if (pnv_ioda_configure_pe(phb, pe)) {
1085 /* XXX What do we do here ? */
1086 pnv_ioda_free_pe(pe);
1087 pdn->pe_number = IODA_INVALID_PE;
1088 pe->pdev = NULL;
1089 pci_dev_put(dev);
1090 return NULL;
1091 }
1092
1093 /* Put PE to the list */
1094 list_add_tail(&pe->list, &phb->ioda.pe_list);
1095
1096 return pe;
1097 }
1098
1099 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1100 {
1101 struct pci_dev *dev;
1102
1103 list_for_each_entry(dev, &bus->devices, bus_list) {
1104 struct pci_dn *pdn = pci_get_pdn(dev);
1105
1106 if (pdn == NULL) {
1107 pr_warn("%s: No device node associated with device !\n",
1108 pci_name(dev));
1109 continue;
1110 }
1111
1112 /*
1113 * In partial hotplug case, the PCI device might be still
1114 * associated with the PE and needn't attach it to the PE
1115 * again.
1116 */
1117 if (pdn->pe_number != IODA_INVALID_PE)
1118 continue;
1119
1120 pe->device_count++;
1121 pdn->pe_number = pe->pe_number;
1122 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1123 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1124 }
1125 }
1126
1127 /*
1128 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1129 * single PCI bus. Another one that contains the primary PCI bus and its
1130 * subordinate PCI devices and buses. The second type of PE is normally
1131 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1132 */
1133 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1134 {
1135 struct pci_controller *hose = pci_bus_to_host(bus);
1136 struct pnv_phb *phb = hose->private_data;
1137 struct pnv_ioda_pe *pe = NULL;
1138 unsigned int pe_num;
1139
1140 /*
1141 * In partial hotplug case, the PE instance might be still alive.
1142 * We should reuse it instead of allocating a new one.
1143 */
1144 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1145 if (pe_num != IODA_INVALID_PE) {
1146 pe = &phb->ioda.pe_array[pe_num];
1147 pnv_ioda_setup_same_PE(bus, pe);
1148 return NULL;
1149 }
1150
1151 /* PE number for root bus should have been reserved */
1152 if (pci_is_root_bus(bus) &&
1153 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1154 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1155
1156 /* Check if PE is determined by M64 */
1157 if (!pe)
1158 pe = pnv_ioda_pick_m64_pe(bus, all);
1159
1160 /* The PE number isn't pinned by M64 */
1161 if (!pe)
1162 pe = pnv_ioda_alloc_pe(phb);
1163
1164 if (!pe) {
1165 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1166 __func__, pci_domain_nr(bus), bus->number);
1167 return NULL;
1168 }
1169
1170 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1171 pe->pbus = bus;
1172 pe->pdev = NULL;
1173 pe->mve_number = -1;
1174 pe->rid = bus->busn_res.start << 8;
1175
1176 if (all)
1177 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1178 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1179 else
1180 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1181 bus->busn_res.start, pe->pe_number);
1182
1183 if (pnv_ioda_configure_pe(phb, pe)) {
1184 /* XXX What do we do here ? */
1185 pnv_ioda_free_pe(pe);
1186 pe->pbus = NULL;
1187 return NULL;
1188 }
1189
1190 /* Associate it with all child devices */
1191 pnv_ioda_setup_same_PE(bus, pe);
1192
1193 /* Put PE to the list */
1194 list_add_tail(&pe->list, &phb->ioda.pe_list);
1195
1196 return pe;
1197 }
1198
1199 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1200 {
1201 int pe_num, found_pe = false, rc;
1202 long rid;
1203 struct pnv_ioda_pe *pe;
1204 struct pci_dev *gpu_pdev;
1205 struct pci_dn *npu_pdn;
1206 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1207 struct pnv_phb *phb = hose->private_data;
1208
1209 /*
1210 * Due to a hardware errata PE#0 on the NPU is reserved for
1211 * error handling. This means we only have three PEs remaining
1212 * which need to be assigned to four links, implying some
1213 * links must share PEs.
1214 *
1215 * To achieve this we assign PEs such that NPUs linking the
1216 * same GPU get assigned the same PE.
1217 */
1218 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1219 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1220 pe = &phb->ioda.pe_array[pe_num];
1221 if (!pe->pdev)
1222 continue;
1223
1224 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1225 /*
1226 * This device has the same peer GPU so should
1227 * be assigned the same PE as the existing
1228 * peer NPU.
1229 */
1230 dev_info(&npu_pdev->dev,
1231 "Associating to existing PE %x\n", pe_num);
1232 pci_dev_get(npu_pdev);
1233 npu_pdn = pci_get_pdn(npu_pdev);
1234 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1235 npu_pdn->pe_number = pe_num;
1236 phb->ioda.pe_rmap[rid] = pe->pe_number;
1237
1238 /* Map the PE to this link */
1239 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1240 OpalPciBusAll,
1241 OPAL_COMPARE_RID_DEVICE_NUMBER,
1242 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1243 OPAL_MAP_PE);
1244 WARN_ON(rc != OPAL_SUCCESS);
1245 found_pe = true;
1246 break;
1247 }
1248 }
1249
1250 if (!found_pe)
1251 /*
1252 * Could not find an existing PE so allocate a new
1253 * one.
1254 */
1255 return pnv_ioda_setup_dev_PE(npu_pdev);
1256 else
1257 return pe;
1258 }
1259
1260 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1261 {
1262 struct pci_dev *pdev;
1263
1264 list_for_each_entry(pdev, &bus->devices, bus_list)
1265 pnv_ioda_setup_npu_PE(pdev);
1266 }
1267
1268 static void pnv_pci_ioda_setup_PEs(void)
1269 {
1270 struct pci_controller *hose;
1271 struct pnv_phb *phb;
1272 struct pci_bus *bus;
1273 struct pci_dev *pdev;
1274 struct pnv_ioda_pe *pe;
1275
1276 list_for_each_entry(hose, &hose_list, list_node) {
1277 phb = hose->private_data;
1278 if (phb->type == PNV_PHB_NPU_NVLINK) {
1279 /* PE#0 is needed for error reporting */
1280 pnv_ioda_reserve_pe(phb, 0);
1281 pnv_ioda_setup_npu_PEs(hose->bus);
1282 if (phb->model == PNV_PHB_MODEL_NPU2)
1283 WARN_ON_ONCE(pnv_npu2_init(hose));
1284 }
1285 if (phb->type == PNV_PHB_NPU_OCAPI) {
1286 bus = hose->bus;
1287 list_for_each_entry(pdev, &bus->devices, bus_list)
1288 pnv_ioda_setup_dev_PE(pdev);
1289 }
1290 }
1291 list_for_each_entry(hose, &hose_list, list_node) {
1292 phb = hose->private_data;
1293 if (phb->type != PNV_PHB_IODA2)
1294 continue;
1295
1296 list_for_each_entry(pe, &phb->ioda.pe_list, list)
1297 pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1298 }
1299 }
1300
1301 #ifdef CONFIG_PCI_IOV
1302 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1303 {
1304 struct pci_bus *bus;
1305 struct pci_controller *hose;
1306 struct pnv_phb *phb;
1307 struct pci_dn *pdn;
1308 int i, j;
1309 int m64_bars;
1310
1311 bus = pdev->bus;
1312 hose = pci_bus_to_host(bus);
1313 phb = hose->private_data;
1314 pdn = pci_get_pdn(pdev);
1315
1316 if (pdn->m64_single_mode)
1317 m64_bars = num_vfs;
1318 else
1319 m64_bars = 1;
1320
1321 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1322 for (j = 0; j < m64_bars; j++) {
1323 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1324 continue;
1325 opal_pci_phb_mmio_enable(phb->opal_id,
1326 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1327 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1328 pdn->m64_map[j][i] = IODA_INVALID_M64;
1329 }
1330
1331 kfree(pdn->m64_map);
1332 return 0;
1333 }
1334
1335 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1336 {
1337 struct pci_bus *bus;
1338 struct pci_controller *hose;
1339 struct pnv_phb *phb;
1340 struct pci_dn *pdn;
1341 unsigned int win;
1342 struct resource *res;
1343 int i, j;
1344 int64_t rc;
1345 int total_vfs;
1346 resource_size_t size, start;
1347 int pe_num;
1348 int m64_bars;
1349
1350 bus = pdev->bus;
1351 hose = pci_bus_to_host(bus);
1352 phb = hose->private_data;
1353 pdn = pci_get_pdn(pdev);
1354 total_vfs = pci_sriov_get_totalvfs(pdev);
1355
1356 if (pdn->m64_single_mode)
1357 m64_bars = num_vfs;
1358 else
1359 m64_bars = 1;
1360
1361 pdn->m64_map = kmalloc_array(m64_bars,
1362 sizeof(*pdn->m64_map),
1363 GFP_KERNEL);
1364 if (!pdn->m64_map)
1365 return -ENOMEM;
1366 /* Initialize the m64_map to IODA_INVALID_M64 */
1367 for (i = 0; i < m64_bars ; i++)
1368 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1369 pdn->m64_map[i][j] = IODA_INVALID_M64;
1370
1371
1372 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1373 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1374 if (!res->flags || !res->parent)
1375 continue;
1376
1377 for (j = 0; j < m64_bars; j++) {
1378 do {
1379 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1380 phb->ioda.m64_bar_idx + 1, 0);
1381
1382 if (win >= phb->ioda.m64_bar_idx + 1)
1383 goto m64_failed;
1384 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1385
1386 pdn->m64_map[j][i] = win;
1387
1388 if (pdn->m64_single_mode) {
1389 size = pci_iov_resource_size(pdev,
1390 PCI_IOV_RESOURCES + i);
1391 start = res->start + size * j;
1392 } else {
1393 size = resource_size(res);
1394 start = res->start;
1395 }
1396
1397 /* Map the M64 here */
1398 if (pdn->m64_single_mode) {
1399 pe_num = pdn->pe_num_map[j];
1400 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1401 pe_num, OPAL_M64_WINDOW_TYPE,
1402 pdn->m64_map[j][i], 0);
1403 }
1404
1405 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1406 OPAL_M64_WINDOW_TYPE,
1407 pdn->m64_map[j][i],
1408 start,
1409 0, /* unused */
1410 size);
1411
1412
1413 if (rc != OPAL_SUCCESS) {
1414 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1415 win, rc);
1416 goto m64_failed;
1417 }
1418
1419 if (pdn->m64_single_mode)
1420 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1421 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1422 else
1423 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1424 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1425
1426 if (rc != OPAL_SUCCESS) {
1427 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1428 win, rc);
1429 goto m64_failed;
1430 }
1431 }
1432 }
1433 return 0;
1434
1435 m64_failed:
1436 pnv_pci_vf_release_m64(pdev, num_vfs);
1437 return -EBUSY;
1438 }
1439
1440 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1441 int num);
1442
1443 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1444 {
1445 struct iommu_table *tbl;
1446 int64_t rc;
1447
1448 tbl = pe->table_group.tables[0];
1449 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1450 if (rc)
1451 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1452
1453 pnv_pci_ioda2_set_bypass(pe, false);
1454 if (pe->table_group.group) {
1455 iommu_group_put(pe->table_group.group);
1456 BUG_ON(pe->table_group.group);
1457 }
1458 iommu_tce_table_put(tbl);
1459 }
1460
1461 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1462 {
1463 struct pci_bus *bus;
1464 struct pci_controller *hose;
1465 struct pnv_phb *phb;
1466 struct pnv_ioda_pe *pe, *pe_n;
1467 struct pci_dn *pdn;
1468
1469 bus = pdev->bus;
1470 hose = pci_bus_to_host(bus);
1471 phb = hose->private_data;
1472 pdn = pci_get_pdn(pdev);
1473
1474 if (!pdev->is_physfn)
1475 return;
1476
1477 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1478 if (pe->parent_dev != pdev)
1479 continue;
1480
1481 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1482
1483 /* Remove from list */
1484 mutex_lock(&phb->ioda.pe_list_mutex);
1485 list_del(&pe->list);
1486 mutex_unlock(&phb->ioda.pe_list_mutex);
1487
1488 pnv_ioda_deconfigure_pe(phb, pe);
1489
1490 pnv_ioda_free_pe(pe);
1491 }
1492 }
1493
1494 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1495 {
1496 struct pci_bus *bus;
1497 struct pci_controller *hose;
1498 struct pnv_phb *phb;
1499 struct pnv_ioda_pe *pe;
1500 struct pci_dn *pdn;
1501 u16 num_vfs, i;
1502
1503 bus = pdev->bus;
1504 hose = pci_bus_to_host(bus);
1505 phb = hose->private_data;
1506 pdn = pci_get_pdn(pdev);
1507 num_vfs = pdn->num_vfs;
1508
1509 /* Release VF PEs */
1510 pnv_ioda_release_vf_PE(pdev);
1511
1512 if (phb->type == PNV_PHB_IODA2) {
1513 if (!pdn->m64_single_mode)
1514 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1515
1516 /* Release M64 windows */
1517 pnv_pci_vf_release_m64(pdev, num_vfs);
1518
1519 /* Release PE numbers */
1520 if (pdn->m64_single_mode) {
1521 for (i = 0; i < num_vfs; i++) {
1522 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1523 continue;
1524
1525 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1526 pnv_ioda_free_pe(pe);
1527 }
1528 } else
1529 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1530 /* Releasing pe_num_map */
1531 kfree(pdn->pe_num_map);
1532 }
1533 }
1534
1535 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1536 struct pnv_ioda_pe *pe);
1537 #ifdef CONFIG_IOMMU_API
1538 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
1539 struct iommu_table_group *table_group, struct pci_bus *bus);
1540
1541 #endif
1542 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1543 {
1544 struct pci_bus *bus;
1545 struct pci_controller *hose;
1546 struct pnv_phb *phb;
1547 struct pnv_ioda_pe *pe;
1548 int pe_num;
1549 u16 vf_index;
1550 struct pci_dn *pdn;
1551
1552 bus = pdev->bus;
1553 hose = pci_bus_to_host(bus);
1554 phb = hose->private_data;
1555 pdn = pci_get_pdn(pdev);
1556
1557 if (!pdev->is_physfn)
1558 return;
1559
1560 /* Reserve PE for each VF */
1561 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1562 if (pdn->m64_single_mode)
1563 pe_num = pdn->pe_num_map[vf_index];
1564 else
1565 pe_num = *pdn->pe_num_map + vf_index;
1566
1567 pe = &phb->ioda.pe_array[pe_num];
1568 pe->pe_number = pe_num;
1569 pe->phb = phb;
1570 pe->flags = PNV_IODA_PE_VF;
1571 pe->pbus = NULL;
1572 pe->parent_dev = pdev;
1573 pe->mve_number = -1;
1574 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1575 pci_iov_virtfn_devfn(pdev, vf_index);
1576
1577 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1578 hose->global_number, pdev->bus->number,
1579 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1580 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1581
1582 if (pnv_ioda_configure_pe(phb, pe)) {
1583 /* XXX What do we do here ? */
1584 pnv_ioda_free_pe(pe);
1585 pe->pdev = NULL;
1586 continue;
1587 }
1588
1589 /* Put PE to the list */
1590 mutex_lock(&phb->ioda.pe_list_mutex);
1591 list_add_tail(&pe->list, &phb->ioda.pe_list);
1592 mutex_unlock(&phb->ioda.pe_list_mutex);
1593
1594 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1595 #ifdef CONFIG_IOMMU_API
1596 iommu_register_group(&pe->table_group,
1597 pe->phb->hose->global_number, pe->pe_number);
1598 pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
1599 #endif
1600 }
1601 }
1602
1603 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1604 {
1605 struct pci_bus *bus;
1606 struct pci_controller *hose;
1607 struct pnv_phb *phb;
1608 struct pnv_ioda_pe *pe;
1609 struct pci_dn *pdn;
1610 int ret;
1611 u16 i;
1612
1613 bus = pdev->bus;
1614 hose = pci_bus_to_host(bus);
1615 phb = hose->private_data;
1616 pdn = pci_get_pdn(pdev);
1617
1618 if (phb->type == PNV_PHB_IODA2) {
1619 if (!pdn->vfs_expanded) {
1620 dev_info(&pdev->dev, "don't support this SRIOV device"
1621 " with non 64bit-prefetchable IOV BAR\n");
1622 return -ENOSPC;
1623 }
1624
1625 /*
1626 * When M64 BARs functions in Single PE mode, the number of VFs
1627 * could be enabled must be less than the number of M64 BARs.
1628 */
1629 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1630 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1631 return -EBUSY;
1632 }
1633
1634 /* Allocating pe_num_map */
1635 if (pdn->m64_single_mode)
1636 pdn->pe_num_map = kmalloc_array(num_vfs,
1637 sizeof(*pdn->pe_num_map),
1638 GFP_KERNEL);
1639 else
1640 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1641
1642 if (!pdn->pe_num_map)
1643 return -ENOMEM;
1644
1645 if (pdn->m64_single_mode)
1646 for (i = 0; i < num_vfs; i++)
1647 pdn->pe_num_map[i] = IODA_INVALID_PE;
1648
1649 /* Calculate available PE for required VFs */
1650 if (pdn->m64_single_mode) {
1651 for (i = 0; i < num_vfs; i++) {
1652 pe = pnv_ioda_alloc_pe(phb);
1653 if (!pe) {
1654 ret = -EBUSY;
1655 goto m64_failed;
1656 }
1657
1658 pdn->pe_num_map[i] = pe->pe_number;
1659 }
1660 } else {
1661 mutex_lock(&phb->ioda.pe_alloc_mutex);
1662 *pdn->pe_num_map = bitmap_find_next_zero_area(
1663 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1664 0, num_vfs, 0);
1665 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1666 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1667 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1668 kfree(pdn->pe_num_map);
1669 return -EBUSY;
1670 }
1671 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1672 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1673 }
1674 pdn->num_vfs = num_vfs;
1675
1676 /* Assign M64 window accordingly */
1677 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1678 if (ret) {
1679 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1680 goto m64_failed;
1681 }
1682
1683 /*
1684 * When using one M64 BAR to map one IOV BAR, we need to shift
1685 * the IOV BAR according to the PE# allocated to the VFs.
1686 * Otherwise, the PE# for the VF will conflict with others.
1687 */
1688 if (!pdn->m64_single_mode) {
1689 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1690 if (ret)
1691 goto m64_failed;
1692 }
1693 }
1694
1695 /* Setup VF PEs */
1696 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1697
1698 return 0;
1699
1700 m64_failed:
1701 if (pdn->m64_single_mode) {
1702 for (i = 0; i < num_vfs; i++) {
1703 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1704 continue;
1705
1706 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1707 pnv_ioda_free_pe(pe);
1708 }
1709 } else
1710 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1711
1712 /* Releasing pe_num_map */
1713 kfree(pdn->pe_num_map);
1714
1715 return ret;
1716 }
1717
1718 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1719 {
1720 pnv_pci_sriov_disable(pdev);
1721
1722 /* Release PCI data */
1723 remove_dev_pci_data(pdev);
1724 return 0;
1725 }
1726
1727 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1728 {
1729 /* Allocate PCI data */
1730 add_dev_pci_data(pdev);
1731
1732 return pnv_pci_sriov_enable(pdev, num_vfs);
1733 }
1734 #endif /* CONFIG_PCI_IOV */
1735
1736 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1737 {
1738 struct pci_dn *pdn = pci_get_pdn(pdev);
1739 struct pnv_ioda_pe *pe;
1740
1741 /*
1742 * The function can be called while the PE#
1743 * hasn't been assigned. Do nothing for the
1744 * case.
1745 */
1746 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1747 return;
1748
1749 pe = &phb->ioda.pe_array[pdn->pe_number];
1750 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1751 pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1752 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1753 /*
1754 * Note: iommu_add_device() will fail here as
1755 * for physical PE: the device is already added by now;
1756 * for virtual PE: sysfs entries are not ready yet and
1757 * tce_iommu_bus_notifier will add the device to a group later.
1758 */
1759 }
1760
1761 /*
1762 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1763 *
1764 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1765 * Devices can only access more than that if bit 59 of the PCI address is set
1766 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1767 * Many PCI devices are not capable of addressing that many bits, and as a
1768 * result are limited to the 4GB of virtual memory made available to 32-bit
1769 * devices in TVE#0.
1770 *
1771 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1772 * devices by configuring the virtual memory past the first 4GB inaccessible
1773 * by 64-bit DMAs. This should only be used by devices that want more than
1774 * 4GB, and only on PEs that have no 32-bit devices.
1775 *
1776 * Currently this will only work on PHB3 (POWER8).
1777 */
1778 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1779 {
1780 u64 window_size, table_size, tce_count, addr;
1781 struct page *table_pages;
1782 u64 tce_order = 28; /* 256MB TCEs */
1783 __be64 *tces;
1784 s64 rc;
1785
1786 /*
1787 * Window size needs to be a power of two, but needs to account for
1788 * shifting memory by the 4GB offset required to skip 32bit space.
1789 */
1790 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1791 tce_count = window_size >> tce_order;
1792 table_size = tce_count << 3;
1793
1794 if (table_size < PAGE_SIZE)
1795 table_size = PAGE_SIZE;
1796
1797 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1798 get_order(table_size));
1799 if (!table_pages)
1800 goto err;
1801
1802 tces = page_address(table_pages);
1803 if (!tces)
1804 goto err;
1805
1806 memset(tces, 0, table_size);
1807
1808 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1809 tces[(addr + (1ULL << 32)) >> tce_order] =
1810 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1811 }
1812
1813 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1814 pe->pe_number,
1815 /* reconfigure window 0 */
1816 (pe->pe_number << 1) + 0,
1817 1,
1818 __pa(tces),
1819 table_size,
1820 1 << tce_order);
1821 if (rc == OPAL_SUCCESS) {
1822 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1823 return 0;
1824 }
1825 err:
1826 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1827 return -EIO;
1828 }
1829
1830 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1831 u64 dma_mask)
1832 {
1833 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1834 struct pnv_phb *phb = hose->private_data;
1835 struct pci_dn *pdn = pci_get_pdn(pdev);
1836 struct pnv_ioda_pe *pe;
1837
1838 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1839 return -ENODEV;
1840
1841 pe = &phb->ioda.pe_array[pdn->pe_number];
1842 if (pe->tce_bypass_enabled) {
1843 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1844 if (dma_mask >= top)
1845 return true;
1846 }
1847
1848 /*
1849 * If the device can't set the TCE bypass bit but still wants
1850 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1851 * bypass the 32-bit region and be usable for 64-bit DMAs.
1852 * The device needs to be able to address all of this space.
1853 */
1854 if (dma_mask >> 32 &&
1855 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1856 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1857 (pe->device_count == 1 || !pe->pbus) &&
1858 phb->model == PNV_PHB_MODEL_PHB3) {
1859 /* Configure the bypass mode */
1860 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1861 if (rc)
1862 return rc;
1863 /* 4GB offset bypasses 32-bit space */
1864 pdev->dev.archdata.dma_offset = (1ULL << 32);
1865 return true;
1866 }
1867
1868 return false;
1869 }
1870
1871 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1872 {
1873 struct pci_dev *dev;
1874
1875 list_for_each_entry(dev, &bus->devices, bus_list) {
1876 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1877 dev->dev.archdata.dma_offset = pe->tce_bypass_base;
1878
1879 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1880 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1881 }
1882 }
1883
1884 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1885 bool real_mode)
1886 {
1887 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1888 (phb->regs + 0x210);
1889 }
1890
1891 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1892 unsigned long index, unsigned long npages, bool rm)
1893 {
1894 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1895 &tbl->it_group_list, struct iommu_table_group_link,
1896 next);
1897 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1898 struct pnv_ioda_pe, table_group);
1899 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1900 unsigned long start, end, inc;
1901
1902 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1903 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1904 npages - 1);
1905
1906 /* p7ioc-style invalidation, 2 TCEs per write */
1907 start |= (1ull << 63);
1908 end |= (1ull << 63);
1909 inc = 16;
1910 end |= inc - 1; /* round up end to be different than start */
1911
1912 mb(); /* Ensure above stores are visible */
1913 while (start <= end) {
1914 if (rm)
1915 __raw_rm_writeq_be(start, invalidate);
1916 else
1917 __raw_writeq_be(start, invalidate);
1918
1919 start += inc;
1920 }
1921
1922 /*
1923 * The iommu layer will do another mb() for us on build()
1924 * and we don't care on free()
1925 */
1926 }
1927
1928 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1929 long npages, unsigned long uaddr,
1930 enum dma_data_direction direction,
1931 unsigned long attrs)
1932 {
1933 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1934 attrs);
1935
1936 if (!ret)
1937 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1938
1939 return ret;
1940 }
1941
1942 #ifdef CONFIG_IOMMU_API
1943 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
1944 unsigned long *hpa, enum dma_data_direction *direction)
1945 {
1946 long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
1947
1948 if (!ret)
1949 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
1950
1951 return ret;
1952 }
1953
1954 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
1955 unsigned long *hpa, enum dma_data_direction *direction)
1956 {
1957 long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
1958
1959 if (!ret)
1960 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
1961
1962 return ret;
1963 }
1964 #endif
1965
1966 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1967 long npages)
1968 {
1969 pnv_tce_free(tbl, index, npages);
1970
1971 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1972 }
1973
1974 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1975 .set = pnv_ioda1_tce_build,
1976 #ifdef CONFIG_IOMMU_API
1977 .exchange = pnv_ioda1_tce_xchg,
1978 .exchange_rm = pnv_ioda1_tce_xchg_rm,
1979 .useraddrptr = pnv_tce_useraddrptr,
1980 #endif
1981 .clear = pnv_ioda1_tce_free,
1982 .get = pnv_tce_get,
1983 };
1984
1985 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1986 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1987 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1988
1989 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1990 {
1991 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1992 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1993
1994 mb(); /* Ensure previous TCE table stores are visible */
1995 if (rm)
1996 __raw_rm_writeq_be(val, invalidate);
1997 else
1998 __raw_writeq_be(val, invalidate);
1999 }
2000
2001 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2002 {
2003 /* 01xb - invalidate TCEs that match the specified PE# */
2004 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2005 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2006
2007 mb(); /* Ensure above stores are visible */
2008 __raw_writeq_be(val, invalidate);
2009 }
2010
2011 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2012 unsigned shift, unsigned long index,
2013 unsigned long npages)
2014 {
2015 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2016 unsigned long start, end, inc;
2017
2018 /* We'll invalidate DMA address in PE scope */
2019 start = PHB3_TCE_KILL_INVAL_ONE;
2020 start |= (pe->pe_number & 0xFF);
2021 end = start;
2022
2023 /* Figure out the start, end and step */
2024 start |= (index << shift);
2025 end |= ((index + npages - 1) << shift);
2026 inc = (0x1ull << shift);
2027 mb();
2028
2029 while (start <= end) {
2030 if (rm)
2031 __raw_rm_writeq_be(start, invalidate);
2032 else
2033 __raw_writeq_be(start, invalidate);
2034 start += inc;
2035 }
2036 }
2037
2038 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2039 {
2040 struct pnv_phb *phb = pe->phb;
2041
2042 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2043 pnv_pci_phb3_tce_invalidate_pe(pe);
2044 else
2045 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2046 pe->pe_number, 0, 0, 0);
2047 }
2048
2049 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2050 unsigned long index, unsigned long npages, bool rm)
2051 {
2052 struct iommu_table_group_link *tgl;
2053
2054 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2055 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2056 struct pnv_ioda_pe, table_group);
2057 struct pnv_phb *phb = pe->phb;
2058 unsigned int shift = tbl->it_page_shift;
2059
2060 /*
2061 * NVLink1 can use the TCE kill register directly as
2062 * it's the same as PHB3. NVLink2 is different and
2063 * should go via the OPAL call.
2064 */
2065 if (phb->model == PNV_PHB_MODEL_NPU) {
2066 /*
2067 * The NVLink hardware does not support TCE kill
2068 * per TCE entry so we have to invalidate
2069 * the entire cache for it.
2070 */
2071 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2072 continue;
2073 }
2074 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2075 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2076 index, npages);
2077 else
2078 opal_pci_tce_kill(phb->opal_id,
2079 OPAL_PCI_TCE_KILL_PAGES,
2080 pe->pe_number, 1u << shift,
2081 index << shift, npages);
2082 }
2083 }
2084
2085 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2086 {
2087 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2088 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2089 else
2090 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2091 }
2092
2093 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2094 long npages, unsigned long uaddr,
2095 enum dma_data_direction direction,
2096 unsigned long attrs)
2097 {
2098 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2099 attrs);
2100
2101 if (!ret)
2102 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2103
2104 return ret;
2105 }
2106
2107 #ifdef CONFIG_IOMMU_API
2108 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2109 unsigned long *hpa, enum dma_data_direction *direction)
2110 {
2111 long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2112
2113 if (!ret)
2114 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2115
2116 return ret;
2117 }
2118
2119 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2120 unsigned long *hpa, enum dma_data_direction *direction)
2121 {
2122 long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2123
2124 if (!ret)
2125 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2126
2127 return ret;
2128 }
2129 #endif
2130
2131 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2132 long npages)
2133 {
2134 pnv_tce_free(tbl, index, npages);
2135
2136 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2137 }
2138
2139 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2140 .set = pnv_ioda2_tce_build,
2141 #ifdef CONFIG_IOMMU_API
2142 .exchange = pnv_ioda2_tce_xchg,
2143 .exchange_rm = pnv_ioda2_tce_xchg_rm,
2144 .useraddrptr = pnv_tce_useraddrptr,
2145 #endif
2146 .clear = pnv_ioda2_tce_free,
2147 .get = pnv_tce_get,
2148 .free = pnv_pci_ioda2_table_free_pages,
2149 };
2150
2151 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2152 {
2153 unsigned int *weight = (unsigned int *)data;
2154
2155 /* This is quite simplistic. The "base" weight of a device
2156 * is 10. 0 means no DMA is to be accounted for it.
2157 */
2158 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2159 return 0;
2160
2161 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2162 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2163 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2164 *weight += 3;
2165 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2166 *weight += 15;
2167 else
2168 *weight += 10;
2169
2170 return 0;
2171 }
2172
2173 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2174 {
2175 unsigned int weight = 0;
2176
2177 /* SRIOV VF has same DMA32 weight as its PF */
2178 #ifdef CONFIG_PCI_IOV
2179 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2180 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2181 return weight;
2182 }
2183 #endif
2184
2185 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2186 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2187 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2188 struct pci_dev *pdev;
2189
2190 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2191 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2192 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2193 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2194 }
2195
2196 return weight;
2197 }
2198
2199 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2200 struct pnv_ioda_pe *pe)
2201 {
2202
2203 struct page *tce_mem = NULL;
2204 struct iommu_table *tbl;
2205 unsigned int weight, total_weight = 0;
2206 unsigned int tce32_segsz, base, segs, avail, i;
2207 int64_t rc;
2208 void *addr;
2209
2210 /* XXX FIXME: Handle 64-bit only DMA devices */
2211 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2212 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2213 weight = pnv_pci_ioda_pe_dma_weight(pe);
2214 if (!weight)
2215 return;
2216
2217 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2218 &total_weight);
2219 segs = (weight * phb->ioda.dma32_count) / total_weight;
2220 if (!segs)
2221 segs = 1;
2222
2223 /*
2224 * Allocate contiguous DMA32 segments. We begin with the expected
2225 * number of segments. With one more attempt, the number of DMA32
2226 * segments to be allocated is decreased by one until one segment
2227 * is allocated successfully.
2228 */
2229 do {
2230 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2231 for (avail = 0, i = base; i < base + segs; i++) {
2232 if (phb->ioda.dma32_segmap[i] ==
2233 IODA_INVALID_PE)
2234 avail++;
2235 }
2236
2237 if (avail == segs)
2238 goto found;
2239 }
2240 } while (--segs);
2241
2242 if (!segs) {
2243 pe_warn(pe, "No available DMA32 segments\n");
2244 return;
2245 }
2246
2247 found:
2248 tbl = pnv_pci_table_alloc(phb->hose->node);
2249 if (WARN_ON(!tbl))
2250 return;
2251
2252 iommu_register_group(&pe->table_group, phb->hose->global_number,
2253 pe->pe_number);
2254 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2255
2256 /* Grab a 32-bit TCE table */
2257 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2258 weight, total_weight, base, segs);
2259 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2260 base * PNV_IODA1_DMA32_SEGSIZE,
2261 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2262
2263 /* XXX Currently, we allocate one big contiguous table for the
2264 * TCEs. We only really need one chunk per 256M of TCE space
2265 * (ie per segment) but that's an optimization for later, it
2266 * requires some added smarts with our get/put_tce implementation
2267 *
2268 * Each TCE page is 4KB in size and each TCE entry occupies 8
2269 * bytes
2270 */
2271 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2272 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2273 get_order(tce32_segsz * segs));
2274 if (!tce_mem) {
2275 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2276 goto fail;
2277 }
2278 addr = page_address(tce_mem);
2279 memset(addr, 0, tce32_segsz * segs);
2280
2281 /* Configure HW */
2282 for (i = 0; i < segs; i++) {
2283 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2284 pe->pe_number,
2285 base + i, 1,
2286 __pa(addr) + tce32_segsz * i,
2287 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2288 if (rc) {
2289 pe_err(pe, " Failed to configure 32-bit TCE table,"
2290 " err %ld\n", rc);
2291 goto fail;
2292 }
2293 }
2294
2295 /* Setup DMA32 segment mapping */
2296 for (i = base; i < base + segs; i++)
2297 phb->ioda.dma32_segmap[i] = pe->pe_number;
2298
2299 /* Setup linux iommu table */
2300 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2301 base * PNV_IODA1_DMA32_SEGSIZE,
2302 IOMMU_PAGE_SHIFT_4K);
2303
2304 tbl->it_ops = &pnv_ioda1_iommu_ops;
2305 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2306 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2307 iommu_init_table(tbl, phb->hose->node);
2308
2309 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2310 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2311
2312 return;
2313 fail:
2314 /* XXX Failure: Try to fallback to 64-bit only ? */
2315 if (tce_mem)
2316 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2317 if (tbl) {
2318 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2319 iommu_tce_table_put(tbl);
2320 }
2321 }
2322
2323 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2324 int num, struct iommu_table *tbl)
2325 {
2326 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2327 table_group);
2328 struct pnv_phb *phb = pe->phb;
2329 int64_t rc;
2330 const unsigned long size = tbl->it_indirect_levels ?
2331 tbl->it_level_size : tbl->it_size;
2332 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2333 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2334
2335 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2336 start_addr, start_addr + win_size - 1,
2337 IOMMU_PAGE_SIZE(tbl));
2338
2339 /*
2340 * Map TCE table through TVT. The TVE index is the PE number
2341 * shifted by 1 bit for 32-bits DMA space.
2342 */
2343 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2344 pe->pe_number,
2345 (pe->pe_number << 1) + num,
2346 tbl->it_indirect_levels + 1,
2347 __pa(tbl->it_base),
2348 size << 3,
2349 IOMMU_PAGE_SIZE(tbl));
2350 if (rc) {
2351 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2352 return rc;
2353 }
2354
2355 pnv_pci_link_table_and_group(phb->hose->node, num,
2356 tbl, &pe->table_group);
2357 pnv_pci_ioda2_tce_invalidate_pe(pe);
2358
2359 return 0;
2360 }
2361
2362 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2363 {
2364 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2365 int64_t rc;
2366
2367 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2368 if (enable) {
2369 phys_addr_t top = memblock_end_of_DRAM();
2370
2371 top = roundup_pow_of_two(top);
2372 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2373 pe->pe_number,
2374 window_id,
2375 pe->tce_bypass_base,
2376 top);
2377 } else {
2378 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2379 pe->pe_number,
2380 window_id,
2381 pe->tce_bypass_base,
2382 0);
2383 }
2384 if (rc)
2385 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2386 else
2387 pe->tce_bypass_enabled = enable;
2388 }
2389
2390 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2391 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2392 bool alloc_userspace_copy, struct iommu_table **ptbl)
2393 {
2394 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2395 table_group);
2396 int nid = pe->phb->hose->node;
2397 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2398 long ret;
2399 struct iommu_table *tbl;
2400
2401 tbl = pnv_pci_table_alloc(nid);
2402 if (!tbl)
2403 return -ENOMEM;
2404
2405 tbl->it_ops = &pnv_ioda2_iommu_ops;
2406
2407 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2408 bus_offset, page_shift, window_size,
2409 levels, alloc_userspace_copy, tbl);
2410 if (ret) {
2411 iommu_tce_table_put(tbl);
2412 return ret;
2413 }
2414
2415 *ptbl = tbl;
2416
2417 return 0;
2418 }
2419
2420 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2421 {
2422 struct iommu_table *tbl = NULL;
2423 long rc;
2424
2425 /*
2426 * crashkernel= specifies the kdump kernel's maximum memory at
2427 * some offset and there is no guaranteed the result is a power
2428 * of 2, which will cause errors later.
2429 */
2430 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2431
2432 /*
2433 * In memory constrained environments, e.g. kdump kernel, the
2434 * DMA window can be larger than available memory, which will
2435 * cause errors later.
2436 */
2437 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2438
2439 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2440 IOMMU_PAGE_SHIFT_4K,
2441 window_size,
2442 POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl);
2443 if (rc) {
2444 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2445 rc);
2446 return rc;
2447 }
2448
2449 iommu_init_table(tbl, pe->phb->hose->node);
2450
2451 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2452 if (rc) {
2453 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2454 rc);
2455 iommu_tce_table_put(tbl);
2456 return rc;
2457 }
2458
2459 if (!pnv_iommu_bypass_disabled)
2460 pnv_pci_ioda2_set_bypass(pe, true);
2461
2462 return 0;
2463 }
2464
2465 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2466 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2467 int num)
2468 {
2469 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2470 table_group);
2471 struct pnv_phb *phb = pe->phb;
2472 long ret;
2473
2474 pe_info(pe, "Removing DMA window #%d\n", num);
2475
2476 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2477 (pe->pe_number << 1) + num,
2478 0/* levels */, 0/* table address */,
2479 0/* table size */, 0/* page size */);
2480 if (ret)
2481 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2482 else
2483 pnv_pci_ioda2_tce_invalidate_pe(pe);
2484
2485 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2486
2487 return ret;
2488 }
2489 #endif
2490
2491 #ifdef CONFIG_IOMMU_API
2492 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2493 __u64 window_size, __u32 levels)
2494 {
2495 unsigned long bytes = 0;
2496 const unsigned window_shift = ilog2(window_size);
2497 unsigned entries_shift = window_shift - page_shift;
2498 unsigned table_shift = entries_shift + 3;
2499 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2500 unsigned long direct_table_size;
2501
2502 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2503 !is_power_of_2(window_size))
2504 return 0;
2505
2506 /* Calculate a direct table size from window_size and levels */
2507 entries_shift = (entries_shift + levels - 1) / levels;
2508 table_shift = entries_shift + 3;
2509 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2510 direct_table_size = 1UL << table_shift;
2511
2512 for ( ; levels; --levels) {
2513 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2514
2515 tce_table_size /= direct_table_size;
2516 tce_table_size <<= 3;
2517 tce_table_size = max_t(unsigned long,
2518 tce_table_size, direct_table_size);
2519 }
2520
2521 return bytes + bytes; /* one for HW table, one for userspace copy */
2522 }
2523
2524 static long pnv_pci_ioda2_create_table_userspace(
2525 struct iommu_table_group *table_group,
2526 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2527 struct iommu_table **ptbl)
2528 {
2529 long ret = pnv_pci_ioda2_create_table(table_group,
2530 num, page_shift, window_size, levels, true, ptbl);
2531
2532 if (!ret)
2533 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
2534 page_shift, window_size, levels);
2535 return ret;
2536 }
2537
2538 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2539 {
2540 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2541 table_group);
2542 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2543 struct iommu_table *tbl = pe->table_group.tables[0];
2544
2545 pnv_pci_ioda2_set_bypass(pe, false);
2546 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2547 if (pe->pbus)
2548 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2549 iommu_tce_table_put(tbl);
2550 }
2551
2552 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2553 {
2554 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2555 table_group);
2556
2557 pnv_pci_ioda2_setup_default_config(pe);
2558 if (pe->pbus)
2559 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2560 }
2561
2562 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2563 .get_table_size = pnv_pci_ioda2_get_table_size,
2564 .create_table = pnv_pci_ioda2_create_table_userspace,
2565 .set_window = pnv_pci_ioda2_set_window,
2566 .unset_window = pnv_pci_ioda2_unset_window,
2567 .take_ownership = pnv_ioda2_take_ownership,
2568 .release_ownership = pnv_ioda2_release_ownership,
2569 };
2570
2571 static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
2572 struct iommu_table_group *table_group,
2573 struct pci_bus *bus)
2574 {
2575 struct pci_dev *dev;
2576
2577 list_for_each_entry(dev, &bus->devices, bus_list) {
2578 iommu_add_device(table_group, &dev->dev);
2579
2580 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2581 pnv_ioda_setup_bus_iommu_group_add_devices(pe,
2582 table_group, dev->subordinate);
2583 }
2584 }
2585
2586 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
2587 struct iommu_table_group *table_group, struct pci_bus *bus)
2588 {
2589
2590 if (pe->flags & PNV_IODA_PE_DEV)
2591 iommu_add_device(table_group, &pe->pdev->dev);
2592
2593 if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
2594 pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
2595 bus);
2596 }
2597
2598 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
2599
2600 static void pnv_pci_ioda_setup_iommu_api(void)
2601 {
2602 struct pci_controller *hose;
2603 struct pnv_phb *phb;
2604 struct pnv_ioda_pe *pe;
2605
2606 /*
2607 * There are 4 types of PEs:
2608 * - PNV_IODA_PE_BUS: a downstream port with an adapter,
2609 * created from pnv_pci_setup_bridge();
2610 * - PNV_IODA_PE_BUS_ALL: a PCI-PCIX bridge with devices behind it,
2611 * created from pnv_pci_setup_bridge();
2612 * - PNV_IODA_PE_VF: a SRIOV virtual function,
2613 * created from pnv_pcibios_sriov_enable();
2614 * - PNV_IODA_PE_DEV: an NPU or OCAPI device,
2615 * created from pnv_pci_ioda_fixup().
2616 *
2617 * Normally a PE is represented by an IOMMU group, however for
2618 * devices with side channels the groups need to be more strict.
2619 */
2620 list_for_each_entry(hose, &hose_list, list_node) {
2621 phb = hose->private_data;
2622
2623 if (phb->type == PNV_PHB_NPU_NVLINK ||
2624 phb->type == PNV_PHB_NPU_OCAPI)
2625 continue;
2626
2627 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2628 struct iommu_table_group *table_group;
2629
2630 table_group = pnv_try_setup_npu_table_group(pe);
2631 if (!table_group) {
2632 if (!pnv_pci_ioda_pe_dma_weight(pe))
2633 continue;
2634
2635 table_group = &pe->table_group;
2636 iommu_register_group(&pe->table_group,
2637 pe->phb->hose->global_number,
2638 pe->pe_number);
2639 }
2640 pnv_ioda_setup_bus_iommu_group(pe, table_group,
2641 pe->pbus);
2642 }
2643 }
2644
2645 /*
2646 * Now we have all PHBs discovered, time to add NPU devices to
2647 * the corresponding IOMMU groups.
2648 */
2649 list_for_each_entry(hose, &hose_list, list_node) {
2650 unsigned long pgsizes;
2651
2652 phb = hose->private_data;
2653
2654 if (phb->type != PNV_PHB_NPU_NVLINK)
2655 continue;
2656
2657 pgsizes = pnv_ioda_parse_tce_sizes(phb);
2658 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2659 /*
2660 * IODA2 bridges get this set up from
2661 * pci_controller_ops::setup_bridge but NPU bridges
2662 * do not have this hook defined so we do it here.
2663 */
2664 pe->table_group.pgsizes = pgsizes;
2665 pnv_npu_compound_attach(pe);
2666 }
2667 }
2668 }
2669 #else /* !CONFIG_IOMMU_API */
2670 static void pnv_pci_ioda_setup_iommu_api(void) { };
2671 #endif
2672
2673 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2674 {
2675 struct pci_controller *hose = phb->hose;
2676 struct device_node *dn = hose->dn;
2677 unsigned long mask = 0;
2678 int i, rc, count;
2679 u32 val;
2680
2681 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2682 if (count <= 0) {
2683 mask = SZ_4K | SZ_64K;
2684 /* Add 16M for POWER8 by default */
2685 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2686 !cpu_has_feature(CPU_FTR_ARCH_300))
2687 mask |= SZ_16M | SZ_256M;
2688 return mask;
2689 }
2690
2691 for (i = 0; i < count; i++) {
2692 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2693 i, &val);
2694 if (rc == 0)
2695 mask |= 1ULL << val;
2696 }
2697
2698 return mask;
2699 }
2700
2701 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2702 struct pnv_ioda_pe *pe)
2703 {
2704 int64_t rc;
2705
2706 if (!pnv_pci_ioda_pe_dma_weight(pe))
2707 return;
2708
2709 /* TVE #1 is selected by PCI address bit 59 */
2710 pe->tce_bypass_base = 1ull << 59;
2711
2712 /* The PE will reserve all possible 32-bits space */
2713 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2714 phb->ioda.m32_pci_base);
2715
2716 /* Setup linux iommu table */
2717 pe->table_group.tce32_start = 0;
2718 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2719 pe->table_group.max_dynamic_windows_supported =
2720 IOMMU_TABLE_GROUP_MAX_TABLES;
2721 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2722 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2723 #ifdef CONFIG_IOMMU_API
2724 pe->table_group.ops = &pnv_pci_ioda2_ops;
2725 #endif
2726
2727 rc = pnv_pci_ioda2_setup_default_config(pe);
2728 if (rc)
2729 return;
2730
2731 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2732 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2733 }
2734
2735 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2736 {
2737 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2738 ioda.irq_chip);
2739
2740 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2741 }
2742
2743 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2744 {
2745 int64_t rc;
2746 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2747 struct irq_chip *chip = irq_data_get_irq_chip(d);
2748
2749 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2750 WARN_ON_ONCE(rc);
2751
2752 icp_native_eoi(d);
2753 }
2754
2755
2756 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2757 {
2758 struct irq_data *idata;
2759 struct irq_chip *ichip;
2760
2761 /* The MSI EOI OPAL call is only needed on PHB3 */
2762 if (phb->model != PNV_PHB_MODEL_PHB3)
2763 return;
2764
2765 if (!phb->ioda.irq_chip_init) {
2766 /*
2767 * First time we setup an MSI IRQ, we need to setup the
2768 * corresponding IRQ chip to route correctly.
2769 */
2770 idata = irq_get_irq_data(virq);
2771 ichip = irq_data_get_irq_chip(idata);
2772 phb->ioda.irq_chip_init = 1;
2773 phb->ioda.irq_chip = *ichip;
2774 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2775 }
2776 irq_set_chip(virq, &phb->ioda.irq_chip);
2777 }
2778
2779 /*
2780 * Returns true iff chip is something that we could call
2781 * pnv_opal_pci_msi_eoi for.
2782 */
2783 bool is_pnv_opal_msi(struct irq_chip *chip)
2784 {
2785 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2786 }
2787 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2788
2789 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2790 unsigned int hwirq, unsigned int virq,
2791 unsigned int is_64, struct msi_msg *msg)
2792 {
2793 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2794 unsigned int xive_num = hwirq - phb->msi_base;
2795 __be32 data;
2796 int rc;
2797
2798 /* No PE assigned ? bail out ... no MSI for you ! */
2799 if (pe == NULL)
2800 return -ENXIO;
2801
2802 /* Check if we have an MVE */
2803 if (pe->mve_number < 0)
2804 return -ENXIO;
2805
2806 /* Force 32-bit MSI on some broken devices */
2807 if (dev->no_64bit_msi)
2808 is_64 = 0;
2809
2810 /* Assign XIVE to PE */
2811 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2812 if (rc) {
2813 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2814 pci_name(dev), rc, xive_num);
2815 return -EIO;
2816 }
2817
2818 if (is_64) {
2819 __be64 addr64;
2820
2821 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2822 &addr64, &data);
2823 if (rc) {
2824 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2825 pci_name(dev), rc);
2826 return -EIO;
2827 }
2828 msg->address_hi = be64_to_cpu(addr64) >> 32;
2829 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2830 } else {
2831 __be32 addr32;
2832
2833 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2834 &addr32, &data);
2835 if (rc) {
2836 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2837 pci_name(dev), rc);
2838 return -EIO;
2839 }
2840 msg->address_hi = 0;
2841 msg->address_lo = be32_to_cpu(addr32);
2842 }
2843 msg->data = be32_to_cpu(data);
2844
2845 pnv_set_msi_irq_chip(phb, virq);
2846
2847 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2848 " address=%x_%08x data=%x PE# %x\n",
2849 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2850 msg->address_hi, msg->address_lo, data, pe->pe_number);
2851
2852 return 0;
2853 }
2854
2855 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2856 {
2857 unsigned int count;
2858 const __be32 *prop = of_get_property(phb->hose->dn,
2859 "ibm,opal-msi-ranges", NULL);
2860 if (!prop) {
2861 /* BML Fallback */
2862 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2863 }
2864 if (!prop)
2865 return;
2866
2867 phb->msi_base = be32_to_cpup(prop);
2868 count = be32_to_cpup(prop + 1);
2869 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2870 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2871 phb->hose->global_number);
2872 return;
2873 }
2874
2875 phb->msi_setup = pnv_pci_ioda_msi_setup;
2876 phb->msi32_support = 1;
2877 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2878 count, phb->msi_base);
2879 }
2880
2881 #ifdef CONFIG_PCI_IOV
2882 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2883 {
2884 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2885 struct pnv_phb *phb = hose->private_data;
2886 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2887 struct resource *res;
2888 int i;
2889 resource_size_t size, total_vf_bar_sz;
2890 struct pci_dn *pdn;
2891 int mul, total_vfs;
2892
2893 if (!pdev->is_physfn || pci_dev_is_added(pdev))
2894 return;
2895
2896 pdn = pci_get_pdn(pdev);
2897 pdn->vfs_expanded = 0;
2898 pdn->m64_single_mode = false;
2899
2900 total_vfs = pci_sriov_get_totalvfs(pdev);
2901 mul = phb->ioda.total_pe_num;
2902 total_vf_bar_sz = 0;
2903
2904 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2905 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2906 if (!res->flags || res->parent)
2907 continue;
2908 if (!pnv_pci_is_m64_flags(res->flags)) {
2909 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2910 " non M64 VF BAR%d: %pR. \n",
2911 i, res);
2912 goto truncate_iov;
2913 }
2914
2915 total_vf_bar_sz += pci_iov_resource_size(pdev,
2916 i + PCI_IOV_RESOURCES);
2917
2918 /*
2919 * If bigger than quarter of M64 segment size, just round up
2920 * power of two.
2921 *
2922 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2923 * with other devices, IOV BAR size is expanded to be
2924 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2925 * segment size , the expanded size would equal to half of the
2926 * whole M64 space size, which will exhaust the M64 Space and
2927 * limit the system flexibility. This is a design decision to
2928 * set the boundary to quarter of the M64 segment size.
2929 */
2930 if (total_vf_bar_sz > gate) {
2931 mul = roundup_pow_of_two(total_vfs);
2932 dev_info(&pdev->dev,
2933 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2934 total_vf_bar_sz, gate, mul);
2935 pdn->m64_single_mode = true;
2936 break;
2937 }
2938 }
2939
2940 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2941 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2942 if (!res->flags || res->parent)
2943 continue;
2944
2945 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2946 /*
2947 * On PHB3, the minimum size alignment of M64 BAR in single
2948 * mode is 32MB.
2949 */
2950 if (pdn->m64_single_mode && (size < SZ_32M))
2951 goto truncate_iov;
2952 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2953 res->end = res->start + size * mul - 1;
2954 dev_dbg(&pdev->dev, " %pR\n", res);
2955 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2956 i, res, mul);
2957 }
2958 pdn->vfs_expanded = mul;
2959
2960 return;
2961
2962 truncate_iov:
2963 /* To save MMIO space, IOV BAR is truncated. */
2964 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2965 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2966 res->flags = 0;
2967 res->end = res->start - 1;
2968 }
2969 }
2970 #endif /* CONFIG_PCI_IOV */
2971
2972 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2973 struct resource *res)
2974 {
2975 struct pnv_phb *phb = pe->phb;
2976 struct pci_bus_region region;
2977 int index;
2978 int64_t rc;
2979
2980 if (!res || !res->flags || res->start > res->end)
2981 return;
2982
2983 if (res->flags & IORESOURCE_IO) {
2984 region.start = res->start - phb->ioda.io_pci_base;
2985 region.end = res->end - phb->ioda.io_pci_base;
2986 index = region.start / phb->ioda.io_segsize;
2987
2988 while (index < phb->ioda.total_pe_num &&
2989 region.start <= region.end) {
2990 phb->ioda.io_segmap[index] = pe->pe_number;
2991 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2992 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2993 if (rc != OPAL_SUCCESS) {
2994 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
2995 __func__, rc, index, pe->pe_number);
2996 break;
2997 }
2998
2999 region.start += phb->ioda.io_segsize;
3000 index++;
3001 }
3002 } else if ((res->flags & IORESOURCE_MEM) &&
3003 !pnv_pci_is_m64(phb, res)) {
3004 region.start = res->start -
3005 phb->hose->mem_offset[0] -
3006 phb->ioda.m32_pci_base;
3007 region.end = res->end -
3008 phb->hose->mem_offset[0] -
3009 phb->ioda.m32_pci_base;
3010 index = region.start / phb->ioda.m32_segsize;
3011
3012 while (index < phb->ioda.total_pe_num &&
3013 region.start <= region.end) {
3014 phb->ioda.m32_segmap[index] = pe->pe_number;
3015 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3016 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3017 if (rc != OPAL_SUCCESS) {
3018 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3019 __func__, rc, index, pe->pe_number);
3020 break;
3021 }
3022
3023 region.start += phb->ioda.m32_segsize;
3024 index++;
3025 }
3026 }
3027 }
3028
3029 /*
3030 * This function is supposed to be called on basis of PE from top
3031 * to bottom style. So the the I/O or MMIO segment assigned to
3032 * parent PE could be overridden by its child PEs if necessary.
3033 */
3034 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3035 {
3036 struct pci_dev *pdev;
3037 int i;
3038
3039 /*
3040 * NOTE: We only care PCI bus based PE for now. For PCI
3041 * device based PE, for example SRIOV sensitive VF should
3042 * be figured out later.
3043 */
3044 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3045
3046 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3047 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3048 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3049
3050 /*
3051 * If the PE contains all subordinate PCI buses, the
3052 * windows of the child bridges should be mapped to
3053 * the PE as well.
3054 */
3055 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3056 continue;
3057 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3058 pnv_ioda_setup_pe_res(pe,
3059 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3060 }
3061 }
3062
3063 #ifdef CONFIG_DEBUG_FS
3064 static int pnv_pci_diag_data_set(void *data, u64 val)
3065 {
3066 struct pci_controller *hose;
3067 struct pnv_phb *phb;
3068 s64 ret;
3069
3070 if (val != 1ULL)
3071 return -EINVAL;
3072
3073 hose = (struct pci_controller *)data;
3074 if (!hose || !hose->private_data)
3075 return -ENODEV;
3076
3077 phb = hose->private_data;
3078
3079 /* Retrieve the diag data from firmware */
3080 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3081 phb->diag_data_size);
3082 if (ret != OPAL_SUCCESS)
3083 return -EIO;
3084
3085 /* Print the diag data to the kernel log */
3086 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3087 return 0;
3088 }
3089
3090 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3091 pnv_pci_diag_data_set, "%llu\n");
3092
3093 #endif /* CONFIG_DEBUG_FS */
3094
3095 static void pnv_pci_ioda_create_dbgfs(void)
3096 {
3097 #ifdef CONFIG_DEBUG_FS
3098 struct pci_controller *hose, *tmp;
3099 struct pnv_phb *phb;
3100 char name[16];
3101
3102 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3103 phb = hose->private_data;
3104
3105 /* Notify initialization of PHB done */
3106 phb->initialized = 1;
3107
3108 sprintf(name, "PCI%04x", hose->global_number);
3109 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3110 if (!phb->dbgfs) {
3111 pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3112 __func__, hose->global_number);
3113 continue;
3114 }
3115
3116 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3117 &pnv_pci_diag_data_fops);
3118 }
3119 #endif /* CONFIG_DEBUG_FS */
3120 }
3121
3122 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3123 {
3124 struct pci_dev *dev = bus->self;
3125 struct pci_bus *child;
3126
3127 /* Empty bus ? bail */
3128 if (list_empty(&bus->devices))
3129 return;
3130
3131 /*
3132 * If there's a bridge associated with that bus enable it. This works
3133 * around races in the generic code if the enabling is done during
3134 * parallel probing. This can be removed once those races have been
3135 * fixed.
3136 */
3137 if (dev) {
3138 int rc = pci_enable_device(dev);
3139 if (rc)
3140 pci_err(dev, "Error enabling bridge (%d)\n", rc);
3141 pci_set_master(dev);
3142 }
3143
3144 /* Perform the same to child busses */
3145 list_for_each_entry(child, &bus->children, node)
3146 pnv_pci_enable_bridge(child);
3147 }
3148
3149 static void pnv_pci_enable_bridges(void)
3150 {
3151 struct pci_controller *hose;
3152
3153 list_for_each_entry(hose, &hose_list, list_node)
3154 pnv_pci_enable_bridge(hose->bus);
3155 }
3156
3157 static void pnv_pci_ioda_fixup(void)
3158 {
3159 pnv_pci_ioda_setup_PEs();
3160 pnv_pci_ioda_setup_iommu_api();
3161 pnv_pci_ioda_create_dbgfs();
3162
3163 pnv_pci_enable_bridges();
3164
3165 #ifdef CONFIG_EEH
3166 pnv_eeh_post_init();
3167 #endif
3168 }
3169
3170 /*
3171 * Returns the alignment for I/O or memory windows for P2P
3172 * bridges. That actually depends on how PEs are segmented.
3173 * For now, we return I/O or M32 segment size for PE sensitive
3174 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3175 * 1MiB for memory) will be returned.
3176 *
3177 * The current PCI bus might be put into one PE, which was
3178 * create against the parent PCI bridge. For that case, we
3179 * needn't enlarge the alignment so that we can save some
3180 * resources.
3181 */
3182 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3183 unsigned long type)
3184 {
3185 struct pci_dev *bridge;
3186 struct pci_controller *hose = pci_bus_to_host(bus);
3187 struct pnv_phb *phb = hose->private_data;
3188 int num_pci_bridges = 0;
3189
3190 bridge = bus->self;
3191 while (bridge) {
3192 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3193 num_pci_bridges++;
3194 if (num_pci_bridges >= 2)
3195 return 1;
3196 }
3197
3198 bridge = bridge->bus->self;
3199 }
3200
3201 /*
3202 * We fall back to M32 if M64 isn't supported. We enforce the M64
3203 * alignment for any 64-bit resource, PCIe doesn't care and
3204 * bridges only do 64-bit prefetchable anyway.
3205 */
3206 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3207 return phb->ioda.m64_segsize;
3208 if (type & IORESOURCE_MEM)
3209 return phb->ioda.m32_segsize;
3210
3211 return phb->ioda.io_segsize;
3212 }
3213
3214 /*
3215 * We are updating root port or the upstream port of the
3216 * bridge behind the root port with PHB's windows in order
3217 * to accommodate the changes on required resources during
3218 * PCI (slot) hotplug, which is connected to either root
3219 * port or the downstream ports of PCIe switch behind the
3220 * root port.
3221 */
3222 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3223 unsigned long type)
3224 {
3225 struct pci_controller *hose = pci_bus_to_host(bus);
3226 struct pnv_phb *phb = hose->private_data;
3227 struct pci_dev *bridge = bus->self;
3228 struct resource *r, *w;
3229 bool msi_region = false;
3230 int i;
3231
3232 /* Check if we need apply fixup to the bridge's windows */
3233 if (!pci_is_root_bus(bridge->bus) &&
3234 !pci_is_root_bus(bridge->bus->self->bus))
3235 return;
3236
3237 /* Fixup the resources */
3238 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3239 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3240 if (!r->flags || !r->parent)
3241 continue;
3242
3243 w = NULL;
3244 if (r->flags & type & IORESOURCE_IO)
3245 w = &hose->io_resource;
3246 else if (pnv_pci_is_m64(phb, r) &&
3247 (type & IORESOURCE_PREFETCH) &&
3248 phb->ioda.m64_segsize)
3249 w = &hose->mem_resources[1];
3250 else if (r->flags & type & IORESOURCE_MEM) {
3251 w = &hose->mem_resources[0];
3252 msi_region = true;
3253 }
3254
3255 r->start = w->start;
3256 r->end = w->end;
3257
3258 /* The 64KB 32-bits MSI region shouldn't be included in
3259 * the 32-bits bridge window. Otherwise, we can see strange
3260 * issues. One of them is EEH error observed on Garrison.
3261 *
3262 * Exclude top 1MB region which is the minimal alignment of
3263 * 32-bits bridge window.
3264 */
3265 if (msi_region) {
3266 r->end += 0x10000;
3267 r->end -= 0x100000;
3268 }
3269 }
3270 }
3271
3272 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3273 {
3274 struct pci_controller *hose = pci_bus_to_host(bus);
3275 struct pnv_phb *phb = hose->private_data;
3276 struct pci_dev *bridge = bus->self;
3277 struct pnv_ioda_pe *pe;
3278 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3279
3280 /* Extend bridge's windows if necessary */
3281 pnv_pci_fixup_bridge_resources(bus, type);
3282
3283 /* The PE for root bus should be realized before any one else */
3284 if (!phb->ioda.root_pe_populated) {
3285 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3286 if (pe) {
3287 phb->ioda.root_pe_idx = pe->pe_number;
3288 phb->ioda.root_pe_populated = true;
3289 }
3290 }
3291
3292 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3293 if (list_empty(&bus->devices))
3294 return;
3295
3296 /* Reserve PEs according to used M64 resources */
3297 pnv_ioda_reserve_m64_pe(bus, NULL, all);
3298
3299 /*
3300 * Assign PE. We might run here because of partial hotplug.
3301 * For the case, we just pick up the existing PE and should
3302 * not allocate resources again.
3303 */
3304 pe = pnv_ioda_setup_bus_PE(bus, all);
3305 if (!pe)
3306 return;
3307
3308 pnv_ioda_setup_pe_seg(pe);
3309 switch (phb->type) {
3310 case PNV_PHB_IODA1:
3311 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3312 break;
3313 case PNV_PHB_IODA2:
3314 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3315 break;
3316 default:
3317 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3318 __func__, phb->hose->global_number, phb->type);
3319 }
3320 }
3321
3322 static resource_size_t pnv_pci_default_alignment(void)
3323 {
3324 return PAGE_SIZE;
3325 }
3326
3327 #ifdef CONFIG_PCI_IOV
3328 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3329 int resno)
3330 {
3331 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3332 struct pnv_phb *phb = hose->private_data;
3333 struct pci_dn *pdn = pci_get_pdn(pdev);
3334 resource_size_t align;
3335
3336 /*
3337 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3338 * SR-IOV. While from hardware perspective, the range mapped by M64
3339 * BAR should be size aligned.
3340 *
3341 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3342 * powernv-specific hardware restriction is gone. But if just use the
3343 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3344 * in one segment of M64 #15, which introduces the PE conflict between
3345 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3346 * m64_segsize.
3347 *
3348 * This function returns the total IOV BAR size if M64 BAR is in
3349 * Shared PE mode or just VF BAR size if not.
3350 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3351 * M64 segment size if IOV BAR size is less.
3352 */
3353 align = pci_iov_resource_size(pdev, resno);
3354 if (!pdn->vfs_expanded)
3355 return align;
3356 if (pdn->m64_single_mode)
3357 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3358
3359 return pdn->vfs_expanded * align;
3360 }
3361 #endif /* CONFIG_PCI_IOV */
3362
3363 /* Prevent enabling devices for which we couldn't properly
3364 * assign a PE
3365 */
3366 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3367 {
3368 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3369 struct pnv_phb *phb = hose->private_data;
3370 struct pci_dn *pdn;
3371
3372 /* The function is probably called while the PEs have
3373 * not be created yet. For example, resource reassignment
3374 * during PCI probe period. We just skip the check if
3375 * PEs isn't ready.
3376 */
3377 if (!phb->initialized)
3378 return true;
3379
3380 pdn = pci_get_pdn(dev);
3381 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3382 return false;
3383
3384 return true;
3385 }
3386
3387 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3388 int num)
3389 {
3390 struct pnv_ioda_pe *pe = container_of(table_group,
3391 struct pnv_ioda_pe, table_group);
3392 struct pnv_phb *phb = pe->phb;
3393 unsigned int idx;
3394 long rc;
3395
3396 pe_info(pe, "Removing DMA window #%d\n", num);
3397 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3398 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3399 continue;
3400
3401 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3402 idx, 0, 0ul, 0ul, 0ul);
3403 if (rc != OPAL_SUCCESS) {
3404 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3405 rc, idx);
3406 return rc;
3407 }
3408
3409 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3410 }
3411
3412 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3413 return OPAL_SUCCESS;
3414 }
3415
3416 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3417 {
3418 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3419 struct iommu_table *tbl = pe->table_group.tables[0];
3420 int64_t rc;
3421
3422 if (!weight)
3423 return;
3424
3425 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3426 if (rc != OPAL_SUCCESS)
3427 return;
3428
3429 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3430 if (pe->table_group.group) {
3431 iommu_group_put(pe->table_group.group);
3432 WARN_ON(pe->table_group.group);
3433 }
3434
3435 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3436 iommu_tce_table_put(tbl);
3437 }
3438
3439 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3440 {
3441 struct iommu_table *tbl = pe->table_group.tables[0];
3442 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3443 #ifdef CONFIG_IOMMU_API
3444 int64_t rc;
3445 #endif
3446
3447 if (!weight)
3448 return;
3449
3450 #ifdef CONFIG_IOMMU_API
3451 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3452 if (rc)
3453 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3454 #endif
3455
3456 pnv_pci_ioda2_set_bypass(pe, false);
3457 if (pe->table_group.group) {
3458 iommu_group_put(pe->table_group.group);
3459 WARN_ON(pe->table_group.group);
3460 }
3461
3462 iommu_tce_table_put(tbl);
3463 }
3464
3465 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3466 unsigned short win,
3467 unsigned int *map)
3468 {
3469 struct pnv_phb *phb = pe->phb;
3470 int idx;
3471 int64_t rc;
3472
3473 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3474 if (map[idx] != pe->pe_number)
3475 continue;
3476
3477 if (win == OPAL_M64_WINDOW_TYPE)
3478 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3479 phb->ioda.reserved_pe_idx, win,
3480 idx / PNV_IODA1_M64_SEGS,
3481 idx % PNV_IODA1_M64_SEGS);
3482 else
3483 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3484 phb->ioda.reserved_pe_idx, win, 0, idx);
3485
3486 if (rc != OPAL_SUCCESS)
3487 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3488 rc, win, idx);
3489
3490 map[idx] = IODA_INVALID_PE;
3491 }
3492 }
3493
3494 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3495 {
3496 struct pnv_phb *phb = pe->phb;
3497
3498 if (phb->type == PNV_PHB_IODA1) {
3499 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3500 phb->ioda.io_segmap);
3501 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3502 phb->ioda.m32_segmap);
3503 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3504 phb->ioda.m64_segmap);
3505 } else if (phb->type == PNV_PHB_IODA2) {
3506 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3507 phb->ioda.m32_segmap);
3508 }
3509 }
3510
3511 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3512 {
3513 struct pnv_phb *phb = pe->phb;
3514 struct pnv_ioda_pe *slave, *tmp;
3515
3516 list_del(&pe->list);
3517 switch (phb->type) {
3518 case PNV_PHB_IODA1:
3519 pnv_pci_ioda1_release_pe_dma(pe);
3520 break;
3521 case PNV_PHB_IODA2:
3522 pnv_pci_ioda2_release_pe_dma(pe);
3523 break;
3524 default:
3525 WARN_ON(1);
3526 }
3527
3528 pnv_ioda_release_pe_seg(pe);
3529 pnv_ioda_deconfigure_pe(pe->phb, pe);
3530
3531 /* Release slave PEs in the compound PE */
3532 if (pe->flags & PNV_IODA_PE_MASTER) {
3533 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3534 list_del(&slave->list);
3535 pnv_ioda_free_pe(slave);
3536 }
3537 }
3538
3539 /*
3540 * The PE for root bus can be removed because of hotplug in EEH
3541 * recovery for fenced PHB error. We need to mark the PE dead so
3542 * that it can be populated again in PCI hot add path. The PE
3543 * shouldn't be destroyed as it's the global reserved resource.
3544 */
3545 if (phb->ioda.root_pe_populated &&
3546 phb->ioda.root_pe_idx == pe->pe_number)
3547 phb->ioda.root_pe_populated = false;
3548 else
3549 pnv_ioda_free_pe(pe);
3550 }
3551
3552 static void pnv_pci_release_device(struct pci_dev *pdev)
3553 {
3554 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3555 struct pnv_phb *phb = hose->private_data;
3556 struct pci_dn *pdn = pci_get_pdn(pdev);
3557 struct pnv_ioda_pe *pe;
3558
3559 if (pdev->is_virtfn)
3560 return;
3561
3562 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3563 return;
3564
3565 /*
3566 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3567 * isn't removed and added afterwards in this scenario. We should
3568 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3569 * device count is decreased on removing devices while failing to
3570 * be increased on adding devices. It leads to unbalanced PE's device
3571 * count and eventually make normal PCI hotplug path broken.
3572 */
3573 pe = &phb->ioda.pe_array[pdn->pe_number];
3574 pdn->pe_number = IODA_INVALID_PE;
3575
3576 WARN_ON(--pe->device_count < 0);
3577 if (pe->device_count == 0)
3578 pnv_ioda_release_pe(pe);
3579 }
3580
3581 static void pnv_npu_disable_device(struct pci_dev *pdev)
3582 {
3583 struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
3584 struct eeh_pe *eehpe = edev ? edev->pe : NULL;
3585
3586 if (eehpe && eeh_ops && eeh_ops->reset)
3587 eeh_ops->reset(eehpe, EEH_RESET_HOT);
3588 }
3589
3590 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3591 {
3592 struct pnv_phb *phb = hose->private_data;
3593
3594 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3595 OPAL_ASSERT_RESET);
3596 }
3597
3598 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3599 .dma_dev_setup = pnv_pci_dma_dev_setup,
3600 .dma_bus_setup = pnv_pci_dma_bus_setup,
3601 .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported,
3602 .setup_msi_irqs = pnv_setup_msi_irqs,
3603 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3604 .enable_device_hook = pnv_pci_enable_device_hook,
3605 .release_device = pnv_pci_release_device,
3606 .window_alignment = pnv_pci_window_alignment,
3607 .setup_bridge = pnv_pci_setup_bridge,
3608 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3609 .shutdown = pnv_pci_ioda_shutdown,
3610 };
3611
3612 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3613 .dma_dev_setup = pnv_pci_dma_dev_setup,
3614 .setup_msi_irqs = pnv_setup_msi_irqs,
3615 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3616 .enable_device_hook = pnv_pci_enable_device_hook,
3617 .window_alignment = pnv_pci_window_alignment,
3618 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3619 .shutdown = pnv_pci_ioda_shutdown,
3620 .disable_device = pnv_npu_disable_device,
3621 };
3622
3623 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3624 .enable_device_hook = pnv_pci_enable_device_hook,
3625 .window_alignment = pnv_pci_window_alignment,
3626 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3627 .shutdown = pnv_pci_ioda_shutdown,
3628 };
3629
3630 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3631 u64 hub_id, int ioda_type)
3632 {
3633 struct pci_controller *hose;
3634 struct pnv_phb *phb;
3635 unsigned long size, m64map_off, m32map_off, pemap_off;
3636 unsigned long iomap_off = 0, dma32map_off = 0;
3637 struct resource r;
3638 const __be64 *prop64;
3639 const __be32 *prop32;
3640 int len;
3641 unsigned int segno;
3642 u64 phb_id;
3643 void *aux;
3644 long rc;
3645
3646 if (!of_device_is_available(np))
3647 return;
3648
3649 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3650
3651 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3652 if (!prop64) {
3653 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3654 return;
3655 }
3656 phb_id = be64_to_cpup(prop64);
3657 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3658
3659 phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
3660 if (!phb)
3661 panic("%s: Failed to allocate %zu bytes\n", __func__,
3662 sizeof(*phb));
3663
3664 /* Allocate PCI controller */
3665 phb->hose = hose = pcibios_alloc_controller(np);
3666 if (!phb->hose) {
3667 pr_err(" Can't allocate PCI controller for %pOF\n",
3668 np);
3669 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3670 return;
3671 }
3672
3673 spin_lock_init(&phb->lock);
3674 prop32 = of_get_property(np, "bus-range", &len);
3675 if (prop32 && len == 8) {
3676 hose->first_busno = be32_to_cpu(prop32[0]);
3677 hose->last_busno = be32_to_cpu(prop32[1]);
3678 } else {
3679 pr_warn(" Broken <bus-range> on %pOF\n", np);
3680 hose->first_busno = 0;
3681 hose->last_busno = 0xff;
3682 }
3683 hose->private_data = phb;
3684 phb->hub_id = hub_id;
3685 phb->opal_id = phb_id;
3686 phb->type = ioda_type;
3687 mutex_init(&phb->ioda.pe_alloc_mutex);
3688
3689 /* Detect specific models for error handling */
3690 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3691 phb->model = PNV_PHB_MODEL_P7IOC;
3692 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3693 phb->model = PNV_PHB_MODEL_PHB3;
3694 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3695 phb->model = PNV_PHB_MODEL_NPU;
3696 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3697 phb->model = PNV_PHB_MODEL_NPU2;
3698 else
3699 phb->model = PNV_PHB_MODEL_UNKNOWN;
3700
3701 /* Initialize diagnostic data buffer */
3702 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3703 if (prop32)
3704 phb->diag_data_size = be32_to_cpup(prop32);
3705 else
3706 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3707
3708 phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
3709 if (!phb->diag_data)
3710 panic("%s: Failed to allocate %u bytes\n", __func__,
3711 phb->diag_data_size);
3712
3713 /* Parse 32-bit and IO ranges (if any) */
3714 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3715
3716 /* Get registers */
3717 if (!of_address_to_resource(np, 0, &r)) {
3718 phb->regs_phys = r.start;
3719 phb->regs = ioremap(r.start, resource_size(&r));
3720 if (phb->regs == NULL)
3721 pr_err(" Failed to map registers !\n");
3722 }
3723
3724 /* Initialize more IODA stuff */
3725 phb->ioda.total_pe_num = 1;
3726 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3727 if (prop32)
3728 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3729 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3730 if (prop32)
3731 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3732
3733 /* Invalidate RID to PE# mapping */
3734 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3735 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3736
3737 /* Parse 64-bit MMIO range */
3738 pnv_ioda_parse_m64_window(phb);
3739
3740 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3741 /* FW Has already off top 64k of M32 space (MSI space) */
3742 phb->ioda.m32_size += 0x10000;
3743
3744 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3745 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3746 phb->ioda.io_size = hose->pci_io_size;
3747 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3748 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3749
3750 /* Calculate how many 32-bit TCE segments we have */
3751 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3752 PNV_IODA1_DMA32_SEGSIZE;
3753
3754 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3755 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3756 sizeof(unsigned long));
3757 m64map_off = size;
3758 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3759 m32map_off = size;
3760 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3761 if (phb->type == PNV_PHB_IODA1) {
3762 iomap_off = size;
3763 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3764 dma32map_off = size;
3765 size += phb->ioda.dma32_count *
3766 sizeof(phb->ioda.dma32_segmap[0]);
3767 }
3768 pemap_off = size;
3769 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3770 aux = memblock_alloc(size, SMP_CACHE_BYTES);
3771 if (!aux)
3772 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
3773 phb->ioda.pe_alloc = aux;
3774 phb->ioda.m64_segmap = aux + m64map_off;
3775 phb->ioda.m32_segmap = aux + m32map_off;
3776 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3777 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3778 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3779 }
3780 if (phb->type == PNV_PHB_IODA1) {
3781 phb->ioda.io_segmap = aux + iomap_off;
3782 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3783 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3784
3785 phb->ioda.dma32_segmap = aux + dma32map_off;
3786 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3787 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3788 }
3789 phb->ioda.pe_array = aux + pemap_off;
3790
3791 /*
3792 * Choose PE number for root bus, which shouldn't have
3793 * M64 resources consumed by its child devices. To pick
3794 * the PE number adjacent to the reserved one if possible.
3795 */
3796 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3797 if (phb->ioda.reserved_pe_idx == 0) {
3798 phb->ioda.root_pe_idx = 1;
3799 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3800 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3801 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3802 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3803 } else {
3804 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3805 }
3806
3807 INIT_LIST_HEAD(&phb->ioda.pe_list);
3808 mutex_init(&phb->ioda.pe_list_mutex);
3809
3810 /* Calculate how many 32-bit TCE segments we have */
3811 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3812 PNV_IODA1_DMA32_SEGSIZE;
3813
3814 #if 0 /* We should really do that ... */
3815 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3816 window_type,
3817 window_num,
3818 starting_real_address,
3819 starting_pci_address,
3820 segment_size);
3821 #endif
3822
3823 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3824 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3825 phb->ioda.m32_size, phb->ioda.m32_segsize);
3826 if (phb->ioda.m64_size)
3827 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3828 phb->ioda.m64_size, phb->ioda.m64_segsize);
3829 if (phb->ioda.io_size)
3830 pr_info(" IO: 0x%x [segment=0x%x]\n",
3831 phb->ioda.io_size, phb->ioda.io_segsize);
3832
3833
3834 phb->hose->ops = &pnv_pci_ops;
3835 phb->get_pe_state = pnv_ioda_get_pe_state;
3836 phb->freeze_pe = pnv_ioda_freeze_pe;
3837 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3838
3839 /* Setup MSI support */
3840 pnv_pci_init_ioda_msis(phb);
3841
3842 /*
3843 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3844 * to let the PCI core do resource assignment. It's supposed
3845 * that the PCI core will do correct I/O and MMIO alignment
3846 * for the P2P bridge bars so that each PCI bus (excluding
3847 * the child P2P bridges) can form individual PE.
3848 */
3849 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3850
3851 switch (phb->type) {
3852 case PNV_PHB_NPU_NVLINK:
3853 hose->controller_ops = pnv_npu_ioda_controller_ops;
3854 break;
3855 case PNV_PHB_NPU_OCAPI:
3856 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3857 break;
3858 default:
3859 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3860 hose->controller_ops = pnv_pci_ioda_controller_ops;
3861 }
3862
3863 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3864
3865 #ifdef CONFIG_PCI_IOV
3866 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3867 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3868 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3869 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3870 #endif
3871
3872 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3873
3874 /* Reset IODA tables to a clean state */
3875 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3876 if (rc)
3877 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc);
3878
3879 /*
3880 * If we're running in kdump kernel, the previous kernel never
3881 * shutdown PCI devices correctly. We already got IODA table
3882 * cleaned out. So we have to issue PHB reset to stop all PCI
3883 * transactions from previous kernel. The ppc_pci_reset_phbs
3884 * kernel parameter will force this reset too. Additionally,
3885 * if the IODA reset above failed then use a bigger hammer.
3886 * This can happen if we get a PHB fatal error in very early
3887 * boot.
3888 */
3889 if (is_kdump_kernel() || pci_reset_phbs || rc) {
3890 pr_info(" Issue PHB reset ...\n");
3891 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3892 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3893 }
3894
3895 /* Remove M64 resource if we can't configure it successfully */
3896 if (!phb->init_m64 || phb->init_m64(phb))
3897 hose->mem_resources[1].flags = 0;
3898 }
3899
3900 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3901 {
3902 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3903 }
3904
3905 void __init pnv_pci_init_npu_phb(struct device_node *np)
3906 {
3907 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
3908 }
3909
3910 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3911 {
3912 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
3913 }
3914
3915 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3916 {
3917 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3918 struct pnv_phb *phb = hose->private_data;
3919
3920 if (!machine_is(powernv))
3921 return;
3922
3923 if (phb->type == PNV_PHB_NPU_OCAPI)
3924 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
3925 }
3926 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
3927
3928 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3929 {
3930 struct device_node *phbn;
3931 const __be64 *prop64;
3932 u64 hub_id;
3933
3934 pr_info("Probing IODA IO-Hub %pOF\n", np);
3935
3936 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3937 if (!prop64) {
3938 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3939 return;
3940 }
3941 hub_id = be64_to_cpup(prop64);
3942 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3943
3944 /* Count child PHBs */
3945 for_each_child_of_node(np, phbn) {
3946 /* Look for IODA1 PHBs */
3947 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3948 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3949 }
3950 }
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